JPH03211767A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To compensate the drop of capacitor capacity accompanying integration improvement of a DRAM so as to secure enough capacitor capacity by removing a third insulating film from the place where a third conductor film is removed selectively, and forming a gap part between it and a second conductor film. CONSTITUTION:A third polysilicon film 10 is patterned at the time of formation of a lower capacitor electrode, and also an insulating film 8 is removed with the third polysilicon film 10 and a second polysilicon film 7 as etching barrier films. At this time, a gap 13 is formed between the second polysilicon film 7 and the third polysilicon film 10. As a result, a lower capacitor electrode 12 is formed in the shape of having a gap 13, and an upper capacitor electrode is made inside in the shape of entering the this gap 13 through a capacitor insulting film 14. By making use of the inside of the gap 13, the opposition area between the lower capacitor electrode 12 and the upper capacitor electrode 15 can be increased, whereby always enough capacitor capacity can be secured.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor memory device, and particularly relates to a method for manufacturing a semiconductor memory device, and in particular, a dynamic RA having a stacked capacitor cell.
The present invention relates to a method of manufacturing M (hereinafter referred to as DRAM).

(Prior Art) As DRAMs continue to become more highly integrated, the area of capacitors decreases, causing serious problems such as erroneous reading of memory contents and data destruction due to radiation. In order to solve these problems, proposals have been made to provide capacitors with various structures. One of these is a stacked capacitor cell structure.

Hereinafter, a conventional method for manufacturing a stacked capacitor cell will be described with reference to the drawings.

FIGS. 3(a) to 3(c) are cross-sectional views showing a conventional method for manufacturing a stacked capacitor cell in the order of manufacturing steps, focusing in particular on a capacitor cell for one bit.

First, as shown in FIG. 3(a), for example, a field insulating film 10 is formed on a p-type semiconductor substrate 101 by selective oxidation.
2 is formed to perform element isolation.

Next, a first thermal oxide film, which will become the gate insulating film 103, is formed on the surface of the element region by a thermal oxidation method. Next, a first polysilicon layer that will become word lines 104 is deposited over the entire surface by CVD. Next, the first polysilicon layer is patterned into a predetermined word line 104 (104+, 1042) shape by photolithography using photoresist. Next, using the patterned word line 104 and the field insulation 5111102 as a mask, a predetermined n-type impurity for forming the source/drain diffusion layer 105 is ion-implanted into the semiconductor substrate 101 and activated, thereby forming an n-type impurity. Source/drain diffusion layer 10
5 (1051, 1052) is formed.

Next, as shown in FIG. 3(b), a first interlayer insulating film 106 is deposited over the entire surface by CVD. Next, the n-type source/drain diffusion layer 10 is formed on the first interlayer insulating film 106 by photolithography using a photoresist.
A contact hole 107 communicating with 5□ is opened.

Next, as shown in FIG. 3(c), a second polysilicon layer that will become the lower capacitor electrode 108 is deposited over the entire surface by CVD. Next, the second polysilicon layer is patterned into a predetermined shape of lower capacitor electrode 108 by photolithography using photoresist. Next, a capacitor insulating film 109 made of a silicon oxide film, which will serve as the dielectric of the capacitor, is formed on the surface of the lower capacitor electrode 108 by thermal oxidation. Next, a third polysilicon layer that will become the upper capacitor electrode 110 is deposited over the entire surface by CVD. Next, the third polysilicon layer is patterned into a predetermined shape of upper capacitor electrode 110 by photolithography using photoresist.

Next, a second interlayer insulating film 1 is formed on the entire surface by CVD method.
11 is deposited and formed. Next, the second interlayer insulating film 111 and the first
A contact hole 112 communicating with the n-type source/drain diffusion layer 1051 is opened in the interlayer insulating film 106 . Next, an aluminum layer that will become the bit line 113 is deposited over the entire surface by sputtering. Next, the aluminum layer is patterned into a predetermined bit line shape by photolithography using photoresist.

Conventional DRAM stacked capacitor cells have been manufactured by the manufacturing method described above.

However, in such a conventional manufacturing method, the following problems have arisen due to the progress of element miniaturization in recent years, that is, the improvement in the degree of DRAMO integration.

As the degree of integration of DRAM increases, semiconductor basic technology 101 and lower Ushi Yabashita Den I! ! The opening size of the contact hole 107 for connecting to ii108 becomes smaller. When the opening size of the contact hole 107 becomes smaller, the second polysilicon layer constituting the r-section capacitor electrode 108 is deposited on the periphery of the contact hole 107 with almost no step difference. In the cow Yabashita cell structure,
It is important to increase the capacitance of the capacitor in any way possible. Therefore, in the stacked capacitor cell structure, the step difference in the lower capacitor electrode 1080 that occurs at the periphery of the contact hole 107 also contributes greatly to the increase in capacitance. If it becomes smaller, the lower capacitor electrode 108 will be formed on the peripheral edge of the contact hole 107 with almost no step difference, so that it is no longer expected to increase the capacitance of the capacitor using the step difference. In order to avoid this problem, it is possible to create a step at the periphery of the contact hole 107 by reducing the thickness of the second polysilicon layer. However, with this method, since the second polysilicon layer is thin, a problem arises in that it is not possible to increase the capacitor capacitance using the sidewalls of the lower capacitor electrode 108.

(Problem to be solved by the invention) This invention was made in view of the points mentioned in the previous Jd.
The purpose of this is to compensate for the decrease in capacitor capacity due to the high integration of DRAMs, and to always ensure sufficient capacitor capacity.
? It is an object of the present invention to provide a stacked capacitor cell structure, and to provide a method for manufacturing a semiconductor memory device using the same.

[Structure of the Invention] (Means for Solving the Problems) The first method for manufacturing a semiconductor memory device of the present invention includes (a)
a step of forming an element isolation region on a semiconductor substrate of a first conductivity type; a step of forming a first insulating film in the element isolation region of the substrate; a step of forming a first conductor film on the entire surface; a step of patterning a first conductor film into a predetermined gate electrode pattern; and introducing impurities of a second conductivity type into the patterned first conductor film in a self-aligned manner into the element isolation region. A step of forming an eleventh second semiconductor region of two conductivity types, a step of forming a second insulating film on the entire surface, a step of forming a T12 conductor film on the entire surface, and a step of forming a third insulating film on the entire surface. a first insulating film that penetrates the third transparent film, the second conductive film, the second insulating film, and the first insulating film and communicates with one of the first and second semiconductor regions; forming a third conductive film over the entire surface including the first opening; applying a first photosensitive resin film over the entire surface; a step of patterning a first photosensitive resin film into a first photosensitive resin film pattern that covers at least the top of the first opening and its vicinity; and using the first photosensitive resin film pattern as a mask. a step of selectively removing the third conductor film; a step of removing the third insulating film including side etching using the second conductor film and the third conductor film as etching barrier films; selectively removing the second conductor film using the first photosensitive resin film pattern as a mask; removing the first photosensitive resin film pattern; and at least the exposed second and third conductor films. a step of forming a fourth insulating film on the entire surface of the conductor film, a step of forming a fourth conductor film on the entire surface including the side etched portion formed when the third insulating film was removed; a step of applying a photosensitive resin film; and a step of applying the second photosensitive resin film.
patterning the photosensitive resin film into an m2 photosensitive resin film pattern that covers at least the upper portions of the second and third conductor films; and patterning the fourth photosensitive resin film using the second photosensitive resin film pattern as a mask. a step of selectively removing the conductor film, a step of removing the second photosensitive resin film pattern, a step of forming a fifth insulating film on the entire surface, and a step of removing the fifth insulating film and the second insulating film. forming a second opening that penetrates the film and the first insulating film and communicates with the other of the first and second semiconductor regions; The method is characterized by comprising the following steps: forming a fifth conductor film; and patterning the fifth conductor into a bit line pattern.

The second method for manufacturing a semiconductor memory device according to the second invention is (b)
forming a device isolation region on a semiconductor substrate of a first conductivity type; forming a first insulating film in the device isolation region of the substrate; and forming a first conductive film on the entire surface. a step of patterning the first conductor film into a predetermined gate electrode pattern; and introducing an impurity of a second conductivity type into the patterned first conductor film in a self-aligned manner to form the device. a step of forming first and second semiconductor regions of a second conductivity type in the isolation region; a step of forming a second insulating film on the entire surface; a step of forming a second conductor film on the entire surface; forming a third insulating film in the first and second semiconductor regions; a step of forming a first opening leading to one side; a step of forming a third conductive film on the entire surface including the inside of the first opening; and a step of forming a first photosensitive resin film on the entire surface. a step of coating, and a step of applying the first
patterning the photosensitive resin film into a first photosensitive resin film pattern that covers at least the top of and the vicinity of the first opening, and patterning the photosensitive resin film pattern using the first photosensitive resin film pattern as a mask. a step of selectively removing the third conductor film of No. 3; a step of removing the third insulating film including side etching using the second conductor film and the third conductor film as etching barrier films; a step of removing the photosensitive resin film pattern; a step of forming a fourth insulating film on at least the exposed surfaces of the second and third conductor films; and a side etching portion formed when removing the third insulating film. a step of forming a fourth conductive film on the entire surface; a step of applying a second photosensitive resin film on the entire surface;
patterning the photosensitive resin film into a second photosensitive resin film pattern that covers at least an upper part of the third conductor film; and patterning the fourth conductor film using the second photosensitive resin film pattern as a mask. , a step of sequentially selectively removing a fourth insulating film and a second conductive film; a step of removing the second photosensitive resin film pattern; a step of forming a fifth insulating film on the entire surface; forming a second opening that penetrates the fifth insulating film, the second insulating film, and the first insulating film and communicates with the other of the first and second semiconductor regions; The method is characterized by comprising the steps of: forming a fifth conductor film on the entire surface including the inside of the second opening; and patterning the fifth conductor film into a bit line pattern.

Furthermore, in the method for manufacturing a semiconductor memory device described in item (a) or (b), the first hole opening step includes the step of forming the third insulating film, the second conductor film, and the second insulating film. and forming a first opening portion that penetrates the first insulating film and further penetrates one of the first and second semiconductor regions formed in the substrate and communicates with the internal region of the substrate. The first semiconductor memory device according to the present invention is characterized in that it is a step and a step of introducing an impurity of a second conductivity type into the inner surface of the internal region of the substrate exposed in the first opening. In the manufacturing method, first, an element isolation region is formed in a first conductivity type semiconductor substrate.

Next, a first insulating film that will become a gate insulating film is formed in the element isolation region of the substrate, and then a first conductive film that will become a gate electrode is formed.

Next, after patterning the first conductor film into a gate electrode pattern, impurities of the second conductivity type are introduced into the substrate in a self-aligned manner with respect to the gate electrode to form impurities of the second conductivity type that will become source/drain regions. 1. Form a second semiconductor region.

Next, after forming a second insulating film over the entire surface, a second conductive film is formed on the second insulating film, and a third insulating film is sequentially formed on the second conductive film.

Next, a first opening is formed through the third insulating film, the second conductive film, the second insulating film, and the first conductive film, and through which the first semiconductor region communicates.

This first opening portion connects the lower capacitor electrode and the source/
This is a contact hole for connecting to one of the drain regions.

Next, a third conductor film is formed on the entire surface. At this time, the third
The conductor film is formed in contact with the second conductor film within the first opening, and later the second and third conductor films will constitute a lower capacitor electrode.

Next, after applying a first photosensitive resin film to the entire surface, this first photosensitive resin film is patterned into a first photosensitive resin film pattern that covers the first opening and its vicinity. .

Next, the third conductive film is selectively removed using the first photosensitive resin film pattern as a mask. The third insulating film is exposed at this selectively removed portion.

Next, the third insulating film is removed using the second conductive film and the third conductive film as etching barrier films.

At this time, the third insulating film is side-etched between the third conductive film remaining under the photosensitive resin film pattern and the second conductive film, and a so-called gap portion is formed.

Next, the second conductor film is selectively removed using the first photosensitive resin film pattern as a mask.

Next, at least the second, including the inner surface of the gap portion,
A fourth insulating film is formed on the surface of the third conductor film.

This fourth insulating film becomes a capacitor insulating film.

Next, a fourth conductor film is formed including the inside of the gap portion.

This fourth conductive film will later become an upper capacitor electrode.

Next, after coating the entire surface with a second photosensitive resin film,
This second photosensitive resin film is patterned into a second photosensitive resin film pattern that covers above the second and third conductor films.

Next, the fourth conductive film is selectively removed using the second photosensitive resin film pattern as a mask.

Next, a fifth insulating film is formed over the entire surface. This is an insulating film generally called an interlayer insulating film.

Next, a second opening is formed that penetrates the fifth insulating film, the second insulating film, and the first insulating film and communicates with the second semiconductor region.

This second opening is a contact hole for connecting the bit line and the other source/drain region.

Next, after forming a fifth conductor film on the entire surface, this fifth conductor film is patterned into a bit line pattern to produce a DRAM having a stacked capacitor cell structure.
be completed.

With such a manufacturing method, as described above, when the third insulating film is removed from the location where the third conductor film has been selectively removed, it is etched with side etching. Therefore, a so-called gap portion is formed in which the second conductor film and the third conductor film face each other with a space in between.

As a result, the first manufacturing method provides a stacked capacitor cell structure in which the capacitance of the capacitor is increased by utilizing the inner surface of the gap portion, and a DRAM equipped with this can be easily manufactured.

In addition, in the second manufacturing method, the second conductive film and the third
When forming the lower capacitor electrode consisting of the conductor film,
Do not pattern both using the same mask.

In the second manufacturing method, the third conductor film is first patterned, and then the fourth conductor film (upper capacitor electrode) and the second conductor film are patterned using the same mask. There is.

As a result, the second manufacturing method provides a stacked capacitor cell structure that can increase capacitor capacity compared to the stacked capacitor cell structure produced by the first manufacturing method,
A DRAM equipped with this can be manufactured.

(Example) Hereinafter, a method for manufacturing a semiconductor memory device according to an example of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(g) are cross-sectional views showing the manufacturing method of the semiconductor memory device according to the first embodiment of the present invention in the order of the manufacturing steps. This is what I focused on and illustrated.

First, as shown in FIG. 1(a), a field insulating film 2 is formed on, for example, a p-type semiconductor substrate 1 by, for example, a selective oxidation method.
is formed to perform element isolation. Next, a first thermal oxide film, which will become the gate insulating film 3, is formed on the surface of the element region by, for example, a thermal oxidation method.

Next, the word line 4 is formed over the entire surface by, for example, the CVD method.
A first polysilicon film of (4, 4□) is deposited. Next, the first polysilicon film is coated with, for example, POC.
The phosphorus deposit is diffused by l3 to make it conductive (n-type). Next, the first polysilicon film is patterned into a predetermined word line (gate electrode) 4 (4+, 42) shape by, for example, photolithography using photoresist.

Next, using the patterned word line 4 and field insulating film 2 as a mask, a source/drain diffusion layer 5 is formed.
A predetermined n-type impurity for forming (5+, 52) is ion-implanted into the semiconductor substrate 1 and activated, thereby forming the n-type source/drain diffusion layer 5 (51, 52).

Next, as shown in FIG. 1(b), for example, CV
A first interlayer insulation @6 is deposited by method D. Next, a second polysilicon film 7, which will become a part of the lower capacitor electrode, is deposited by, for example, the CVD method. Next, the second polysilicon film 7 is made conductive (n-type) by depositing and diffusing phosphorus using POCl3, for example.

Next, an insulating film 8 is deposited by, for example, a CVD method.

Next, as shown in FIG. 1(c), the insulating film 8, the second polysilicon film 7, and the first interlayer insulating film 6 are penetrated (
If the first thermal oxide film remains, it also penetrates),
A first contact hole 9 communicating with the n-type source/drain diffusion layer 52 is opened.

Next, a third polysilicon film 10, which will become a part of the lower capacitor electrode, is deposited over the entire surface including the inside of the first contact hole 9 by, for example, the CVD method. Next, the third polysilicon film 10 is made conductive (n-type) by depositing and diffusing phosphorus using, for example, POCI.

Next, as shown in FIG. 1(d), a photoresist 11 is applied to the entire surface and patterned into a planar shape of a lower capacitor electrode covering at least the first opening and its vicinity. Next, using the patterned photoresist 11 as a mask, the third polysilicon film 10 is
For example, anisotropic etching is performed using the RIE method.

Note that the anisotropic etching by the RIE method described above is
After etching the polysilicon film 10, the insulating film 8 may also be etched.

Next, as shown in FIG. 1(e), the insulating film 8 is isotropically etched by, for example, the CDE method using the third polysilicon film 10 and the second polysilicon film as etching barrier films. . At this time, the second polysilicon film 7 and the third
A location where the polysilicon film 10 of
A so-called gap portion 13 is formed.

Next, as shown in FIG.
Anisotropic etching is performed using the E method.

Next, as shown in FIG. 1(g), a capacitor insulating film 14, which will become the dielectric of the capacitor, is formed on the surface of the lower capacitor electrode 12, including the inner surface of the gear 13, by, for example, a thermal oxidation method. Next, a fourth polysilicon film, which will become the upper capacitor electrode 15, is deposited over the entire surface by, for example, the CVD method. Next, the fourth polysilicon film is made conductive (made n-type) by depositing and diffusing phosphorus using, for example, POCl. Next, this fourth polysilicon film is patterned into the shape of an upper capacitor electrode having an opening above at least the source/drain diffusion layer 5 by photolithography using a photoresist. Next, a second interlayer insulating film 16 is deposited over the entire surface by, for example, a CVD method. Next, the n-type source/
Drain diffusion layer 5. A second contact hole 17 communicating with the second contact hole 17 is opened. Next, an aluminum layer that will become the bit line 18 is formed on the entire surface including the inside of the second contact hole 17 by, for example, sputtering, and this is applied to the predetermined bit line 18.
By patterning into a shape, a stacked capacitor cell portion of a DRAM is completed.

In the method for manufacturing a semiconductor memory device according to the first embodiment, the second polysilicon film 7 is formed on the substrate 1 via the first interlayer insulating film 6, and the second polysilicon film 7 is An insulating film 8 is formed overlying the silicon film 7 . A first contact hole 9 communicating with the source/drain diffusion layer 52 is formed through these 141 interlayer insulating films 6, second polysilicon film 7, and insulating film 8. Further, a third polysilicon film 10 is formed overlying the insulating film 8 including the inside of the contact hole 9. And the third polysilicon II! 10 is patterned into the shape of a lower capacitor electrode, and the insulating film 8 is removed using the third polysilicon film 10 and the second polysilicon film 7 as etching barrier films.

At this time, a gap portion 13 is formed between the second polysilicon film 7 and the third polysilicon film 10. As a result, the lower capacitor electrode 12 is formed in a shape with a gap portion 13, as shown in FIG. 1(e). The upper capacitor electrode is formed into the gear part 13 via the capacitor insulating film 14.

Therefore, by utilizing the inner surface of the gap portion 13, the lower capacitor electrode 12 and the upper capacitor electrode 1
This increases the area facing 5.

As a result, in the manufacturing method according to the first embodiment, even if the size of the contact hole 9 decreases as the degree of integration increases, the decrease in capacitance of the capacitor is compensated for, and sufficient capacitance is always ensured. The present invention provides a stacked capacitor cell structure, and provides a method for manufacturing a DRAM equipped with the same.

Next, a method for manufacturing a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIGS. 2(a) and 2(b).

FIG. 2(a) and FIG. 2(b) are cross-sectional views showing the manufacturing process order of a semiconductor memory device manufacturing method according to a second embodiment of the present invention. This diagram focuses on the following. Figure 2(a)
And in FIG. 2(b), the reference numerals in FIG. 1(
It corresponds to a) to FIG. 1(g).

The manufacturing steps up to FIG. 2(a) are similar to the steps shown in FIGS. 1(a) to 1(e) described in the first embodiment. Therefore, it will be omitted.

Next, as shown in FIG. 2(b), a capacitor insulating film 14, which will become the dielectric of the capacitor, is formed on the entire surface including the inner surface of the gear 13 by, for example, a thermal oxidation method. Next, a fourth polysilicon film, which will become the upper capacitor electrode 15, is deposited over the entire surface by, for example, the CVD method. Next, the fourth polysilicon film is made conductive (n-type) by depositing and diffusing phosphorus using, for example, P OCl 3 .

Next, this fourth polysilicon film is patterned into the shape of the upper capacitor electrode by photolithography using photoresist. At this time, etching is subsequently performed to etch the capacitor insulating film 14 and further pattern the third polysilicon film 12 in the shape of the lower capacitor electrode. Next, a second interlayer insulating film 16 is deposited over the entire surface by, for example, a CVD method. Next, a second contact hole 17 communicating with the n-type source/drain diffusion layer 51 is opened in the second living room insulating film 16 . Next, an aluminum layer that will become the bit line 18 is formed on the entire surface including the inside of the second contact hole 17 by, for example, sputtering, and is patterned into a predetermined shape of the bit line 18, thereby forming a capacitor during stacking of the DRAM.・The cell part is completed.

In this way, the second polysilicon film 7 may be patterned at the same time as the fourth polysilicon film 15.

The method for manufacturing a semiconductor memory device according to the second embodiment also provides the same effects as the first embodiment.

Moreover, in the case of the manufacturing method according to the second embodiment, the second polysilicon film 7, which will become the lower capacitor electrode, and the fourth polysilicon film 15, which will become the upper capacitor electrode, are patterned at the same time. The facing area increases further.

As a result, the manufacturing method according to the second embodiment provides a stacked capacitor cell structure that can achieve a further increase in capacitor capacity, and a DR equipped with this structure.
This is the manufacturing method for AM.

In addition, in the manufacturing method of the first and second embodiments, the contact hole 9 for the n-type source/drain diffusion layer 5 is opened in such a way that the contact hole 9 forms a groove in the substrate 1. It may be made with holes. For example, the contact hole 9 is formed to penetrate the source/drain diffusion layer 52 formed in the substrate 1 and reach the inner region of the substrate 1.

A contact hole 9 reaches the inner region within the substrate 1.
After forming a hole, a diffusion layer of the same conductivity type as the source/drain diffusion layer 5° is formed on the inner surface where the internal region is exposed, so as to be integrated with the source/drain diffusion layer 5□.

The method for forming this diffusion layer is an ion implantation method, a two-step diffusion method from a glass layer or doped oxide containing impurities, or a third polysilicon film deposited later.

According to such a manufacturing method, a so-called trench-type capacitor cell structure is further used, so a capacitor cell structure that can further increase the capacitor capacity is provided, and a method for manufacturing a DRAM equipped with the same is provided. Become.

[Effects of the Invention] As explained above, according to the present invention, the DRAM
In order to improve the degree of integration of f't', a stacked capacitor cell structure is provided that compensates for a decrease in capacitance and can always ensure sufficient capacitor capacity, and a method of manufacturing a semiconductor memory device equipped with the same is provided. Ru.

[Brief explanation of drawings]

1(a) to 1(g) are cross-sectional views showing the method for manufacturing a semiconductor memory device according to the first embodiment of the present invention in the order of manufacturing steps, and FIG. 2(a) to FIG. b)
FIG.
) to 3(c) are cross-sectional views showing the conventional method for manufacturing a semiconductor memory device in the order of manufacturing steps. 1...p-type semiconductor substrate, 2...field insulating film,
3... Gate insulating film, 414□... Word line, 5,
52... N-type source/drain diffusion layer, 6... First interlayer insulating film, 7... Second polysilicon film, 8...
...Insulating film, 9...First contact hole, 10...
Third polysilicon film, 11... Photoresist, 12
... lower capacitor electrode, 13 ... gap, 14
... Capacitor insulating film, 15... Fourth polysilicon film (upper capacitor electrode) 16... Second interlayer insulating film, 17... Second contact hole, 18... Bit line.

Claims (3)

[Claims] (1) A step of forming an element isolation region on a semiconductor substrate of a first conductivity type, a step of forming a first insulating film in the element formation region of the substrate, and a step of forming a first conductor film on the entire surface. and patterning the first conductor film into a predetermined gate electrode pattern; and introducing impurities of a second conductivity type into the patterned first conductor film in a self-aligned manner to form the element. a step of forming first and second semiconductor regions of a second conductivity type within the region; a step of forming a second insulating film over the entire surface; a step of forming a second conductor film over the entire surface; forming a third insulating film; penetrating the third insulating film, the second conductor film, the second insulating film, and the first insulating film, and forming a third insulating film in one of the first and second semiconductor regions; forming a first aperture leading to the first aperture, forming a third conductive film on the entire surface including the first aperture, and applying a first photosensitive resin film on the entire surface. and the step of
patterning the photosensitive resin film into a first photosensitive resin film pattern that covers at least the top of and the vicinity of the first opening, and patterning the photosensitive resin film pattern using the first photosensitive resin film pattern as a mask. a step of selectively removing the third conductive film of No. 3, and a step of removing the third insulating film including side etching using the second conductive film and the third conductive film as etching barrier films; selectively removing the second conductor film using the photosensitive resin film pattern as a mask; removing the first photosensitive resin film pattern; and removing at least the exposed second and third conductors. a step of forming a fourth insulating film on the surface of the film; a step of forming a fourth conductor film on the entire surface including the side etched portion formed when removing the third insulating film; and a step of exposing the entire surface to a second photosensitive layer. a step of applying a synthetic resin film, and a step of applying the second
patterning the photosensitive resin film into a second photosensitive resin film pattern that covers at least above the second and third conductor films; and using the second photosensitive resin film pattern as a mask, patterning the fourth photosensitive resin film. a step of selectively removing the conductor film; a step of removing the second photosensitive resin film pattern; a step of forming a fifth insulating film on the entire surface; forming a second opening that penetrates an insulating film and the first insulating film and communicates with the other of the first and second semiconductor regions; 1. A method for manufacturing a semiconductor memory device, comprising: forming a fifth conductor film; and patterning the fifth conductor film into a bit line pattern. (2) Forming an element isolation region on a first conductivity type semiconductor substrate; Forming a first insulating film in the element formation region of the substrate; Forming a first conductive film over the entire surface. and patterning the first conductor film into a predetermined gate electrode pattern; and introducing impurities of a second conductivity type into the patterned first conductor film in a self-aligned manner to form the element. a step of forming first and second semiconductor regions of a second conductivity type within the region; a step of forming a second insulating film over the entire surface; a step of forming a second conductor film over the entire surface; forming a third insulating film; penetrating the third insulating film, the second conductor film, the second insulating film, and the first insulating film, and forming a third insulating film in one of the first and second semiconductor regions; forming a first aperture leading to the first aperture, forming a third conductive film over the entire surface including the inside of the first aperture, and applying a first photosensitive resin film over the entire surface. and the step of
patterning the photosensitive resin film into a first photosensitive resin film pattern that covers at least the top of and the vicinity of the first opening, and patterning the photosensitive resin film pattern using the first photosensitive resin film pattern as a mask. a step of selectively removing the third conductive film of No. 3, and a step of removing the third insulating film including side etching using the second conductive film and the third conductive film as etching barrier films; a step of removing the photosensitive resin film pattern; a step of forming a fourth insulating film on at least the exposed surfaces of the second and third conductor films; and a side etching portion formed when removing the third insulating film. a step of forming a fourth conductive film on the entire surface; a step of applying a second photosensitive resin film on the entire surface;
patterning the photosensitive resin film into a second photosensitive resin film pattern that covers at least an upper part of the third conductor film; and patterning the fourth conductor film using the second photosensitive resin film pattern as a mask. , a step of sequentially selectively removing a fourth insulating film and a second conductive film; a step of removing the second photosensitive resin film pattern; a step of forming a fifth insulating film on the entire surface; forming a second opening that penetrates the fifth insulating film, the second insulating film, and the first insulating film and communicates with the other of the first and second semiconductor regions; A semiconductor memory device comprising: forming a fifth conductor film on the entire surface including the inside of the second opening; and patterning the fifth conductor film into a bit line pattern. Production method. (3) The first opening step includes penetrating the third insulating film, the second conductor film, the second insulating film, and the first insulating film, and further forming the hole in the substrate. forming a first opening that penetrates one of the first and second semiconductor regions and communicates with the substrate internal region, and the substrate internal region that is exposed within the first opening. 3. The method of manufacturing a semiconductor memory device according to claim 1, wherein the step includes introducing an impurity of a second conductivity type into the inner surface.