JPH03211740A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03211740A JPH03211740A JP692190A JP692190A JPH03211740A JP H03211740 A JPH03211740 A JP H03211740A JP 692190 A JP692190 A JP 692190A JP 692190 A JP692190 A JP 692190A JP H03211740 A JPH03211740 A JP H03211740A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- adhesive layer
- terminal member
- polyimide
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 239000012790 adhesive layer Substances 0.000 claims abstract description 38
- 239000004642 Polyimide Substances 0.000 claims abstract description 33
- 229920001721 polyimide Polymers 0.000 claims abstract description 33
- 230000001070 adhesive effect Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000000853 adhesive Substances 0.000 claims abstract description 16
- 229920006332 epoxy adhesive Polymers 0.000 claims abstract description 9
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 claims abstract 2
- 239000004020 conductor Substances 0.000 claims description 20
- 239000010410 layer Substances 0.000 abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 4
- 238000010030 laminating Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 9
- 230000006866 deterioration Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004575 stone Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000006096 absorbing agent Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
多数の端子を有するため半導体素子とインナーリードと
の間に中継部材となるターミナル部材を設けてなる半導
体装置に関し、
多端子を有する半導体素子に対しても十分な強痕を持っ
てワイヤーボンディングを行いつるターミナル部材を有
した半導体ｉｓを提供することを目的とし、
一端が半導体素子に形成されたパッドにワイヤーボンデ
ィングされると共に、他端がインナーリードにワイヤー
ボンディングされる導体パターンが形成されてなり、リ
ードフレームステージ上に配設されたターミナル部ｌを
具備してなる゛Ｖ導体装置において、該ターミナル部材
を第１の接着剤層、ポリイミド系基板、第２の接着剤層
、ポリイミド系接着剤層を順次積層し、該第１の接着剤
層及び第２の接着剤層を少なくともゴム添加１ボキシ系
接着剤またはゴム添加ノ■ノール系接肴剤により構成し
た構成とする。[Detailed Description of the Invention] [Summary] Regarding a semiconductor device that has a large number of terminals and is provided with a terminal member that serves as a relay member between a semiconductor element and an inner lead, the present invention is also suitable for a semiconductor element that has a large number of terminals. The purpose is to provide a semiconductor IS that has a terminal member that performs wire bonding with strong traces, one end of which is wire bonded to a pad formed on a semiconductor element, and the other end of which is wire bonded to an inner lead. In a V-conductor device comprising a terminal portion l disposed on a lead frame stage, the terminal member is bonded to a first adhesive layer, a polyimide substrate, a second An adhesive layer and a polyimide adhesive layer are sequentially laminated, and the first adhesive layer and the second adhesive layer are made of at least a rubber-added boxy adhesive or a rubber-added no-nol adhesive. The configuration is as follows.
また、該ターミナル部材はポリイミド系接着剤層のみか
ら構成してもよい。Further, the terminal member may be composed only of a polyimide adhesive layer.
（産業上の利用分野〕
本発明は半導体装置に係り、特に多数の端子をｈするた
め半導体装ｆとインナーリードとの間に中継材となるタ
ーミナル部材を設けてなる事導体ＳＩｔ訂に関する。(Industrial Field of Application) The present invention relates to a semiconductor device, and more particularly to a conductor SIt in which a terminal member serving as a relay material is provided between a semiconductor device f and an inner lead in order to connect a large number of terminals.
近年、半導体素子の高集積化、半導体装置の多ビン化等
に藍求に伴い、小型半導体集子を多ピン半導体装置に搭
載した構成のものが提供されている。2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated and semiconductor devices have increased in number of bins, structures in which small semiconductor chips are mounted on multi-pin semiconductor devices have been provided.
この場合、インナーリードの先端をワイヤーボンディン
グ可能な位置まで半導体素子のパッドに近づける必要が
ある。しかるに、端子数が多くなるとインナーリードの
先端の間隔が狭くなり現在のリードフレーム加工技術（
エツチング、プレス等）ではワイヤーボンディングに耐
え得る強度をＮ￥ｉしつつインナーリードの先端を半導
体素子に近づけることが不可能となってきている。In this case, it is necessary to bring the tip of the inner lead close to the pad of the semiconductor element to a position where wire bonding is possible. However, as the number of terminals increases, the distance between the tips of the inner leads becomes narrower, and current lead frame processing technology (
(etching, pressing, etc.), it has become impossible to bring the tips of inner leads close to semiconductor elements while maintaining sufficient strength to withstand wire bonding.
そこで、このような半導体装置を現在のワイヤーボンデ
ィング技術で製造するため、半導体装ｆとインナーリー
ドとの間に導体パターンを右するターミナル部材（中継
部材）を設け、このターミナル部材を介してインナーリ
ードと半導体素子を接続することが行なわれている。具
体的には、インナーリードの先端とターミナル部材の導
体パターンの一端をワイヤーボンディングすると共に、
導体パターンの他端と半導体素子のパッドとをワイヤー
ボンディングすることが行われている。Therefore, in order to manufacture such a semiconductor device using current wire bonding technology, a terminal member (relay member) that connects the conductor pattern is provided between the semiconductor device f and the inner lead, and the inner lead is connected through this terminal member. Connecting semiconductor devices to semiconductor devices is being carried out. Specifically, while wire-bonding the tip of the inner lead and one end of the conductor pattern of the terminal member,
Wire bonding is performed between the other end of a conductor pattern and a pad of a semiconductor element.
このように、ターミナル部材は二度のワイヤーボンディ
ングが行われる為、これに耐え得る十分な強度を有する
必要がある。As described above, since the terminal member is subjected to wire bonding twice, it is necessary to have sufficient strength to withstand the wire bonding.
上記のようにターミノ−ル部材はワイヤーボンディング
の安定性を確保するため、絶縁部材としである程度の硬
度を為し、また熱変質（熱変形、熱軟化）の少ない材質
を使用する必要がある。As mentioned above, in order to ensure the stability of wire bonding, the terminal member must be an insulating member, have a certain degree of hardness, and be made of a material that is less susceptible to thermal deterioration (thermal deformation, thermal softening).
従来では、このターミナル部材としてガラスエポキシ材
を用いていた。Conventionally, a glass epoxy material has been used as this terminal member.
しかるに、ガラスエポキシ材よりなるターミナル部材で
は、ガラス１ポー１シ材の耐熱情が低いため、次のよう
な問題点があった。即ち端子数が多くなることによりイ
ンナーリードの先端部が少幅。However, the terminal member made of glass epoxy material has the following problems because the glass epoxy material has low heat resistance. In other words, as the number of terminals increases, the tip of the inner lead becomes narrower.
肉薄となった場合、このインナーリード先端部に十分な
強度をもってワイヤーボンディングしようとした場合、
２００℃以上の温度でワイへ７−ボンディングする必要
があるが、この湿度ではガラス１ボギシ材は熱変質して
しまい、４分な強度をもってワイヤーボンディングを行
うことが出来ないという課題があった。If you try to wire bond to the tip of this inner lead with sufficient strength,
It is necessary to perform wire bonding at a temperature of 200° C. or higher, but at this humidity, the glass material deteriorates due to heat, and there is a problem in that wire bonding cannot be performed with sufficient strength.
本発明は上記の点に鑑みてなされたものであり、多端ｆ
を有する半導体装ｆに対しても十分な強度を持ってワイ
ヤーボンディングを行いうるターミナル部材を有した半
導体装置を提供することを目的とする。The present invention has been made in view of the above points, and the present invention has been made in view of the above points.
It is an object of the present invention to provide a semiconductor device having a terminal member that can perform wire bonding with sufficient strength even for a semiconductor device f having a semiconductor device f.
上記課題を解決するために、本発明では、一端が半導体
装Ｉ（１）に形成されたパッド（２）にワイヤーボンデ
ィングされると共に、他端がインナーリード（３）にワ
イヤーボンディングされる導体パターン（４）が形成さ
れてなり、リードフレームステージ（１２）上に配設さ
れるターミナル部材（５，１０）を具備してなる半導体
装置において、
上記ターミナル部材（５）を第１の接着剤層（６）、ポ
リイミド系基板（７）、ゴム添加エポキシ系接着剤層（
８）、第２の接着剤層〈９）を順次積層し、
上記第１の接着剤層（６）及び第２の接着剤層（８）を
少なくともゴム添加１−ボｔ−シ系接着剤またはゴム添
加フェノール系接着剤により構成したことを特徴とする
ものである１゜
また、十記ターミブル部材（１０）はポリイミド系接着
剤腑のみから構成してもよい。In order to solve the above problems, the present invention provides a conductor pattern whose one end is wire-bonded to a pad (2) formed on a semiconductor device I (1) and whose other end is wire-bonded to an inner lead (3). (4) is formed, and is provided with terminal members (5, 10) disposed on a lead frame stage (12). (6), polyimide substrate (7), rubber-added epoxy adhesive layer (
8), the second adhesive layer (9) is sequentially laminated, and the first adhesive layer (6) and the second adhesive layer (8) are made of at least a rubber-added 1-bottom adhesive. Alternatively, the terminal member (10) may be composed of only a polyimide adhesive.
〔信用）
上記の構成において、ゴム添加１ボ１シ系接看剤または
ゴム添加フェノール系接着剤よりなる第１の接着剤層（
６）はリードル−ムステージ（１２）とポリイミド系す
板（７）とを接着させる。また、ゴム添加■−ボ１シ系
接石剤また（、ｔゴム添加）１ノール系接盾剤よりなる
第２の接着剤層（８）は、密名竹の悪いポリイミド系基
板（７）とポリイミド系１８肴剤〈９）とを密着さける
機能を央する。更に、ポリイミド系接着剤（９〉は、導
体パターン（４）の接＠竹を向上させるために配設され
ている。[Credit] In the above configuration, the first adhesive layer (
Step 6) is to bond the lead lume stage (12) and the polyimide base plate (7). In addition, the second adhesive layer (8) consisting of a rubber-added ■-bond type stone contact agent or (t-rubber-added) 1-nor type stone contact agent is made of a polyimide-based substrate (7) with a bad name. The main function is to avoid close contact with polyimide-based 18 appetizers (9). Furthermore, a polyimide adhesive (9) is provided to improve the adhesion of the conductor pattern (4).
また、ポリイミド系基板（７）は熱膨張係数が小さく、
高い硬度を有し、かつ耐熱性に優れている。４Ｊ１せて
、他の接着剤層等も耐熱性、密着性に優れた材質が選定
されている。よって、高い温度でワイヤーボンディング
を行っても熱変質は発生せず、多端ｆ含有する半導体素
子のワイヤーボンディング処理に十分対応することがで
きる。In addition, the polyimide substrate (7) has a small coefficient of thermal expansion,
It has high hardness and excellent heat resistance. 4J1 In addition, materials with excellent heat resistance and adhesion are selected for other adhesive layers and the like. Therefore, even if wire bonding is performed at a high temperature, thermal deterioration does not occur, and the wire bonding process of a semiconductor element containing multi-end f can be satisfactorily applied.
更に、厚みが薄くなりターミナル部材（１０）の製造工
程上で取り扱いが困難になるが、ポリイミド系接着剤の
みによりターミナル部材（１０）を構成してらよい。こ
の場合、ポリイミド系接着剤は絶縁基板としての機能を
も兼ねることになる。Furthermore, the terminal member (10) may be constructed only with a polyimide adhesive, although the thickness becomes thinner and handling becomes difficult during the manufacturing process of the terminal member (10). In this case, the polyimide adhesive also functions as an insulating substrate.
次に本発明の実施例について図面、と共に説明する。第
２図は本発明の一実施例である半導体装置１３を示して
いる。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows a semiconductor device 13 which is an embodiment of the present invention.
図中、１は半導体素子でありリードフレームステージ１
２上に搭載されている。この半導体装ｆ１は例えば１９
６〜２５６の端子を有し、この端子に対応する数のパッ
ド２が半導体装ｆ１の外周部分を囲繞するよう配設され
ている。また、リードフレームステージ１２はＦｅ−Ｎ
ｉ合金又はＣｕ合金よりなり、半導体装置１３の基板と
して！！！能するものである。In the figure, 1 is a semiconductor element and lead frame stage 1
It is installed on 2. This semiconductor device f1 is, for example, 19
It has 6 to 256 terminals, and a number of pads 2 corresponding to the terminals are arranged so as to surround the outer peripheral portion of the semiconductor device f1. In addition, the lead frame stage 12 is made of Fe-N
Made of i alloy or Cu alloy, as a substrate for semiconductor device 13! ! ! It is possible.
このリードフレームステージ１２上には上記の半導体素
子１と共に、ターミナル部材５が配設されている。ター
ミナル部材５は、後述するように耐熱性及び機械的強度
を有する構造とされているため、高温のワイヤーボンデ
ィングにも１分に耐えることが出来る。また、このター
ミプル部４１５は、半導体素子１を取り囲むように配設
されると共に、その上面には上記バッド２に対応する数
の導体パターン４が配設されている。On this lead frame stage 12, a terminal member 5 is arranged together with the semiconductor element 1 described above. Since the terminal member 5 has a structure having heat resistance and mechanical strength as described later, it can withstand high-temperature wire bonding for 1 minute. Further, this termiple portion 415 is arranged so as to surround the semiconductor element 1, and a number of conductor patterns 4 corresponding to the number of pads 2 are arranged on its upper surface.
インナーリード３は半導体索子１の電極たるパッド２を
パッケージの外部へ引き出すために設けられるものであ
り、半導体素子１及びターミナル部材５が配設されたリ
ードフレームステージ１２を囲繞するように設けられて
いる。また、ワイヤボンディングが行われるインナーリ
ード先端３ａはワイヤーボンディングに耐え得る範囲で
小幅、肉薄となるよう構成されている。The inner lead 3 is provided to draw out the pad 2, which is an electrode of the semiconductor cable 1, to the outside of the package, and is provided so as to surround the lead frame stage 12 on which the semiconductor element 1 and the terminal member 5 are arranged. ing. Further, the inner lead tip 3a to which wire bonding is performed is configured to have a small width and a thin wall to the extent that it can withstand wire bonding.
インブーリード３は、これと￥棚体索子１のバッド２と
を直接ワイヤーボンディングしようとした場合、インナ
ーリード先＄３ａをかなり小幅。If you try to directly wire bond the inboo lead 3 and the pad 2 of the yenbar body cord 1, the inner lead tip $3a will be quite narrow.
肉薄とする必要があるが、あまりにインナーリード先端
３ａを小幅、肉薄にするとワイヤーボンディングを行う
ことが出来なくなってしまう。It is necessary to make the inner lead tip 3a thin, but if the inner lead tip 3a is made too narrow and thin, wire bonding will not be possible.
即ち、ワイヤーボンディングの手段として一般に超音波
ボンディングが行われているが、インナーリード先端３
ａが小幅、肉薄となり機械的強度が低下すると、超名波
の振動に伴いインナーリード先端３ａも振動してしまい
ワイヤーボンディングが出来なくなってしまう。よって
、インナーリード先端３ａの小幅化、ＷＩ型化には限界
が生じてしまう。また、バッド２とインナーリード先端
３ａとの距離を大きくとることもワイヤーボンディング
装置の性能上、限界がある（実用上３．０ｔｎｍが限界
である）。That is, although ultrasonic bonding is generally performed as a means of wire bonding, the tip 3 of the inner lead
If a becomes narrow and thin and its mechanical strength decreases, the inner lead tip 3a will also vibrate with the vibration of the ultra-high wave, making wire bonding impossible. Therefore, there is a limit to reducing the width of the inner lead tip 3a and making it WI type. Further, there is also a limit to the performance of the wire bonding device when the distance between the pad 2 and the inner lead tip 3a is large (3.0 tnm is the practical limit).
従って、半導体装〒１のパッド数が多くなりインナーリ
ード先端３ａとパッド２とを直接ワイヤーボンディング
できなくなった場合には、中継部材として導体パターン
４が配設されたターミナル部材５をパッド２とインナー
リード先Ｑ５ａとの間に設（）る必要がある３、ｓ体パ
ターン４は硬度の高いターミナル部材５上に形成されて
いるため、小幅、肉薄としてもワイヤーボンディング時
に振動してしまうようなことはない。Therefore, when the number of pads in the semiconductor device 1 increases and direct wire bonding between the inner lead tip 3a and the pad 2 becomes impossible, the terminal member 5 on which the conductor pattern 4 is arranged as a relay member can be used as a relay member between the pad 2 and the inner lead. 3. The S-shaped pattern 4 that needs to be installed between the lead tip Q5a is formed on the terminal member 5 which has high hardness, so even if it is small in width and thin, it will not vibrate during wire bonding. There isn't.
パッド２と導体パターン４との間にはインリイドワイＡ
７１４がライ１フーボンデイングされ、また導体パター
ン４とインブーリード先端３ａとの間にはアウトリイド
ワイ１７１５がワイヤーボンディングされる。この時、
ターミナル部材５は半導体素子１を取り囲むように配設
されているため、半導体素子１はリードフレームステー
ジ１２土に自接搭叔され、パッド２と導体パターン４の
高さ位置は路間−の高さとなりワイヤーボンディングの
作業性が向上する。There is an indirect wire A between the pad 2 and the conductor pattern 4.
714 is wire bonded, and an out lead wire 1715 is wire bonded between the conductor pattern 4 and the inboo lead tip 3a. At this time,
Since the terminal member 5 is arranged so as to surround the semiconductor element 1, the semiconductor element 1 is self-attached to the lead frame stage 12, and the height positions of the pads 2 and the conductive patterns 4 are at the height of the path. This improves the workability of wire bonding.
続いて、本発明の要部となるターミナル部材５の構造に
ついて第１図４用いて説明する。同図（、良ターミナル
部材５の断面を示す図である、。Next, the structure of the terminal member 5, which is the main part of the present invention, will be explained using FIG. 1. This figure shows a cross section of a good terminal member 5.
同図に示されるように、ターミナル部材５はリードフレ
ームステージ１２上に設けられており、その上部に導体
パターン４が設けられている、２タ一ミブル部材５は、
１・部よりゴム添加エボ４シ系接肴剤層６（厚さ１５−
）１０ｎ）、ユービレックス（商標）等のポリイミド系
基板７（厚さ５０±８μ重）、ゴム添加エポキシ系接着
剤層８（厚さ９±３μＩ）、ポリイミド系接着剤層９（
厚さ２７±４μ−）を順次１層した構造とされている。As shown in the figure, the terminal member 5 is provided on the lead frame stage 12, and the two-terminal member 5 is provided with the conductive pattern 4 on the top thereof.
Rubber-added Evo 4-based adhesive layer 6 (thickness 15-
) 10n), polyimide substrate 7 (thickness 50±8 μl) such as Ubilex (trademark), rubber-added epoxy adhesive layer 8 (thickness 9±3 μl), polyimide adhesive layer 9 (
It has a structure in which one layer with a thickness of 27±4μ-) is sequentially formed.
１また、このターミナル部材５土に形成される導体パタ
ーン４はＣｕ箔１６（厚さ１８辷５μ１１＞上にＮｉメ
ツキ１７（１層腸以上）、Ａｕメツキ１８（厚さ２，５
層論以上）を順次形成した構造となっている。1 Also, the conductor pattern 4 formed on the soil of this terminal member 5 is a Cu foil 16 (thickness 18 x 5μ11), Ni plating 17 (one layer or more), Au plating 18 (thickness 2,5 μm)
It has a structure in which layers (more than layer theory) are formed sequentially.
上記のターミナル部材５を構成するゴム添加１ボキシ系
接暑剤層６は接＠竹の良くないリードフレームステージ
１２とポリイミド系基板７とを接着させる。また、ゴム
添加エポキシ系接着剤層８１．１、密着性の悪いポリイ
ミド系基板７とポリイミド系接着剤９とを密着させる機
能を秦する。更に、ポリイミド系接着剤９は、その上部
に配設されるＣＵ箔１６との接着性を向上させるために
配設されている。The rubber-added 1-boxy type heat absorbing agent layer 6 constituting the terminal member 5 adheres the lead frame stage 12, which has poor adhesion, to the polyimide type substrate 7. Further, the rubber-added epoxy adhesive layer 81.1 has the function of bringing the polyimide adhesive 9 into close contact with the polyimide substrate 7, which has poor adhesion. Further, the polyimide adhesive 9 is provided to improve adhesiveness with the CU foil 16 provided above.
また、ポリイミド系基板７はターミナル部材５の基部と
なるものである。このポリイミド系基板７は熱膨張係数
が小ざく、高い硬度を為し、かつ耐熱性に帰れている（
３００℃以十に耐え得る）。Further, the polyimide substrate 7 serves as the base of the terminal member 5. This polyimide-based substrate 7 has a small coefficient of thermal expansion, high hardness, and is heat resistant (
(Can withstand temperatures above 300℃).
併せて、他の接名剤層等６，８．９も耐熱性、密着性に
優れた材質が選定されている。よって、高い温度のワイ
ヤーボンディングを行ってもターミナル部材５に熱変質
−ま発す−せず、多端子を有する半導体素子１のワイヤ
ーボンディング処理に十分対応することができ、これに
より半導体装置１３の信頼性を向上することがでさる２
、この゛ｒ導体装置１３は、例えばトランスフン・−モ
ールド成形により樹脂封止成形される。In addition, materials with excellent heat resistance and adhesion are also selected for the other contact layers 6, 8.9. Therefore, even if high-temperature wire bonding is performed, the terminal member 5 does not undergo thermal deterioration, and can be fully used for wire bonding of the semiconductor element 1 having multiple terminals, thereby increasing the reliability of the semiconductor device 13. You can improve your sexuality 2
The conductor device 13 is molded by resin sealing, for example, by trans-funnel molding.
尚、上記の実施例ではターミナル部材５を半導体素子１
を取り囲むよう構成したが、第３図に示されるように、
上記構造と同一＃ｉ造を有するターミナル部材１９上に
半導体素子１を搭載した構成としてもよい。この場合、
ワイヤーボンディングのｎ業が若上面倒とはなるが、４
分に本願の効果を奏することができる。また、第４図に
示されるように、ターミナル部材５の外周にパテ等の接
着〜１２（ｌ塗布し、ターミナル部材５とリードフレー
ムステージ１２の密着性を向上させた構成としてもよい
。この半導体１！訂も例えば、トランスノ？−モールド
成形により封止樹脂３０のように封止成形される。また
、ゴム添加Ｔボ１シ系接着剤１１６．８は、いずれ心ゴ
ム添加フェノール系接着剤層に代えても、あるいはゴム
添加１ボ１シ系接着剤層とゴム添加）［ノール系接着剤
層とを重ねて用いても同様の効果が得られる。In the above embodiment, the terminal member 5 is connected to the semiconductor element 1.
However, as shown in Figure 3,
The semiconductor element 1 may be mounted on the terminal member 19 having the same #i structure as the above structure. in this case,
Although the wire bonding process may be troublesome, 4
The effects of the present application can be achieved in minutes. Alternatively, as shown in FIG. 4, a structure may be adopted in which adhesive or the like is applied to the outer periphery of the terminal member 5 to improve the adhesion between the terminal member 5 and the lead frame stage 12. For example, the rubber-added T-bottom adhesive 116.8 is also sealed by trans-no-mold molding like the sealing resin 30. The same effect can be obtained in place of the two layers, or by stacking one rubber-added adhesive layer and one rubber-added rubber-based adhesive layer.
第５図１ｊ本発明の第２実施例を示している。尚、第１
実施例と同一構成については同一符号を４＝Ｊ Ｌ。FIG. 5 1j shows a second embodiment of the invention. Furthermore, the first
For the same configuration as the embodiment, the same reference numeral is 4=JL.
てその説明を省略する。Therefore, the explanation will be omitted.
本実施例では、ターミナル部材１０として第１実施例に
おけるターミプル部０５よりゴム添加エポキシ系接着剤
層６．ポリイミド系基板７．ゴム添加エポキシ系接着剤
層８を取り除き、ポリイミド系接着剤層のみにより構成
したことを特徴とするものである。ポリイミド系接着剤
層はリードフレームステージ１２及びＣｕ箔１６との密
ＷＭは良好であり、かつワイヤーボンディングに１分に
耐えることができる耐熱性、硬度を有している。In this embodiment, a rubber-added epoxy adhesive layer 6. Polyimide substrate7. It is characterized in that the rubber-added epoxy adhesive layer 8 is removed and it is composed only of a polyimide adhesive layer. The polyimide adhesive layer has good tightness WM with the lead frame stage 12 and the Cu foil 16, and has heat resistance and hardness that can withstand wire bonding for 1 minute.
この構成の場合、ターミナル部材１０の厚みが薄くなり
ターミナル部材の製造■捏上で取り扱いが面倒となるが
、才導体装首の薄型化を行い冑る１゜尚、上記したポリ
イミド系基板７の材質としてコービレックスに代えてカ
プトン（商標）を用いることら考えられるが、カプトン
は熱膨張係数が大きいためワイヤーボンディング時にＳ
体パターンが剥がれる虞れがある。また、ポリイミド系
基板に代えてセラミックを用いることは可能であると思
われる。In the case of this configuration, the thickness of the terminal member 10 becomes thinner, making it difficult to handle during manufacturing and rolling of the terminal member. It is possible to use Kapton (trademark) instead of Corbilex as a material, but Kapton has a large coefficient of thermal expansion, so it is difficult to use S during wire bonding.
There is a risk that the body pattern may peel off. Furthermore, it seems possible to use ceramic instead of the polyimide substrate.
（発明の効果）
上述したように、本発明によれば、ターミナル部材はｆ
ツイヤ−ボンディング時に熱変質してしまうことはなく
、高い温度でワイヤーボンディングを実施できるため、
高集積化され多くのパッドを右した゛ｒ導体素ｆに対し
てし確実にワイヤーボンディングを行いうるため、半導
体装置の性能向上及び仁頼竹の向十庖図ることかでさ゛
る等の特長をｉする。(Effect of the invention) As described above, according to the present invention, the terminal member has f
There is no thermal deterioration during wire bonding, and wire bonding can be performed at high temperatures.
Since wire bonding can be performed reliably on a conductor element f that is highly integrated and has many pads, it has features such as improving the performance of semiconductor devices and increasing the number of semiconductor devices. i do
））１図は本発明の第１実施例である゛Ｌ導体装置に設
けられたターミナル部材の構造を説明するための図、
第２図は本発明の第１実施例である゛ｒ導体装ｄの斜視
図、
第３図及び第４図は第１実施例の変形例を説明するため
の図、
第５〕図は本発明の第２実施例である゛Ｖ導体装置に設
けられたターミナル部材の構造を説明づるｔ、：めの図
である。
図において、
１は゛Ｖ導体素子、
２（、ｉパッド、
３はインナーリード、
４は導体パターン、
５．１０はターミナル部材、
６はゴム添加■ポｔシ系接着剤層、
７はポリイミド系基板、
８はゴム添加圧ボＶシ系接石剤層、
９はポリイミド系接着剤層、
１２はリードフレームステージ
を小す。)) Figure 1 is a diagram for explaining the structure of the terminal member provided in the L conductor device which is the first embodiment of the present invention, and Figure 2 is the diagram for explaining the structure of the terminal member provided in the L conductor device which is the first embodiment of the present invention. d is a perspective view, FIGS. 3 and 4 are diagrams for explaining modifications of the first embodiment, and FIG. 5 is a terminal provided in a V-conductor device according to a second embodiment of the present invention. FIG. 2 is a diagram illustrating the structure of the member. In the figure, 1 is a V conductor element, 2 is an i-pad, 3 is an inner lead, 4 is a conductor pattern, 5.10 is a terminal member, 6 is a rubber-added pot adhesive layer, and 7 is a polyimide board. , 8 is a rubber added pressure V-type stone contact layer, 9 is a polyimide adhesive layer, and 12 is a small lead frame stage.
Claims (1)
）にワイヤーボンディングされると共に、他端がインナ
ーリード（３）にワイヤーボンディングされる導体パタ
ーン（４）が形成されてなり、リードフレームステージ
（１２）上に配設されたターミナル部材（５、１０）を
具備してなる半導体装置において、 該ターミナル部材（５）を第１の接着剤層 （６）、ポリイミド系基板（７）、第２の接着剤層（８
）、ポリイミド系接着剤層（９）を順次積層した構成と
し、 該第１の接着剤層（６）及び第２の接着剤層（８）を少
なくともゴム添加エポキシ系接着剤またはゴム添加フェ
ノール系接着剤により構成してなることを特徴とする半
導体装置。 （２）該ターミナル部材（１０）はポリイミド系接着剤
層のみから構成したことを特徴とする半導体装置。[Claims] (1) One end of a bat (2) formed on the semiconductor element (1).
), and a conductor pattern (4) whose other end is wire-bonded to the inner lead (3) is formed, and the terminal member (5, 10) arranged on the lead frame stage (12) ), the terminal member (5) is connected to a first adhesive layer (6), a polyimide substrate (7), and a second adhesive layer (8).
), polyimide adhesive layers (9) are sequentially laminated, and the first adhesive layer (6) and the second adhesive layer (8) are made of at least a rubber-added epoxy adhesive or a rubber-added phenol adhesive. A semiconductor device comprising an adhesive. (2) A semiconductor device characterized in that the terminal member (10) is composed only of a polyimide adhesive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP692190A JPH03211740A (en) | 1990-01-16 | 1990-01-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP692190A JPH03211740A (en) | 1990-01-16 | 1990-01-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03211740A true JPH03211740A (en) | 1991-09-17 |
Family
ID=11651709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP692190A Pending JPH03211740A (en) | 1990-01-16 | 1990-01-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03211740A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0677272A (en) * | 1992-08-26 | 1994-03-18 | Kyocera Corp | Semiconductor chip housing package |
| JP2011187841A (en) * | 2010-03-10 | 2011-09-22 | Renesas Electronics Corp | Electronic device, relay member, mounting substrate, and method of manufacturing electronic device |
| WO2016180671A1 (en) * | 2015-05-08 | 2016-11-17 | Rogers Germany Gmbh | Multilayer adhesive bond |
-
1990
- 1990-01-16 JP JP692190A patent/JPH03211740A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0677272A (en) * | 1992-08-26 | 1994-03-18 | Kyocera Corp | Semiconductor chip housing package |
| JP2011187841A (en) * | 2010-03-10 | 2011-09-22 | Renesas Electronics Corp | Electronic device, relay member, mounting substrate, and method of manufacturing electronic device |
| WO2016180671A1 (en) * | 2015-05-08 | 2016-11-17 | Rogers Germany Gmbh | Multilayer adhesive bond |
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