JPH03211731A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a short-circuit between wirings due to hillock and current leakage by providing substantially parallel slits on the side of an Al wiring at least on part of the wiring. CONSTITUTION:A plurality of slits 5 which are intermittently connected are provided along the side of an Al wiring 1, and the wiring 1 is separated in space into a relatively wide first part 6 and a relatively narrow second part 7. However, these parts are electrically connected to each other on a region on which the slit 5 is not formed. A hillock 4 is easily generated from the part 6, and scarcely generated from the part 7. Therefore, even if other Al wiring 2 is provided near the part 7, a short-circuit is not substantially generated by the hillock 4 generated from the second part. The hillock generated from the part 6 can be prevented from being brought into contact with other Al wiring by the part 7.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor device having an Al wiring, and more particularly to a semiconductor device having an Al wiring in which current leakage and short circuits between wirings are less likely to occur due to hillocks.

(Prior Art) AI (aluminum) is a material that has a low specific resistance and a relatively low contact resistance to a silicon semiconductor diffusion layer. For this reason, AI is widely used as a wiring material for semiconductor devices.

Typically, a material in which other elements such as Si are added to AI (A1 alloy) is used as a wiring material for semiconductor devices. Therefore, in this specification, AI also includes A1 alloy.

The melting point of AI is about 660°C. Many of the processes for manufacturing semiconductor devices using silicon semiconductors require processing at high temperatures exceeding the melting point of A1.

Therefore, the process of forming wiring made of AI (Al wiring) is performed after all such high-temperature processes are completed. However, after forming the Al wiring, a sintering process is required at a temperature of about 400° C. or higher for the purpose of reducing the resistance in the contact portion and making the contact characteristics ohmic.

As semiconductor devices become more highly integrated, the spacing between interconnects is decreasing and the total interconnect length is increasing. Under these circumstances, the multiplicity of wiring has become one of the most important factors for the reliability of the entire semiconductor device.

Regarding the reliability of the Al wiring, one of the problems is that protrusions (hillocks) are generated from the surface of the Al wiring due to the above-mentioned sintering process and the like. The A1 atoms in the A1 wiring easily move to relieve the stress applied to the wiring even at the processing temperature of the sintering process, causing hillocks. This hillock breaks through the interlayer insulating film and
It may even reach the wiring. In such a case, the hillocks may cause leaks between the Al wirings or short circuits between the Al wirings. Therefore, hillocks reduce the manufacturing yield of semiconductor devices.

Hillocks in the A1 wiring also occur and grow due to electromigration while the semiconductor device is in use. Therefore, hillocks also reduce the reliability of semiconductor devices.

Al wiring hillocks occur from wide Al wiring,
Easy to grow big. On the other hand, the possibility of hillocks occurring from narrow Al wiring is small.

Taking this characteristic into consideration, there is a layout method for Al interconnects in which the distance between a wide Al interconnect and the adjacent A1 interconnect is sufficiently wide.

FIG. 2 shows a plan view of essential parts of a semiconductor device for explaining this conventional A1 wiring layout method.

After a plurality of elements (not shown) consisting of various patterned layers are formed on a semiconductor substrate, those elements and an external system ( (not shown) are provided. Figure 2 shows such wiring,
A] Wiring 2 with a relatively wide wiring width where hillocks are likely to occur
1 and an adjacent Al wiring 22 with a relatively narrow wiring width.
and Al wiring 23 are shown.

In the area shown in FIG. 2, the distance between the wide Al wiring 21 and the narrow A1 wiring 22 is smaller than the distance between the narrow A1 wiring 22 and the narrow A1 wiring 23. It is widely designed. For this reason, if the wide A1 wiring 2
Even if a hillock 24 occurs on the surface of 1 and grows,
There is a low possibility that the tip of the groove 24 will reach the adjacent Al wiring 22. According to this layout, it is possible to prevent a decrease in manufacturing yield and reliability due to hillocks to some extent.

(Problems to be Solved by the Invention) However, the above-mentioned conventional technology has the following problems.

The conventional layout consists of a wide Al wiring 21 and an adjacent A
Since a large space is required between the l wiring 22,
It is not suitable for high integration of semiconductor devices.

The present invention has been made in order to solve the above problems, and its purpose is to provide an Al wiring that does not cause a decrease in reliability due to Hiro/I distortion and has an arrangement configuration suitable for high integration. An object of the present invention is to provide a semiconductor device having the following features.

(Means for Solving the Problems) A semiconductor device of the present invention is a semiconductor device having a plurality of A1 wirings, in which at least a part of the Al wirings is
The slits are provided substantially parallel to the sides of the wiring, thereby achieving the above objective.

(Example) The present invention will be described below with reference to Examples.

FIG. 1 shows a plan view of the main parts of a semiconductor device for explaining the layout of the Al wiring of this embodiment.

After a plurality of elements (not shown) consisting of various patterned layers are formed on a semiconductor substrate, those elements and an external system ( (not shown) are provided. Among such Al wirings, an Al wiring 1 having a relatively wide wiring width, and Al wirings 2 and 3 having relatively narrow wiring widths are shown in FIG.

One of the features of this embodiment is that the wide AI wiring 1 has a plurality of slits 5 that are intermittently connected along the side surface of the Al wiring 1.

In the area where the A1 wiring 1 has the slit 5, the slit 5 spatially separates the Al wiring 1 into a relatively wide first part 6 and a relatively narrow second part 7. has been done. However, these parts are electrically connected to each other in the region where the slit 5 is not formed.

Hillocks 4 tend to occur from the wide first portion 6 and are less likely to occur from the narrow second portion 7. For this reason,
Even if another Al wiring 2 is provided near the narrow second portion 7, short circuits are hardly caused by hillocks 4 generated from the second portion. Further, hillocks generated from the wide first portion 6 are prevented from coming into contact with other Al wirings by the narrow second portion 7. At this time, even if a hillock generated from the wide first part 6 comes into contact with the narrow second part 7, there is no problem because these parts are originally one wiring having the same potential. .

As described above, in this embodiment, by providing the slit 5 in the wide Al wiring 1, the groove 4 grows from the side surface of the wide AI wiring 1 and comes into contact with the adjacent A1 wiring 2. There is no need to put it away.

Therefore, short circuits and current leaks between Al wiring lines due to hillocks 4 do not occur, and the manufacturing yield and reliability of semiconductor devices are improved. Moreover, the distance between the wide Al wiring 1 and the adjacent other Al wiring 2 is reduced by the narrow Al wiring 2.
There is no need to make the distance larger than the distance between the A1 wiring 3 and the narrow A1 wiring 3. Therefore, the semiconductor device can be highly integrated or miniaturized.

In this embodiment, the slit 5 is formed only in a portion close to one side of the wide Al wiring, but the slit 5 may be formed in each portion close to both sides of the A1 wiring. In particular, when other Al wirings are provided close to each other on either side of a wide Al wiring, it is necessary to provide the slits 5 near each side of the wide Al wiring.

The slits 5 do not need to be formed in all regions along the wide Al wiring. It is only necessary to form the slit 5 in a region where a wide Al wiring and another Al wiring are close enough to each other that there is a possibility that they may come into contact with each other through a hillock 4.

(Effects of the Invention) As described above, according to the present invention, by providing slits in the relatively wide Al wiring where hillocks are likely to occur, hillocks can be removed from the side surfaces of the A and I wirings.

It is possible to prevent this from occurring. For this reason,
The manufacturing yield and reliability of the semiconductor device are improved without short circuits and current leaks between wiring lines due to hillocks. Moreover, since there is no need to provide a large distance between the wide Al wiring and other adjacent Al wiring, the semiconductor device can be highly integrated or miniaturized.

4. Nona:'8 Fig. 1 is a plan view showing an embodiment of the present invention, and Fig. 2 is a plan view showing a conventional example.

1.2.3...A I Arrangement 4-...Hillock,
5...Slit, 6...First part, 7...Second
part.

that's all

Claims (1)

[Claims] 1. A semiconductor device having a plurality of Al wirings, wherein at least a part of the Al wirings is provided with a slit substantially parallel to a side surface of the Al wirings. .