JPH03206629A - Metal mold for semiconductor resin-sealing - Google Patents

Metal mold for semiconductor resin-sealing

Info

Publication number
JPH03206629A
JPH03206629A JP190090A JP190090A JPH03206629A JP H03206629 A JPH03206629 A JP H03206629A JP 190090 A JP190090 A JP 190090A JP 190090 A JP190090 A JP 190090A JP H03206629 A JPH03206629 A JP H03206629A
Authority
JP
Japan
Prior art keywords
resin
mold
cavity
metal
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP190090A
Other languages
Japanese (ja)
Other versions
JP2600411B2 (en
Inventor
Toshiaki Shirouchi
俊昭 城内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2001900A priority Critical patent/JP2600411B2/en
Publication of JPH03206629A publication Critical patent/JPH03206629A/en
Application granted granted Critical
Publication of JP2600411B2 publication Critical patent/JP2600411B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Moulds For Moulding Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce that a sink on the surface of a package and a void at the inside are produced by a method wherein an air vent is formed as a three- layer structure or it is formed in a position which is symmetric with respect to a gate by using a semiconductor element as the center and the residual air remaining inside a cavity of a metal mold is reduced as far as possible at a resin injection operation. CONSTITUTION:Main metal molds 1a, 1b, a partitioning block 3 and a lead frame 4 are sandwiched and pressurized as shown in the crosssectional view at a resin injection operation; a molten resin 11 is injected into a lower metal- mold cavity and an upper metal-mold cavity 2a, 2b from a subrunner 6. At this time, the resin 11 which is injected forcibly is shaped in such a way that the tip is collapsed inside the cavities. An air layer 10 is left inside the upper metal-mold cavity 2b; it is discharged from an air vent 7 formed on the surface of the partitioning block 3 and is reduced to be very small. The resin 11 is filled completely into the lower metal-mold and upper metal mold cavities 2a, 2b and the resin-injection operation is finished. Thereby, it is possible to sharply reduce that a sink on the surface of a package and a void at the inside are produced in a molded product.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路素子(以下ICと称す)を樹脂
封止する為の封止用金型に関し、特に光学素子を透明樹
脂にて封止成形する半導体樹脂封止用金型に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a mold for sealing a semiconductor integrated circuit element (hereinafter referred to as IC) with a resin, and in particular to a mold for sealing an optical element with a transparent resin. The present invention relates to a semiconductor resin encapsulation mold for molding.

〔従来の技術〕[Conventional technology]

従来、この種の半導体樹脂封止用金型は、第4図の分解
斜視図および第5図の断面図に示すように、上型および
下型キャビティ2b,2aのエアー排出用通気孔(以下
エアーベント7と称す)が樹脂注入口(以下ゲートと称
す〉のある側面に対する反対側の側面の任意の位置で、
リードフレーム4の上面と底面とに接する上下それぞれ
の金型1b.1aの表面のみに形成されていた。また、
封止する半導体素子5が光素子の場合には、用いられる
透明樹脂の溶融粘度は、約3 0 0 poiseと通
常のIC封止用樹脂の約2 0 0 poiseに比べ
高いため、樹脂注入時のボンディングワイヤー流れを防
止する為に注入速度を通常のものの半分程度で行なって
いた. 〔発明が解決しようとする課題〕 上述した従来の半導体樹脂封止用金型は、リードフレー
ムに接する面にしかエアーベントが形成されていない.
また、樹脂注入時のワイヤー変形を防止する為に樹脂注
入速度を遅くする必要があり、通常、■個のキャビテイ
部に樹脂が流入し始めてから完全に充填されるまで10
秒以上かかつていた。
Conventionally, this type of mold for semiconductor resin encapsulation has air exhaust holes (hereinafter referred to as An air vent 7) is located at an arbitrary position on the side opposite to the side where the resin injection port (hereinafter referred to as gate) is located.
Upper and lower molds 1b in contact with the top and bottom surfaces of the lead frame 4. It was formed only on the surface of 1a. Also,
When the semiconductor element 5 to be encapsulated is an optical element, the melt viscosity of the transparent resin used is approximately 300 poise, which is higher than the approximately 200 poise of ordinary IC encapsulation resin. In order to prevent the bonding wire from flowing, the injection speed was approximately half that of the normal injection speed. [Problems to be Solved by the Invention] In the conventional semiconductor resin encapsulation mold described above, air vents are formed only on the surface that contacts the lead frame.
In addition, in order to prevent wire deformation during resin injection, it is necessary to slow down the resin injection speed, and it usually takes 10 minutes from the time the resin begins to flow into the ■ cavities until they are completely filled.
It was more than a second ago.

そうした場合、樹脂注入用の射出シリンダーによって強
制的にキャビティ部へ押し入れられた樹脂は、ゲートロ
からキャビテイ部を通過し反対側の側面へ到達する時に
第5図に示す樹脂11の如く流動し、上型キャビティ2
bに閉ざされた空気JWIOは排気孔を失い、最終的に
はICの外観にボイド或いはひけとなって現れ、不良と
なる要因の一つとなっていた。
In such a case, the resin forced into the cavity by the injection cylinder for resin injection flows as shown in the resin 11 shown in Fig. 5 when it passes through the cavity from the gatero and reaches the opposite side. mold cavity 2
The air JWIO trapped in b loses its exhaust hole and eventually appears as voids or sink marks on the external appearance of the IC, which is one of the causes of failure.

特に光半導体としては、こう言ったボイド、ひけによる
光の乱反射、屈折等が光学特性に直接悪影響を及ぼす為
問題となっていた。
Particularly for optical semiconductors, such voids and sink marks have caused problems, such as diffuse reflection and refraction of light, which have a direct negative effect on optical properties.

上述した従来の半導体樹脂封止用金型は、リードフレー
ムと接触する上金型と下金型の表面のみにエアーベント
を有しているのに対し、本発明は上金型のキャビティ部
側面の一部を成す部分を分割構造とし、その分割ブロッ
クの上型キャビティ部の上面高さに相当する部分にもエ
アーベントを設ける。そうすることにより、本封止用金
型は、リードフレームの下面,リードフレームの上面、
及びパッケージの上面の3層のエアーベントを有すると
いう相違点がある。
The conventional mold for semiconductor resin encapsulation described above has air vents only on the surfaces of the upper mold and lower mold that contact the lead frame, whereas the present invention has air vents on the side surface of the cavity part of the upper mold. A portion forming a part of the block is divided into a divided structure, and an air vent is also provided in a portion corresponding to the height of the upper surface of the upper mold cavity portion of the divided block. By doing so, the present sealing mold can be used on the bottom surface of the lead frame, the top surface of the lead frame,
The difference is that it has three layers of air vents on the top surface of the package.

また、エアーベントは、樹脂注入ゲートのゲート幅中心
点とリードフレームに搭載された半導体素子の中点とを
結ぶ延長線上に位置するという相違点を有する。
Another difference is that the air vent is located on an extension line connecting the center point of the gate width of the resin injection gate and the center point of the semiconductor element mounted on the lead frame.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体樹脂封止用金型は、下金型と、上金型と
、その中間に挾持される分割ブロックとからなる。下金
型には樹脂の流動経路になるランナー,サブランナー及
びゲートと、パッケージを形或するキャビティと、それ
ら凹部空間のエアー排出を行うためのエアーベントが形
或され、上金型には、下金型キャビティと相対する部分
にキャビティが形戒されている。そして、分割ブロック
は、上面及び底面に下金型と同等のエアーベントを有し
、下金型のガイドビンにより位置が固定される様になっ
ている。
The semiconductor resin encapsulation mold of the present invention includes a lower mold, an upper mold, and a divided block sandwiched between the lower mold and the upper mold. The lower mold is formed with runners, sub-runners, and gates that serve as flow paths for the resin, a cavity that forms the package, and air vents that discharge air from these recessed spaces. The cavity is shaped in the part facing the lower mold cavity. The divided blocks have air vents on the top and bottom surfaces similar to those of the lower mold, and are fixed in position by guide bins of the lower mold.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の実施例1の分解斜視図である。]aは
下金型,lbは上金型で3が分割ブロックである。下金
型1aには、図示しないランナーとサブランナー6,下
パッケージとなる下型キャビティ2a,及び深さ5μm
程度のエアーベント7が形成され、また、リードフレー
ム4を固定するためのリードフレームガイドビン8aと
、分割ブロック3を固定するためのガイドビン9aがそ
れぞれ植設されている。上金型1bには、ICの上パッ
ケージとなる部分の上型キャビテイ2bと、ガイドビン
逃げ穴9Cが形成されている。そして、分割ブロック3
には、上面と底面とに深さ5μm程度のエアーベント7
が形成されており、また、ガイド穴9b及びリードフレ
ームガイドビン逃げ穴8cがそれぞれ貫通されている。
FIG. 1 is an exploded perspective view of Embodiment 1 of the present invention. ]a is the lower mold, lb is the upper mold, and 3 is the divided block. The lower mold 1a includes a runner and a sub-runner 6 (not shown), a lower mold cavity 2a which becomes a lower package, and a depth of 5 μm.
In addition, a lead frame guide bin 8a for fixing the lead frame 4 and a guide bin 9a for fixing the divided block 3 are respectively implanted. The upper mold 1b is formed with an upper mold cavity 2b for a portion that will become the upper package of the IC, and a guide bin relief hole 9C. And divided block 3
Air vents 7 with a depth of approximately 5 μm are installed on the top and bottom surfaces.
A guide hole 9b and a lead frame guide bin relief hole 8c are respectively penetrated therethrough.

本金型1a,lb、分割ブロック3,及びリードフレー
ム4は、樹脂注入時は第2図の実施例1の機能部断面図
に示す如く挾持,加圧され、サブランナー6より溶融し
た樹脂11が下型および上型キャビティ2a,2bへ注
入されていく。その時、前述した通り強制的に注入され
た樹脂11は、キャビティ内にて先端が崩れた様な形状
となり、上型キャビティ2bに空気層10が残留するが
、分割ブロック3の上面に形威された前記エアーベント
7より排出され、樹脂11は下型および上型キャビティ
2a,2b全てに充填され、樹脂注入を終了する。
The molds 1a, lb, the divided blocks 3, and the lead frame 4 are clamped and pressurized as shown in the cross-sectional view of the functional parts of the first embodiment in FIG. is injected into the lower and upper mold cavities 2a and 2b. At that time, the resin 11 that was forcibly injected as described above has a shape in which the tip collapses inside the cavity, and the air layer 10 remains in the upper die cavity 2b, but the resin 11 is not formed on the upper surface of the divided block 3. The resin 11 is discharged from the air vent 7, and the resin 11 is filled into both the lower and upper mold cavities 2a and 2b, and the resin injection is completed.

次に本発明の実施例2について説明する。本実施例では
エアーベントの位置をある条件に基づき設定するもので
あり、第3図のパッケージ平面図を用いて説明する。ま
ず、パッケージ15の一辺に形戒されたゲートのゲート
幅に対する中心点12を点Aとする。またリードフレー
ムに搭載された半導体素子5の中点13を点Bとし、点
Aと点Bとを結ぶ延長線を仮想する。そうした場合、そ
の延長線とパッケージ15の他の一辺との交点を点Cと
し、C点を中心とした所定幅のエアーベントを形成する
ものである。
Next, a second embodiment of the present invention will be described. In this embodiment, the position of the air vent is set based on certain conditions, and will be explained using the package plan view of FIG. 3. First, point A is the center point 12 of the gate width defined on one side of the package 15. Further, the midpoint 13 of the semiconductor element 5 mounted on the lead frame is defined as a point B, and an extension line connecting points A and B is assumed. In such a case, the intersection of the extended line and the other side of the package 15 is set as a point C, and an air vent having a predetermined width centered at the point C is formed.

通常、この種の半導体素子の樹脂封入は、樹脂流入過程
においてゲートより注入された溶融樹脂がキャビティを
進行して充填されるわけであるが、厚さ約500μm程
度の半導体素子の上面及び下面においては、樹脂の流動
抵抗が他の部分に比べて大きいため進行速度が遅くなり
、溶融樹脂は、第3図に示す樹脂境界線l6の様な流動
形態を示す。この場合、半導体素子中点13の点Bを中
心としたゲートと対称な位置が最も樹脂到達が遅くなり
、その部分にエアーベントを設けることがボイド等の不
良削減に効果的である。
Normally, in this type of resin encapsulation of semiconductor devices, the molten resin injected from the gate advances through the cavity during the resin inflow process and is filled. Since the flow resistance of the resin is greater than that of other parts, the advancing speed is slow, and the molten resin exhibits a flow form like the resin boundary line 16 shown in FIG. 3. In this case, the resin reaches the slowest point at a position symmetrical to the gate around point B of the midpoint 13 of the semiconductor element, and providing an air vent at that position is effective in reducing defects such as voids.

但し本実施例は、もちろん実施例1と同様の3層エアー
ベントと併用して用いることによって、より多大な効果
が得られるのは言うまでもなく、また、本実施例に示す
位置以外にもエアーベントを追加で設けることは何らさ
しつかえない。
However, it goes without saying that this embodiment can be used in combination with a three-layer air vent similar to that of embodiment 1 to achieve even greater effects. There is nothing wrong with providing additional information.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、エアーベントを3層構造
にしたり、或いは半導体素子を中心にゲートと対称な位
置に設けることにより、樹脂注入時に金型のキャビティ
内に残留する空気を極力少なくすることができる。した
がって、戒形後の製品において、パッケージ表面のひけ
、及びパッケージ内部のボイド等の発生を大幅に軽減す
ることが可能である。
As explained above, the present invention minimizes the amount of air remaining in the mold cavity during resin injection by forming the air vent into a three-layer structure or by providing it in a position symmetrical to the gate with the semiconductor element in the center. be able to. Therefore, it is possible to significantly reduce the occurrence of sink marks on the package surface, voids, etc. inside the package in the packaged product.

特に光学素子においては、ごく微小な気泡やごみ等によ
っても感度劣化等が見られることからみても大幅な品質
向上となる。
This is a significant quality improvement, especially in optical elements, where even the smallest bubbles or dust can cause deterioration in sensitivity.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例1の分解斜視図、第2図は実施
例1の機能部断面図、第3図は本発明の実施例2のパッ
ケージ平面図、第4図は従来の金型の分解斜視図、第5
図は従来の金型の機能部断面図である。 1a・・・下金型、1b・・・上金型、2a・・・下型
キャビティ、2b・・・上型キャビティ、3・・・分割
ブロック、4・・・リードフレーム、5・・・半導体素
子、6・・・サブランナー 7・・・エアーベント、8
a・・・リードフレームガイトビン、8b・・・リード
フレームガイド穴、8C・・・リードフレームガイドピ
ン逃げ穴、9a・・・ガイドビン、9b・・・ガイド穴
、9c・・・ガイドピン逃げ穴、10・・・空気層、1
1・・・樹脂、12・・・ゲート中心点、l3・・・半
導体素子中点、14・・・エアーベント中心点、15・
・・パッケージ、16・・・樹脂境界線。
Fig. 1 is an exploded perspective view of Embodiment 1 of the present invention, Fig. 2 is a sectional view of functional parts of Embodiment 1, Fig. 3 is a plan view of the package of Embodiment 2 of the present invention, and Fig. 4 is a conventional metal Exploded perspective view of the mold, No. 5
The figure is a sectional view of a functional part of a conventional mold. 1a...Lower mold, 1b...Upper mold, 2a...Lower mold cavity, 2b...Upper mold cavity, 3...Divided block, 4...Lead frame, 5... Semiconductor element, 6... Sub-runner 7... Air vent, 8
a...Lead frame guide bin, 8b...Lead frame guide hole, 8C...Lead frame guide pin escape hole, 9a...Guide bin, 9b...Guide hole, 9c...Guide pin escape hole Hole, 10...air layer, 1
DESCRIPTION OF SYMBOLS 1... Resin, 12... Gate center point, l3... Semiconductor element center point, 14... Air vent center point, 15...
...Package, 16...Resin boundary line.

Claims (1)

【特許請求の範囲】 1、リードフレーム上に搭載された半導体素子を金属細
線にてボンディング後樹脂封止する為の上下一対の半導
体樹脂封止用金型において、キャビティ部のエアー排出
用通気孔を、上型キャビティの上面と同じ高さに位置す
る箇所に設けたことを特徴とする半導体樹脂封止用金型
。 2、キャビティ部のエアー排出用通気孔を、上型キャビ
ティの少なくとも樹脂注入口の中心と半導体素子の中心
とを結ぶ延長線上に位置する箇所に設けた請求項1記載
の半導体樹脂封止用金型。
[Scope of Claims] 1. In a pair of upper and lower semiconductor resin sealing molds for resin-sealing a semiconductor element mounted on a lead frame after bonding with a thin metal wire, a vent hole for air discharge in a cavity portion. A mold for semiconductor resin encapsulation, characterized in that: is provided at a location located at the same height as the top surface of an upper mold cavity. 2. The mold for semiconductor resin encapsulation according to claim 1, wherein the air discharge hole of the cavity portion is provided at a location of the upper mold cavity located on an extension line connecting at least the center of the resin injection port and the center of the semiconductor element. Type.
JP2001900A 1990-01-08 1990-01-08 Mold for semiconductor resin sealing Expired - Lifetime JP2600411B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001900A JP2600411B2 (en) 1990-01-08 1990-01-08 Mold for semiconductor resin sealing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001900A JP2600411B2 (en) 1990-01-08 1990-01-08 Mold for semiconductor resin sealing

Publications (2)

Publication Number Publication Date
JPH03206629A true JPH03206629A (en) 1991-09-10
JP2600411B2 JP2600411B2 (en) 1997-04-16

Family

ID=11514458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001900A Expired - Lifetime JP2600411B2 (en) 1990-01-08 1990-01-08 Mold for semiconductor resin sealing

Country Status (1)

Country Link
JP (1) JP2600411B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100583496B1 (en) * 2000-08-14 2006-05-24 앰코 테크놀로지 코리아 주식회사 Circuit board for semiconductor package

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182142A (en) * 1984-02-28 1985-09-17 Toshiba Corp Resin sealing mold for semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182142A (en) * 1984-02-28 1985-09-17 Toshiba Corp Resin sealing mold for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100583496B1 (en) * 2000-08-14 2006-05-24 앰코 테크놀로지 코리아 주식회사 Circuit board for semiconductor package

Also Published As

Publication number Publication date
JP2600411B2 (en) 1997-04-16

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