JPH03204940A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form respectively a high potential barrier at both ends of a channel region and to improve source/drain breakdown strengths by a method wherein the formation of ion-implanted layers for controlling a threshold voltage is performed by an obliquely rotating ion implantation method using a transfer gate electrode as a mask. CONSTITUTION:Boron ions which are P-type impurity ions identical with those in a semiconductor substrate 1 are obliquely implanted in the whole surface of the substrate 1 from the direction at a prescribed angle of inclination with respect to the direction normal to the substrate surface. Simultaneously with this, the substrate 1 is rotated centering around the normal of the center of a transfer gate electrode 5. By this obliquely rotational ion implantation method, P-type ion-implanted layers 4 for threshold voltage control use are formed using the electrode as a mask. It is desirable to set the angle of inclination for the ion implantation at 15 deg. or larger and 60 deg. or smaller and the ion implantation is normally performed at about 30 deg. or larger and about 45 deg. or smaller. Thereby, the concentration distribution of an impurity subsequent to diffusion can be made high remarkedly in the vicinities of a source and a drain at both ends of a channel region compared to that of the impurity in the vicinity of the center of the channel region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device.
S (Metal Oxide Sem1cond
uctor) type LDD (LightIyDoped
The present invention relates to a method of manufacturing a semiconductor device forming a drain structure transistor and other MO3 type transistors.

[Prior art] The basic structure of a MOg field effect transistor is as follows:
This is a so-called MOS capacitor in which a metal electrode is provided on an St substrate via a thin oxide film, and a source serving as a carrier supply source and a drain taking out carriers are arranged on both sides. The metal electrode on the oxide film has the function of controlling the conductance between the source and drain, and is therefore called a transfer gate electrode. The material used for this transfer gate electrode is often impurity-doped polysilicon or metal silicide formed by heat-treating a high-melting point metal such as tungsten deposited on polysilicon in an inert gas.

When the voltage of the transfer gate electrode (gate voltage) is lower than the threshold voltage Vth required to invert the conductivity type near the Si substrate surface (channel) between the source and drain, both the source and drain are separated by a pn junction. , and no current flows. When a gate voltage equal to or higher than Vth is applied, the conductivity type of the channel surface is reversed, a layer of the same conductivity type as the source/drain is formed in this portion, and a current flows between the source/drain.

By the way, if the impurity concentration distribution at the boundary between the source/drain and the channel changes rapidly, the electric field strength at this portion increases. This electric field gives carriers energy and generates so-called hot carriers. Then, these carriers are injected into the transfer gate insulating film, and interface states are generated at the interface between the transfer gate insulating film and the semiconductor substrate, or they are trapped in the transfer gate insulating film. Therefore, the threshold voltage and transconductance of the MOS transistor deteriorate during operation. This is a phenomenon in which the MOS transistor deteriorates due to hot carriers. Moreover, the so-called avalanche breakdown voltage against avalanche breakdown between the source and drain is also degraded by hot carriers. Therefore, the electric field strength is alleviated by lowering the n-type impurity concentration near the source/drain to moderate the change in concentration distribution. This allows M
The MO8 type LDD structure transistor suppresses deterioration of the transistor due to hot carriers and improves the avalanche breakdown voltage of the source/drain.

As a conventional method for manufacturing an MO8 type LDD structure transistor, there is a method shown in FIGS. 14A to 14F, for example. In this manufacturing method, first, so-called LOGO8 (Local Oxidation) is formed on the p-type semiconductor substrate 1.
A transfer gate oxide film 3 is formed in an element formation region surrounded by an element isolation insulating film 2 by a method (FIG. 14A). Next, in order to control the threshold voltage, p-type impurities such as boron ions are implanted into the entire surface of the semiconductor substrate 1 to form an ion implantation region 4 (14th
Figure B). After that, a polysilicon film is deposited on the entire surface of the transfer gate oxide film 3 by low pressure CVD method,
Transfer gate electrode 5 is formed by photolithography and reactive ion etching (FIG. 14C). As the transfer gate electrode 5, instead of polysilicon, high melting point metals such as tungsten, molybdenum, titanium, etc. or their silicides, and two types of polysilicon are used.
It may also be formed from a layered film. This transfer gate electrode 5 is doped with phosphorus ions to improve conductivity. In this case, the transfer gate electrode 5 becomes n-type, which is the same conductivity type as the channel, that is, the conductivity type of the source/drain.

Therefore, even when no gate voltage is applied to the transfer gate electrode 5, a positive gate voltage is effectively applied to the p-type channel surface due to the difference in work function between the n-type transfer gate electrode 5 and the p-type channel surface. A state is created in which it appears that the voltage is being applied. Furthermore, the n-type impurity doped in the transfer gate electrode 5 may diffuse into the p-type channel surface due to subsequent heat treatment. For these reasons, Vth decreases, and in some cases, an inversion layer may already be formed in the channel. Note that the above-mentioned ion implantation region 4 cancels the influence of impurity ions doped into the transfer gate electrode 5 by implanting all p impurities in advance.
This is to ensure the desired vth.

Next, using the gate electrode 5 as a mask, n-type impurities such as phosphorus ions and arsenic ions are implanted perpendicularly to the surface of the semiconductor substrate 1 to form an n-type ion implantation layer 6 (14th
Figure D). Thereafter, an insulating film such as silicon dioxide is deposited on the entire surface of the semiconductor substrate 1 by low pressure CVD or normal pressure CVD, and this is anisotropically etched to form sidewall spacers 7 (FIG. 14E). . Next, using the transfer gate electrode 5 and sidewall spacer 7 as a mask, n-type impurities such as phosphorus ions and arsenic ions are implanted perpendicularly to the surface of the semiconductor substrate 1, and n-type ions with a higher concentration than the ion implantation layer 6 are implanted. An injection layer 8 is formed (FIG. 14F). Thereafter, a heat treatment is performed to activate the implanted impurity ions, and an MO8 type LDD structure transistor is completed.

In the above conventional example, a p-type semiconductor substrate is used as the substrate, but a p-well, which is a region in which p-type impurities are implanted, may also be formed at least near the substrate surface. Further, as the substrate, an n-type semiconductor substrate or a substrate in which an n-well, which is a region in which n-type impurities are implanted at least near the surface, is formed may be used. In this case, the transfer gate electrode 5 is of p type, the ion implantation region 4 for threshold voltage control is of n type, and p type ion implantation layers 6.8 are formed in the source and drain regions.

In the conventional example described above, ions are implanted only from the direction perpendicular to the surface of the semiconductor substrate 1, so it is necessary to form the ion implantation region 4 for controlling the threshold voltage before forming the transfer gate electrode 5. On the other hand, as a method of forming each ion implantation layer after forming the transfer gate electrode 5 by applying the oblique ion implantation method, Japanese Patent Laid-Open No. 61-22696
Examples include those described in Publication No. 8. M described in the same bulletin
The method for manufacturing an O8 type semiconductor device is shown in FIGS. 15A to 15D.
Referring to the figure, first, a field oxide film 12 and a transfer gate electrode 1 are formed on a p-type semiconductor substrate 11.
4 as a mask, phosphorus ions are implanted at an acceleration voltage of 20 KeV to form an n-type region 18 (FIG. 15A). Next, using the gate electrode 14 as a mask, boron ions are applied at an incident angle of 3.
When the impurity is implanted at 0° and an acceleration voltage of 30 KeV, impurities are implanted in the front side of the impurity, and a p-type region is formed inside the n-type region 18 on the right side wall of the channel formation region directly under the transfer gate electrode 14 (15th B). figure). When similar inclined ion implantation is performed from the opposite side, p-type head regions 19a and 1 are formed to surround all sides and bottom surfaces of n-type region 18.
9b is formed (Figure 15C).

Next, a photoresist 20 is patterned and formed around the transfer gate electrode 14, and using this as a mask, arsenic ions are implanted at a high concentration to form an n-type region 21 that will become a source/drain (FIG. 15D). .

Finally, a silicon oxide film 22 is deposited on the entire surface using the CVD method, contact holes are formed at predetermined locations in each of the gate, source, and drain regions using a reactive ion etching method, etc., and aluminum is deposited on the entire surface using a sputtering method or a CVD method. By depositing and turning the deposited material, an n-channel MO8 type semiconductor device is completed.

As described above, according to this conventional example, since the p-type head regions 19a and 19b are formed by oblique ion implantation, each ion implantation layer is formed after the gate electrode 14 is formed.

[Problems to be Solved by the Invention] Among the conventional semiconductor device manufacturing methods described above, in the case of the first conventional example, by performing vertical ion implantation on the entire surface of the semiconductor substrate 1 before forming the transfer gate electrode 5. , an ion implantation region 4 which is a diffusion layer for threshold voltage control.
form. Therefore, p
The type impurity ion concentration distribution becomes almost uniform as shown by the broken line in the graph of FIG. Even after the thermal diffusion process, this tendency does not change significantly, resulting in a distribution as shown by the two-dot chain line in FIG. Since the threshold voltage is determined corresponding to the approximately average value of the channel potential of the entire channel region, when a predetermined threshold voltage is set, the average value of the concentration distribution of the ion implantation region 4 to be formed is also determined correspondingly. It will be done. In the first conventional example, the concentration distribution in the ion-implanted region 4 near the channel region and, in turn, the channel potential distribution are almost uniform, and the channel potential near the source and drain regions is relatively the same as the potential at the center of the channel. The value will be low.

Therefore, a sufficient potential barrier is not formed near the source/drain regions at both ends of the channel region. Therefore, the depletion layer expands toward the semiconductor substrate near the source and drain. As devices become more highly integrated,
As the length of the transfer gate electrode or the effective channel length becomes shorter, due to the expansion of this depletion layer,
Penetration between the source and drain is likely to occur, and the punch-through breakdown voltage between the source and drain decreases. If the concentration of the channel region is increased in order to suppress the expansion of this depletion layer, the threshold voltage will become higher than a desired value.

In addition, the so-called ALPEN phenomenon occurs in which alpha particles emitted from radioactive isotopes in the package penetrate the source/drain region.
(Alpha Particle Source/Dr.
ain Penetration) effect is more likely to occur. When the α particle penetrates the source/drain, electron-hole pairs are generated along the penetration path. These electron-hole pairs are separated by the electric field of the depletion layer between the source/drain and the semiconductor substrate, and a new transient depletion layer is created along the penetration path of the α particles. This generation of a transient depletion layer along the penetration path of α particles is called the funneling phenomenon. If a transient depletion layer caused by this funneling phenomenon occurs between the depletion layers near the source/drain during operation of a transistor, transient bunch-through will occur between the source/drain, thereby causing new mode soft error (“L-H” soft error).

As described above, in the manufacturing method of the first conventional example, as the device becomes highly integrated, the source/drain withstand voltage deteriorates and soft errors are more likely to occur, resulting in poor device characteristics and long-term reliability. There is a problem of deterioration.

Furthermore, in the second conventional example, the p-type region 19a.

The inclined ion implantation method used to form the ion implantation region 19b can also be applied to the formation of the ion implantation region 4 in the manufacturing process of the MO8 type LDD structure transistor having the configuration of the first conventional example, but in this case, the following method is applied. Problems like this arise. In the first conventional example, the ion implantation region 4 is formed by oblique ion implantation from two symmetrical directions at a predetermined inclination angle (hereinafter referred to as "oblique fixed ion implantation j") using the transfer gate electrode 5 and sidewall spacer 7 as masks. The profile of the ion implanted region 4 immediately after the completion of ion implantation and the corresponding impurity concentration distribution near the substrate surface are shown by broken lines in FIG. 17.As can be seen from FIG. When ion implantation is applied, immediately after ion implantation, the profile of the ion implantation layer 4 changes sharply at the left and right positions directly below the center of the transfer gate electrode 5. This is because the masking effect of the sidewall spacer 7 prevents the prescribed irradiation pattern from being applied. This is because the impurity ion beam has a fixed inclination angle and irradiates the same position in the same pattern for a certain period of time, so the irradiation pattern has a significant effect on changes in the impurity concentration distribution.

Corresponding to the profile of the ion implantation region 4, the concentration distribution of impurity ions near the substrate surface shows an extremely high p-type impurity concentration immediately below the vicinity of both left and right sides of the transfer gate electrode 5 immediately after the completion of ion implantation, and at the center thereof. is low.

After the ion implantation is completed, a heat treatment step is required to activate the impurity ions. It is known that the movement speed of impurity ions during this diffusion is proportional to the gradient of impurity concentration. Therefore, immediately after the completion of ion implantation, in a region having a steep change in impurity concentration as shown by the broken line in FIG. 17, diffusion rapidly progresses with an extremely short heat treatment. Therefore, when heat treatment is performed under the conditions necessary for the device, it is easy to average out the concentration distribution, especially in regions where the concentration distribution is steep, and after heat treatment, the first
This results in a gentle concentration distribution shown by the two-dot chain line in FIG. As a result, as in the case of the first conventional example, the concentration distribution near the channel region and, in turn, the channel potential distribution become nearly uniform, and there is still a sufficient potential barrier near the source/drain regions at both ends of the channel region. The problem is that it is not formed.

In order to solve the above-mentioned conventional problems, the present invention forms a high potential barrier only near the source/drain at both ends of the channel region, thereby preventing characteristics such as source/drain breakdown voltage from deteriorating even if the device is highly integrated. An object of the present invention is to provide a method for manufacturing a semiconductor device without any problems.

[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes a first step of forming a transfer gate electrode on a semiconductor substrate having a region of one conductivity type at least near the surface via an insulating film; Using this transfer gate electrode as a mask, impurity ions of a conductivity type opposite to that of the semiconductor substrate are implanted into the surface of the semiconductor substrate to form a low concentration source region and a drain region, and the side walls on both sides of the transfer gate electrode. a third step of forming an insulating sidewall spacer on the
A fourth step of implanting impurity ions of a conductivity type opposite to that of the semiconductor substrate into the surface of the semiconductor substrate using the sidewall spacers and transfer gate electrodes as a mask to form highly concentrated source and drain regions; and a fifth step of performing heat treatment to thermally diffuse impurity ions. In the present invention, between the second and third steps, or between the fourth and fifth steps, the surface of the semiconductor substrate is tilted at a predetermined angle from the normal direction of the semiconductor substrate.
The present invention is characterized in that it includes a step of implanting impurity ions of the same conductivity type as the semiconductor substrate while the semiconductor substrate is rotated about one normal line thereof as a rotation axis.

[Function] According to the present invention, by forming the ion implantation layer for threshold voltage control by the oblique rotational implantation method using the transfer gate electrode as a mask, the impurity concentration distribution immediately after the completion of ion implantation is changed to the obliquely fixed ion Compared to the injection method, the process is more gradual. Therefore, in the subsequent diffusion step by heat treatment, even if the heat treatment is performed under conditions necessary for the device, the concentration distribution will not be sharply averaged. Therefore, even after diffusion, almost the same distribution as immediately after ion implantation is maintained. As a result, the concentration distribution of impurities after diffusion can be made significantly higher near the source/drain at both ends of the channel than near the center of the channel region. Therefore, the channel potential of the channel region is also distributed corresponding to this concentration distribution, being low near the center of the channel region and significantly high at both ends.

As a result, a high potential barrier is formed at both ends of the channel region, and the spread of the depletion layer between the source/drain regions is suppressed. As a result, penetration of the depletion layer between the source/drain becomes less likely to occur, and the withstand voltage between the source/drain is improved.

Furthermore, even if α particles enter the source/drain region, the resulting funneling phenomenon is suppressed by the high potential barrier at both ends of the channel region, and transient punch-through between the source/drain caused by the ALPEN effect is also prevented. Ru.

[Example] An example of the present invention will be described below with reference to FIGS. 1A to 1F and 2.
This will be explained based on the diagram.

The manufacturing process of the first embodiment of the present invention is shown in FIGS. 1A to 1F.
As shown in the figure. First, a transfer gate insulating film 3 is formed on a p-type semiconductor substrate 1 in an element formation region surrounded by an element isolation region 2 by the LOCOS method (first
Figure A). Next, a polysilicon film is deposited on the entire surface of the transfer gate insulating film 3 by low pressure CVD, and a transfer gate electrode 5 is formed by photolithography and reactive ion etching (FIG. 1B). The transfer gate electrode 5 may be formed of a single layer of polysilicon, or may be formed of tungsten or molybdenum.

Two layers of high melting point metal such as titanium and polysilicon are heated under reduced pressure C.
It can be deposited by a VD method or a sputtering method, and can also be formed by photolithography and reactive ion etching. Alternatively, a so-called high melting point metal silicide, which is a high melting point metal silicided, may be deposited and photoetched.

Note that the transfer gate electrode 5 is doped with impurity ions such as phosphorus ions for the purpose of increasing its conductivity, so that it has a conductivity type opposite to that of the semiconductor substrate, that is, the same conductivity type as the channel. Therefore, the threshold voltage is lowered due to the work function difference between the n-type transfer gate electrode and the p-type channel region and the diffusion of phosphorus ions into the channel due to subsequent heat treatment. Therefore, it is necessary to increase the threshold voltage by forming an ion implantation region 4, which will be described later.

Next, boron ions, which are the same p-type impurity ions as the semiconductor substrate 1, are implanted into the entire surface of the semiconductor substrate 1 obliquely from a direction forming a predetermined inclination angle θ with respect to the normal direction.

At the same time, the semiconductor substrate 1 is rotated about the normal line at the center of the transfer gate electrode 5. By this oblique rotational ion implantation, a p-type ion implantation layer 4 for threshold voltage control is formed using the transfer gate electrode 5 as a mask (FIG. 1C).

If the tilt angle θ of ion implantation is less than about 10″, it is not preferable because a so-called channeling effect occurs in which ions penetrate abnormally deep in the direction of the crystal axis.Also, even if θ is about 10° or more, If θ is less than about 15°, ion implantation directly under the transfer gate electrode 5 will not be performed sufficiently, making it difficult to control the threshold voltage.
If it exceeds .degree., the amount of ions implanted directly under the transfer gate electrode 5 will increase, resulting in a problem that the threshold voltage will become too high. Therefore, the tilt angle θ of ion implantation is preferably set to 15° or more and 60° or less, and is usually performed at about 30° or more and about 45° or less.

Thereafter, phosphorus ions or arsenic ions, which are n-type impurity ions opposite to the conductivity type of the semiconductor substrate 1, are implanted into the entire surface of the semiconductor substrate 1 from the normal direction. As a result, an n-type ion implantation layer 6 is formed using the transfer gate electrode 5 as a mask (FIG. 1D). Next, an oxide film of silicon dioxide is deposited on the entire surface of the semiconductor substrate 1 by CVD or the like, and is subjected to anisotropic etching to form sidewall spacers 7 (FIG. 1E).

Next, phosphorus ions or arsenic ions, which are n-type impurity ions, are implanted into the entire surface of the semiconductor substrate 1 from the normal direction. As a result, the transfer gate electrode 5
Then, an n-type ion implantation layer 8 is formed using the sidewall spacer 7 as a mask (FIG. 1F).

At this time, the amount of ions implanted into the ion implantation layer 6 is LDD
For structure formation, the concentration is set to be much lower than that of the ion implantation layer 8.

In addition, by performing heat treatment, each ion implantation layer 6, 8
, and a diffusion layer of impurity ions is formed.

In this embodiment, a p-type semiconductor substrate 1 was used as the substrate for forming the MO8 type LDD structure transistor, but instead of this, a p-well, which is a p-type region, is formed at least at a predetermined depth from the substrate surface. It is also possible to use a material formed with the following.

Further, the conductivity type on the substrate side is not limited to p-type, but the substrate side and ion implantation region 4 are n-type, and the ion implantation layer 6
, 8 can also be formed as p-type.

The impurity ion concentration distribution of the MO8 type LDD structure transistor manufactured as described above is as shown in FIG.

The profile and channel potential distribution of the ion implantation region 4 when using the oblique rotational implantation method are based on the LSS theory, which is the theory of vertical ion implantation into an amorphous target, as well as the shadowing effect of the transfer gate electrode 5 and the gate The tangent can be calculated by numerical analysis that introduces a weighting function that takes the effect into consideration. The distribution of impurity ion concentration in FIG. 2 is a schematic representation of the distribution on the surface of the channel region based on this calculation result.

An outline of the theory of numerical analysis for determining the impurity ion concentration distribution shown in FIG. 2 will be explained below.

The distribution of impurities implanted into the semiconductor substrate 1 is first determined by the implantation amount, accelerating voltage, and implantation direction. This relationship can be known by analyzing the mechanism of collision between implanted ions and target atoms. Further, the second factor that determines the impurity distribution is the heat treatment conditions after implantation. That is, the distribution determined by collisions with target atoms is modified by diffusion during heat treatment.

First, consider the first element that does not involve heat treatment. Even if the target material is crystalline, if ions are implanted in a random direction such that no channeling effect occurs, it can be regarded as amorphous. Therefore, the theory of ion implantation in amorphous materials is applied.

The implanted ions collide with target atoms and their direction of motion is bent, creating a trajectory as shown in FIG.

The distance R that the ions travel is called the range, and the projection RP in the injection direction is called the projected range.

Further, the range of the implanted ions has a component RXa in the xy plane direction. Each of these ranges is spread out with a certain distribution around the average value because collisions occur randomly. Lindhard et al. derived an integral equation giving the distribution of these ranges and presented an expression for the distribution of implanted ions that showed fairly good agreement with experimental values. This is called the LSS theory (for example, "Kogyo Kenkyukai Co., Ltd., Electronics Complete Works (8) Ion Implantation Technology, p.29-p.40")
.

The formula for the three-dimensional concentration distribution N (X, Y, Z) of impurity ions derived from this LSS theory is as shown below.

Here, <ΔRp>: Standard deviation of Rp ΔX2>, <ΔY2>: Root mean square of deviations in the X and y directions <ΔX> wide f7WY>: spread of Rp in the X direction ΔY> 17 >: Expansion of Rp in the y direction Next, in addition to the LSS theory described above, a numerical analysis will be described in which a weighting function is introduced that takes into consideration the shadowing effect of the transfer gate electrode 5 and the gate contact effect.

The oblique rotation implantation includes three factors shown in FIGS. 4A, 4B, and 4C. The first factor is the shadowing factor (see FIG. 4A) for the implanted ions at the edge of the transfer gate electrode 5, and this is referred to as a factor [A]. The second factor is due to the direct entry of ions from the surface of the semiconductor substrate 1 to the lower part of the transfer gate electrode 5 (see FIG. 4B), which is calculated by the factor [
B]. The third factor is the transfer gate electrode 5
This is due to the penetration of ions through the polysilicon gate 5b on the side surface (see FIG. 4C), and this is taken as a factor [C].

These three factors [A] [B] [CF all act to reduce the number of ions implanted into the semiconductor substrate 1 when the transfer gate electrode 5 is not present. Therefore, this effect can be incorporated into the concept of probability. In other words, what is the ratio of the number of ions implanted into the substrate when transfer gate electrode 5 actually exists to the number of ions implanted into semiconductor substrate 1 when transfer gate electrode 5 does not exist? This is called weight. This weight obviously depends first of all on the distance from the transfer gate electrode 5.

Now, the impurity distribution formed by oblique rotational ion implantation is roughly divided into two components. One is implanted from the surface of the semiconductor substrate 1, and the factor [A]
Contains [B]. The others are implanted from the side of the polysilicon gate and contain factor [C]. factor[
When A] [B] [C] are taken in as weights, the impurity distribution N(x, z) formed by oblique rotation implantation is expressed as follows.

N (x, ri=NOcos θ fW(r) ρ(ri+W□.d(X) ρ.ad (z)1 where, No: Irradiation amount per unit area of impurity ions θ: Direction perpendicular to the substrate Inclination angle of the ion implantation direction W(I): Weighting function W in the X direction by factor [A] [8]..., (1) : Weighting function in the X direction by factor [C] /' (1) : W (1) □1.0.W
-, d(1) ・Concentration distribution ρ in two directions when Q. a (1): W(I)・Q, W-6d(x)
・Concentration distribution in two directions when 1, 0 Also, the first term of the above equation “Na cosθW(x) I)
(J represents the component injected from the surface of the semiconductor substrate, and the second term rNo cosθWmoa (x)
p.m. a (i) J represents a component injected from the side surface of polysilicon gate 5b.

The coordinate system has an origin 0 on the surface of the semiconductor substrate 1 below the side surface of the transfer gate electrode 5, and x as shown in FIG.
, y, and z axes.

As a specific example of the distribution of the weighting function, θ=45° and the irradiation energy of implanted ions E1m. =42keV.

For No = 2.8X10'3 cm-2, W(
x), W,, od (x), p (z), ρ-od
The results of calculating (z) are shown in FIGS. 6A and 6B.

The function value obtained in this way and the above N(x, y,
The curve shown by the broken line in the graph of FIG. 2 shows the result of determining the impurity ion concentration distribution near the channel surface from the equation (z).

As can be seen from this graph, the impurity ion profile immediately after the completion of ion implantation formed by oblique rotational ion implantation shows a tendency for the p-type ion concentration to increase near both ends of the channel, but It changes more slowly than in the case of fixed injection. This is considered to be due to the following reasons, as already stated in the description of the prior art. First, in oblique fixed ion implantation, the irradiated ions whose concentration distribution changes rapidly at the boundaries of the shadows are shielded by the transfer gate electrode 5 and the sidewall spacer 7, but are irradiated at the same tilt angle for a certain period of time. , the concentration distribution immediately after the completion of ion implantation is also significantly influenced by the shadow and changes rapidly. On the other hand, in oblique rotational implantation, since the irradiated ions and the semiconductor substrate 1 rotate with respect to each other, the shadow caused by the shielding of the transfer gate electrode 5 and the sidewall spacer 7 moves from time to time. It is thought that the influence on the change is averaged and relaxed, resulting in a concentration distribution with gradual changes.

As described above, the impurity profile formed by oblique rotational implantation changes gradually even immediately after ion implantation, and therefore is not easily affected by the heat treatment required thereafter. That is, since the diffusion of impurities due to heat treatment is proportional to the spatial gradient of the impurity profile, the impurity profile formed by oblique rotational implantation does not change significantly even after the heat treatment. this is,
The optimal distribution of the impurity profile after heat treatment is determined by, for example, DRAM (Dynamic Random Accelerator).
This means that it can be achieved under the heat treatment conditions required to maintain device characteristics, such as the optimal heat treatment conditions for ensuring refresh characteristics in ss memory. In other words, even if the impurity ion profile formed by oblique rotational implantation is subsequently subjected to heat treatment under the optimal conditions for the device, it will not be affected as strongly by the diffusion caused by the heat treatment. It can be determined almost independently of the heat treatment conditions.

On the other hand, the impurity profile formed by, for example, oblique fixed ion implantation has a fairly steep change immediately after implantation, and is considerably influenced by the heat treatment required thereafter. Therefore, heat treatment conditions that can maintain an optimal distribution of impurity ion profiles are often not optimal heat treatment conditions for the device. On the contrary,
If the optimum heat treatment is performed for the device, there is a high possibility that the optimum impurity ion profile cannot be obtained after the heat treatment.

As described above, the more gently the impurity ion profile changes immediately after ion implantation is completed, the more optimal the impurity ion profile can be obtained under the optimal heat treatment conditions for the device.

In this sense, it can be said that oblique rotational implantation is a better ion implantation method for device design than oblique fixed implantation.

Further, the threshold voltage approximately corresponds to the average value of the channel potential over the entire channel region. A qualitative explanation of this is as follows. When the p-type impurity ion concentration in the length (ΔL shown in Figure 2) near the source/drain region is increased, the threshold voltage in this region increases, and the carrier mobility, that is, the electric field, due to impurity scattering in this region increases. This results in a decrease in drift velocity proportional to the strength. Therefore, the threshold voltage Vth of the entire transistor also becomes high. Therefore, by lowering the p-type ion concentration in the central part of the channel than in conventional transistors, the threshold voltage in this part decreases and the mobility in this part increases. This allows the threshold voltage Vth of the entire channel to be lowered. From the above, the threshold voltage of the entire channel vt
h is determined corresponding to a substantially average value of the p-type impurity ion concentration over the entire channel length (length scale in FIG. 2).

Therefore, in the channel potential distribution for obtaining a predetermined threshold voltage, by using oblique rotational implantation, the channel potential near the source/drain region is higher than when using the oblique fixed implantation method. As a result, this portion forms a potential barrier and suppresses the spread of the depletion layer between the source/drain regions, thereby improving the source/drain breakdown voltage when no voltage is applied to the transfer gate electrode 5.

Furthermore, even if α particles penetrate through the source/drain region and enter the channel region, the funneling phenomenon in which a depletion layer is transiently created along the α particle penetration path is also suppressed by this potential barrier.

Therefore, transient punch-through between the source/drain caused by the ALPEN effect and the resulting soft error ("L→H" error) are also suppressed.

In this way, according to this embodiment, by forming a high potential barrier near the source/drain at both ends of the channel region, good initial characteristics can be maintained even when the device becomes highly integrated and the effective channel length becomes short. Obtainable. Furthermore, it is possible to operate the device while maintaining good reliability regarding transient characteristics.

Next, another embodiment of the present invention will be described based on FIGS. 7A to 7F.

In the manufacturing process of this embodiment, a transfer gate insulating film 3 is formed in an element formation region surrounded by an element isolation region 2 on a p-type semiconductor substrate l by the LOCO8 method (FIG. 7A).
Furthermore, the process up to the formation of the transfer gate electrode 5 (FIG. 7B) is the same as the embodiment shown in FIGS. 1A and 1B.

This embodiment differs from the above embodiments in that the p-type ion implantation region 4 is used for threshold voltage control by oblique rotational ion implantation.
This is done after forming the n-type ion implantation layer 6.8. That is, in this embodiment, after the n-type ion implantation layer 6 is formed by vertical ion implantation using the transfer gate electrode 5 as a mask (FIG. 7C), the sidewall spacer 7 is formed (7th DIffl).
.

Next, using the transfer gate electrode 5 and sidewall spacer 7 as a mask, an n-type ion implantation layer 8 is formed by vertical ion implantation (FIG. 7E). Thereafter, by performing ion implantation at a predetermined tilt angle θ while rotating the semiconductor substrate l around the normal line at the center of the transfer gate electrode 5, the threshold voltage is controlled using the transfer gate electrode 5 and the sidewall spacer 7 as a mask. A p-type ion implantation region 4 is formed for this purpose (FIG. 7F). Thereafter, heat treatment is further performed to diffuse the implanted ions.

Through the manufacturing process of this embodiment, it is possible to obtain profiles and channel potential distributions of each ion implantation layer that are substantially similar to those shown in FIG. 2.

The first and second embodiments described above are both cases in which the present invention is applied to an MO8 type LDD structure transistor, but the idea of the present invention is to apply the present invention to an MO8 type transistor other than an LDD structure. It can also be applied to the production of Hereinafter, an embodiment in which the present invention is applied to manufacturing an MO8 type transistor other than an LDD structure will be described.

The steps of the third embodiment of the present invention are shown in FIGS. 8A to 8C. This embodiment relates to a method of manufacturing an MO8 type transistor in which no side wall spacer is formed on the side wall of the transfer gate electrode 5. In this example, first, the transfer gate electrode 5 is formed on the transfer gate electrode 3 on the surface of the p-type semiconductor substrate 1 by photolithography and reactive ion etching (FIG. 8A).
.

Next, using this transfer gate electrode as a mask, n
Phosphorus or arsenic, which is a type impurity, is implanted perpendicularly to the substrate surface to form an ion implantation layer 6 that will become a source/drain region (FIG. 8B). Next, while rotating the semiconductor substrate 1 in a horizontal plane, p-type boron ions are irradiated from an oblique direction at a predetermined inclination angle to form an ion implantation region 4 for controlling the threshold voltage of the channel region (No. 8C). figure).

Next, a fourth embodiment of the present invention will be described with reference to FIGS. 9A to 9D. In this embodiment, the transfer gate electrode 5
(Fig. 9A), and using this as a mask, n-type ions are implanted to form the ion implantation layer 6 which becomes the source/drain (Fig. 9B). There is. In this example, after forming the ion implantation layer 6, the sidewall spacer 7 is formed on the side wall of the transfer gate electrode 5 (FIG. 9C), and the ion implantation region 4 is formed by oblique rotational ion implantation (FIG. 9D). figure).

A fifth embodiment of the present invention is shown in FIGS. 10A to 10D. In this embodiment, after forming the transfer gate electrode 5 on the transfer gate electrode 3 (FIG. 10A), using this as a mask, the ion implantation region 4 is formed by oblique rotational ion implantation (FIG. 10B). Next, after forming the sidewall spacer 7 (FIG. 10C), the ion implantation layer 6 is formed by vertical ion implantation (FIG. 10D).
.

A sixth embodiment of the present invention is shown in FIGS. 11A to 11D. In this embodiment, immediately after forming the gate electrode 5 (FIG. 11A), sidewall spacers 7 are formed (FIG. 11B), and in this state, oblique rotational ion implantation is performed to form the ion implantation region 4. 11C), and further form an ion implantation layer 6 by vertical ion implantation (first
1D figure).

A seventh embodiment of the present invention is shown in FIGS. 12A to 12D. In this embodiment, using the transfer gate electrode 5 as a mask, oblique rotational ion implantation of boron ions is performed to first form the ion implantation region 4 (FIG. 12A), and then to form the sidewall spacer 7 (FIG. 12B). ). Thereafter, phosphorus ions are implanted by vertical ion implantation to form a relatively low concentration ion implantation layer 6.
Furthermore, arsenic ions having a smaller thermal diffusion coefficient than phosphorus ions are implanted by vertical ion implantation to form a relatively high concentration ion implantation layer 9 (FIG. 12D). Double ion-implanted layers 6 with different concentrations formed in this way,
This is based on the same concept as the LDD structure, in which punch-through in the channel is prevented by relaxing the electric field strength in the channel portion. This structure is MO8
Type Double Diffuse Drain
It is called a d-drain (DDD) structure transistor.

An eighth embodiment of the present invention is shown in FIGS. 13A to 13D. This embodiment is similar to the seventh embodiment in that the present invention is applied to the formation of an MO8 type DDD structure transistor. In this embodiment, the side wall spacer 7
(FIG. 13A), boron ions are implanted by oblique rotational ion implantation to form a p-type ion implantation region 4 (FIG. 13B). This is similar to the seventh embodiment in that a DDD structure is formed by vertically implanting phosphorus ions (FIG. 13C) and then arsenic ions (FIG. 13D).

In the third to eighth embodiments described above, the ion implantation region 4 for setting the threshold voltage of the channel has almost the same distribution as in the first embodiment. Therefore, even after the subsequent heat treatment, an impurity concentration distribution as shown by the two-dot chain line in FIG. 2 is obtained, a potential barrier is formed, and the source/drain breakdown voltage can be improved.

[Effects of the Invention] As described above, according to the present invention, an ion implantation layer for threshold voltage control is formed by an oblique rotational implantation method using a transfer gate electrode as a mask.
The channel potential distribution for setting a predetermined threshold voltage can be made significantly higher only near the source/drain than near the center of the channel region. As a result, a high potential barrier is formed at both ends of the channel region without increasing the threshold voltage, and the expansion of the depletion layer between the source/drain regions is suppressed. Therefore, the source/drain breakdown voltage is improved when no voltage is applied to the transfer gate electrode. Furthermore, the high potential barrier suppresses punch-through between the source and drain caused by the ALPEN effect, and also prevents a new mode of soft error (L→H" error).

As a result, even if the device becomes highly integrated and the effective channel length becomes short, initial characteristics and long-term transient characteristics are maintained well, and a highly reliable semiconductor device can be manufactured.

[Brief explanation of drawings]

Figure 1A, Figure 1B, Figure 1C, Figure 1D, Figure 1E,
FIG. 1F is a cross-sectional view sequentially schematically showing the manufacturing process of the first embodiment of the present invention. FIG. 2 is a diagram schematically showing the profile of the ion implantation layer in the vicinity of the channel of the MO8 type LDD structure transistor formed by the process of this embodiment and the corresponding impurity ion concentration distribution. FIG. 3 is a diagram showing the range of ions and the coordinate system in order to explain the theory of numerical analysis for determining the impurity ion concentration distribution in each embodiment of the present invention. FIG. 4A, FIG. 4B, and FIG. 4C are diagrams for explaining three factors that affect the shielding of the transfer gate electrode 5 in ion implantation. FIG. 5 is a diagram for explaining a coordinate system in analysis of oblique rotational ion implantation. 6A and 6B show the transfer gate electrode 5
The shadowing effect and juxtaposition of the weighting functions W (x), Wna o d (x), and the distribution of the depth distribution functions ρ(2), ρ1゜d(z) considering the effect are as follows. . Figure 7A, Figure 7B, Figure 7C, Figure 7D, Figure 7E,
FIG. 7F is a cross-sectional view sequentially schematically showing the manufacturing process of the second embodiment of the present invention. FIG. 8A, FIG. 8B, and FIG. 8C are sectional views sequentially schematically showing the outline of the manufacturing process in the third embodiment of the present invention. 9A, 9B, 9C, and 9D are cross-sectional views sequentially schematically showing the outline of the manufacturing process in the fourth embodiment of the present invention. Figures 10A, 10B, 10C, and 10D are
It is sectional drawing which sequentially schematically shows the outline of the manufacturing process in the 5th Example of this invention. Figures 11A, 11B, 11C, and 11D are
It is sectional drawing which sequentially schematically shows the outline of the manufacturing process in the 6th Example of this invention. Figures 12A, 12B, 12C, and 12D are
It is sectional drawing which sequentially schematically shows the outline of the manufacturing process in the 7th Example of this invention. Figures 13A, 13B, 13C, and 13D are
It is sectional drawing which sequentially schematically shows the outline of the manufacturing process in the 8th Example of this invention. 14A, 14B, 14C, 14D, 14E, and 14F are cross-sectional views sequentially schematically showing the manufacturing steps in the first conventional example. Figures 15A, 15B, 15C, and 15D are
FIG. 7 is a cross-sectional view sequentially schematically showing an outline of the manufacturing process of a second conventional example. FIG. 16 is a diagram schematically showing the profile of the ion implantation layer near the channel and the corresponding impurity ion concentration of the MO3 type LDD structure transistor formed according to the first conventional example. FIG. 17 is a diagram schematically showing the profile of the ion implantation layer near the channel of the MO8 type LDD transistor formed by the same method as the second conventional example and the corresponding impurity ion concentration distribution. . In the figure, 1 is a semiconductor substrate, 2 is an element isolation region, 3 is a transfer gate insulating film, 4 is an ion implantation layer, 5 is a transfer gate electrode, 7 is a sidewall spacer,
8 and 9 are ion-implanted layers. In addition, in the drawings, the same reference numerals indicate the same or equivalent elements. Figure 3 Figure 4A Figure 5 Figure 7A Section 7B Figure 7C Figure P ion Figure 6A Figure B ion\ Figure 14A Figure 4B Figure 14c Figure 15C Figure A is (1 G Figure

Claims (1)

[Claims] A first step of forming a transfer gate electrode via an insulating film on a semiconductor substrate having a region of one conductivity type at least near the surface; A second step of implanting impurity ions of a conductivity type opposite to that of the semiconductor substrate to form a low concentration source region and a drain region, and forming insulating sidewall spacers on both side walls of the transfer gate electrode. a third step, using the sidewall spacer and the transfer gate electrode as a mask, implanting impurity ions of a conductivity type opposite to that of the semiconductor substrate into the surface of the semiconductor substrate to form a highly concentrated source region and a drain region; A method for manufacturing a semiconductor device comprising a fourth step and a fifth step of performing heat treatment for thermally diffusing implanted impurity ions, wherein the step is performed between the second step and the third step, or between the fourth step. and the fifth step, with the surface of the semiconductor substrate forming a predetermined inclination angle from the normal direction of the semiconductor substrate, and the semiconductor substrate being rotated about one normal line as a rotation axis, A method for manufacturing a semiconductor device, comprising the step of implanting impurity ions of the same conductivity type as the semiconductor substrate.