JP2928342B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device,
S (Metal Oxide Semiconductor) type LDD (Lightly Doped
The present invention relates to a method for manufacturing a semiconductor device for forming a transistor having a drain structure or another MOS transistor.

[Prior art] The basic structure of a MOS field effect transistor is S
On both sides of a so-called MOS capacitor having a metal electrode provided on a i-substrate via a thin oxide film, a source serving as a carrier supply source and a drain for taking out carriers are arranged. The metal electrode on the oxide film has a function of controlling the conductance between the source and the drain, and is therefore called a transfer gate electrode. As the material of the transfer gate electrode, polysilicon doped with impurities, metal silicide formed by heat-treating a high melting point metal such as tungsten deposited on polysilicon in an inert gas, and the like are often used.

When the voltage (gate voltage) of the transfer gate electrode is lower than the threshold voltage _Vth required to reverse the conductivity type near the surface of the Si substrate (channel) between the source and the drain, both the source and the drain have a pn junction. Separated, no current flows. When a gate voltage of _Vth or more is applied, the conductivity type of the channel surface is inverted, a layer of the same conductivity type as the source / drain is formed in this portion, and a current flows between the source / drain.

By the way, if the change in the impurity concentration distribution at the boundary between the source / drain and the channel is abrupt, the electric field intensity in this portion increases. The carrier obtains energy by this electric field, so-called hot carriers are generated. Then,
This carrier is injected into the transfer gate insulating film,
An interface state is generated at the interface between the transfer gate insulating film and the semiconductor substrate, or trapped in the transfer gate insulating film. For this reason, the threshold voltage and transconductance of the MOS transistor deteriorate during operation. This is a deterioration phenomenon of the MOS transistor due to hot carriers. The so-called avalanche breakdown voltage against avalanche breakdown between the source and the drain is also deteriorated by the hot carriers. Therefore, the electric field strength is reduced by lowering the concentration of the n-type impurity in the vicinity of the source / drain and making the change in the concentration distribution gentle. This allows MOS
A MOS-type LDD structure transistor suppresses deterioration of the transistor due to hot carriers and improves the avalanche withstand voltage of the source / drain.

As a conventional method of manufacturing a MOS type LDD transistor,
For example, there are those shown in FIGS. 14A to 14F. In this manufacturing method, first, a so-called LOCOS
By (Local O xidation of S ilicon) method to form a transfer gate oxide film 3 in the element formation region surrounded by the element isolation insulating film 2 (first 14A Figure). Next, a p-type impurity such as boron ions is implanted into the entire surface of the semiconductor substrate 1 to control the threshold voltage, thereby forming an ion-implanted region 4.
14B). Thereafter, a polysilicon film is deposited on the entire surface of the transfer gate oxide film 3 by the low pressure CVD method, and the transfer gate electrode 5 is formed by photolithography and reactive ion etching (FIG. 14C). The transfer gate electrode 5 may be formed of a two-layer film of polysilicon and a refractory metal such as tungsten, molybdenum, or titanium, or a silicide thereof, instead of polysilicon. This transfer gate electrode 5
Is doped with phosphorus ions to increase conductivity. In this case, the transfer gate electrode 5 becomes n-type and has the same conductivity type as the channel, that is, the conductivity type of the source / drain. Therefore, even when a gate voltage is not applied to the transfer gate electrode 5, a positive gate voltage is effectively applied to the p-type channel surface due to a difference in work function between the n-type transfer gate electrode 5 and the p-type channel surface. A state is created that is being applied.
Also, n doped in the transfer gate electrode 5
The type impurities may be diffused to the p-type channel surface by the subsequent heat treatment. For these reasons, V _th decreases, and in some cases, an inversion layer may already be formed in the channel. The above-described ion-implanted region 4 is formed by implanting a p-type impurity in advance.
The purpose is to cancel the influence of impurity ions doped into the transfer gate electrode 5 and secure a desired _Vth .

Next, using the gate electrode 5 as a mask, an n-type impurity such as phosphorus ions or arsenic ions is vertically injected into the surface of the semiconductor substrate 1 to form an n-type ion implantation layer 6 (fourteenth).
D figure). Thereafter, an insulating film such as silicon dioxide is deposited on the entire surface of the semiconductor substrate 1 by a low pressure CVD method or a normal pressure CVD method, and is subjected to anisotropic etching to form a sidewall spacer 7 (FIG. 14E). . Next, n-type impurities such as phosphorus ions and arsenic ions are vertically implanted into the surface of the semiconductor substrate 1 using the transfer gate electrode 5 and the sidewall spacers 7 as a mask, and n-type ions having a higher concentration than the ion-implanted layer 6. Form injection layer 8 (14F
Figure). Thereafter, a heat treatment for activating the implanted impurity ions is performed, thereby completing the MOS-type LDD transistor.

In the above conventional example, a p-type semiconductor substrate is used as the substrate, but a p-well which is a region into which p-type impurities are implanted at least in the vicinity of the substrate surface may be used. Further, an n-type semiconductor substrate is used as a substrate, or an n-type impurity is implanted at least in the vicinity of the surface.
A substrate in which a well is formed may be used. In this case, the transfer gate electrode 5 is p-type, the ion implantation region 4 for controlling the threshold voltage is n-type, and p-type ion implantation layers 6 and 8 are formed in the source and drain regions.

In the above conventional example, since the ion implantation is performed only from the direction perpendicular to the surface of the semiconductor substrate 1, the ion implantation region 4 for controlling the threshold voltage must be formed before the transfer gate electrode 5 is formed. On the other hand, as a method for forming each ion-implanted layer after forming the transfer gate electrode 5 by applying the oblique ion-implantation method, there is a method described in JP-A-61-226968. The manufacturing method of the MOS type semiconductor device described in the publication is described with reference to FIGS. 15A to 15D.
First, a field oxide film formed on a p-type semiconductor substrate 11
Using the 12 and the transfer gate electrode 14 as a mask, phosphorus ions are implanted at an acceleration voltage of 20 KeV to form an n-type region 18 (FIG. 15A). Subsequently, when boron ions are implanted at an incident angle of 30 ° and an acceleration voltage of 30 KeV using the gate electrode 14 as a mask, impurities are implanted in front of the incidence, and an n-type region 18 is formed on the right side wall of the channel formation region immediately below the transfer gate electrode 14.
A p-type region is formed further inside (FIG. 15B). When the same inclined ion implantation is performed from the opposite side, p-type regions 19a and 19b are formed so as to surround all the side surfaces and the lower surface of n-type region 18 (FIG. 15C).

Next, the photoresist 20 is patterned and formed around the transfer gate electrode 14, and when this is used as a mask, arsenic ions are implanted at a high concentration to form an n-type region 21 serving as a source / drain (FIG. 15D).

Finally, a silicon oxide film 22 is deposited on the entire surface by a CVD method, and contact holes are formed at predetermined positions in gate, source, and drain regions by a reactive ion etching method or the like. If this is deposited and patterned, an n-channel MOS type semiconductor device is completed.

As described above, according to this conventional example, since the p-type regions 19a and 19b are formed by oblique ion implantation, each ion-implanted layer is formed after the gate electrode 14 is formed.

[Problems to be Solved by the Invention] Among the above-described conventional methods for manufacturing a semiconductor device, in the case of the first conventional example, vertical ion implantation is performed on the entire surface of the semiconductor substrate 1 before forming the transfer gate electrode 5. Then, an ion implantation region 4 which is a diffusion layer for controlling a threshold voltage is formed. Therefore, the p-type impurity ion concentration distribution becomes almost uniform over the entire channel region as shown by the broken line in the graph of FIG. Even after the heat diffusion step, this tendency does not change significantly, and the distribution becomes as shown by the two-dot chain line in FIG. Since the threshold voltage is determined according to the almost average value of the channel potential of the entire channel region,
When a predetermined threshold voltage is set, the average value of the concentration distribution of the ion-implanted region 4 to be formed is determined correspondingly.
In the first conventional example, the ion implantation region 4 near the channel region is used.
And the distribution of the channel potential becomes substantially uniform, and the channel potential in the vicinity of the source region and the drain region has a relatively low value substantially equal to the potential at the center of the channel. Therefore, a sufficient potential barrier is not formed near the source / drain regions at both ends of the channel region. Therefore, the spread of the depletion layer toward the semiconductor substrate near the source and the drain increases.
As the device becomes highly integrated, as the length of the transfer gate electrode or the effective channel length becomes shorter, penetration of the source / drain tends to occur due to the expansion of the depletion layer, and the source / drain becomes more susceptible. , The punch-through withstand voltage is reduced. If the concentration of the channel region is increased in order to suppress the spread of the depletion layer, the threshold voltage will be higher than a desired value.

In addition, the so-called ALPEN (A
lpha particle Source / Drain Penetration) effect easily occurs. When the α particle penetrates the source / drain,
Electron-hole pairs are generated along the through path. The electron-hole pairs are separated by the electric field of the depletion layer between the source / drain and the semiconductor substrate, and a new transient depletion layer is generated along the α particle penetration path. The generation of a transient depletion layer along the α particle penetration path in this way is called a funneling phenomenon. If a transient depletion layer caused by this funneling phenomenon occurs between the depletion layers near the source / drain during the operation of the transistor, a transient punch-through occurs between the source / drain,
This causes a new mode of soft error (“L → H” soft error).

As described above, in the manufacturing method as in the first conventional example, the source / drain withstand voltage is deteriorated and the soft error is liable to occur as the device is highly integrated, and the initial characteristics and long-term reliability of the device are increased. Is deteriorated.

Also, the gradient ion implantation method used for forming the p-type regions 19a and 19b in the second conventional example is changed to the formation of the ion-implanted region 4 in the manufacturing process of the MOS LDD structure transistor having the configuration of the first conventional example. However, in this case, the following problem occurs. The formation of the ion implantation region 4 in the first conventional example is performed by using the transfer gate electrode 5.
Profile of the ion-implanted region 4 immediately after the completion of ion implantation when formed by oblique ion implantation (hereinafter, referred to as “oblique fixed ion implantation”) from two symmetrical directions with a predetermined inclination angle using the mask and the sidewall spacer 7 as a mask. The corresponding impurity concentration distribution near the substrate surface
This is indicated by a broken line in the figure. As can be seen from FIG. 17, when the gradient ion implantation is applied, immediately after the ion implantation, the profile of the ion implantation layer 4 changes sharply at the left and right positions just below the center of the transfer gate electrode 5. This is because the impurity ion beam having a predetermined irradiation pattern is irradiated at a fixed inclination angle and at the same position with the same pattern for a certain period of time due to the masking action of the sidewall spacers 7. This is because the change in the impurity concentration distribution is significantly affected.

Corresponding to the profile of the ion implantation region 4, the concentration distribution of impurity ions in the vicinity of the substrate surface shows an extremely high p-type impurity concentration immediately below the right and left sides of the transfer gate electrode 5 immediately after the ion implantation is completed, and in the center thereof. Is low. After the completion of the ion implantation, a heat treatment step for activating the impurity ions is required.
It is known that the moving speed of the impurity ions in this diffusion is proportional to the gradient of the impurity concentration. Therefore,
Immediately after the completion of the ion implantation, in a region having a steep impurity concentration change as indicated by a broken line in FIG. 17, the diffusion rapidly proceeds by a heat treatment for a very short time. Therefore, if you try to heat treatment under the conditions necessary for the device,
In particular, in a region where the concentration distribution is steep, the averaging easily occurs, and after the heat treatment, the concentration distribution becomes gentle as shown by a two-dot chain line in FIG. As a result, as in the case of the first conventional example, the concentration distribution near the channel region and, consequently, the channel potential distribution become nearly uniform, and a sufficient potential barrier also exists near the source / drain regions at both ends of the channel region. There is a problem that it is not formed.

The present invention solves the above-mentioned conventional problems by forming a high potential barrier only in the vicinity of the source / drain at both ends of the channel region, so that the characteristics of the source / drain withstand voltage are deteriorated even when the device is highly integrated. It is an object to provide a method for manufacturing a semiconductor device.

[Means for Solving the Problems] A semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type and a pair of first conductivity type semiconductor substrates disposed on a main surface of the semiconductor substrate with a channel region interposed therebetween. , A channel region and a pair of first impurity regions,
A pair of second conductivity type second impurity regions which contain impurities at a higher concentration than the first impurity region and become a source region and a drain region together with the pair of first impurity regions, and a channel region on the surface of the semiconductor substrate And a transfer gate electrode having an impurity concentration substantially equal to that of the second impurity region and a pair of semiconductors closer to the pair of first impurity regions than the center of the channel region. A pair of third conductive type third conductive regions formed to cover both lower ends of the first and second impurity regions from the main surface of the substrate.
Impurity region.

A step of forming a transfer gate electrode on the main surface of the semiconductor substrate of the first conductivity type via an insulating film; and a step of injecting impurities of the first conductivity type by oblique rotation ion implantation to form a main portion of the semiconductor substrate below the transfer gate electrode. Forming a first impurity region opposed across the channel region on the surface;
A step of forming a second impurity region in the first impurity region by ion-implanting a conductive impurity, a step of forming a sidewall spacer of an insulator on a side wall of the transfer gate electrode, Ion implantation of impurities of
Forming a third impurity region in the first impurity region which contains a higher concentration of impurity than the second impurity region and which becomes a source region and a drain region together with the second impurity region. is there.

[Operation] According to the semiconductor device of the present invention having the above-described configuration, the source / drain region and the reverse conductivity are formed so as to cover the lower end of the high concentration region and the low concentration region of the source / drain region from the main surface of the semiconductor substrate. Channel region for setting a predetermined threshold voltage is significantly higher in the vicinity of the source / drain region than in the center of the channel region, and a high potential barrier is formed in this portion. It can be formed, and the expansion of the depletion layer between the source / drain regions can be suppressed.

Also, even if α particles enter the source / drain regions,
The resulting funneling phenomenon is also suppressed by the high potential barrier at both ends of the channel region, and transient punch-through between the source and drain due to the ALPEN effect is also prevented.

Further, since impurities of the opposite conductivity type to the source / drain regions are obliquely rotated and ion-implanted to form impurity regions covering the source / drain regions, an impurity concentration distribution can be formed in the impurity regions. Thereby, the potential distribution in the channel region, that is, the potential barrier can be set to be remarkably high only in the vicinity of the source / drain regions, and the spread of the depletion layer between the source / drain regions is suppressed. You can get the way.

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1A to 1F and FIG.

The manufacturing process of the first embodiment of the present invention is as shown in FIGS. 1A to 1F. First, LO on a p-type semiconductor substrate 1
A transfer gate insulating film 3 is formed in a device forming region surrounded by a device isolation region 2 by the COS method (FIG. 1A).
Next, a polysilicon film is deposited on the entire surface of the transfer gate insulating film 3 by a low pressure CVD method, and the transfer gate electrode 5 is formed by photolithography and reactive ion etching.
(FIG. 1B). This transfer gate electrode 5
In addition to forming a single layer of polysilicon, two layers of refractory metal such as tungsten, molybdenum, and titanium and polysilicon are deposited by low pressure CVD or sputtering, and photolithography and reactive ion etching are performed. Alternatively, it can be formed. In addition, a so-called high melting point metal silicide obtained by converting a high melting point metal into a silicide is deposited,
It may be formed by performing photoetching.

The transfer gate electrode 5 is doped with impurity ions such as phosphorus ions for the purpose of enhancing its conductivity, and is made to have a conductivity type opposite to that of the semiconductor substrate, that is, the same conductivity type as the channel. Therefore, the work function difference between the n-type transfer gate electrode and the p-type channel region and the diffusion of phosphorus ions into the channel by the subsequent heat treatment lower the threshold voltage. Therefore, it is necessary to increase the threshold voltage by forming an ion implantation region 4 described later.

Next, the semiconductor substrate 1 is inclined over the entire surface of the semiconductor substrate 1 from a direction forming a predetermined inclination angle θ with respect to the normal direction.
Boron ions, which are the same p-type impurity ions, are implanted. At the same time, the semiconductor substrate 1 is rotated around a center normal line of the transfer gate electrode 5. By this oblique rotation ion implantation, a p-type ion implantation layer 4 for controlling the threshold voltage is formed using the transfer gate electrode 5 as a mask (FIG. 1C).

If the inclination angle θ of the ion implantation is about 10 ° or less, a so-called channeling effect in which ions penetrate abnormally deep into the crystal axis direction occurs, which is not preferable. Even if θ is about 10 ° or more, if the angle is about 15 ° or less, ions are not sufficiently implanted immediately below the transfer gate electrode 5 and it is difficult to control the threshold voltage. When θ exceeds about 60 °, the amount of ions implanted immediately below the transfer gate electrode 5 increases, and the threshold voltage becomes too high. Therefore, the inclination angle θ of the ion implantation is
It is preferable to set the angle between 15 ° and 60 °, usually between about 30 ° and about 45 °.

Thereafter, phosphorus ions or arsenic ions as n-type impurity ions opposite to the conductivity type of the semiconductor substrate 1 are implanted into the entire surface of the semiconductor substrate 1 from the normal direction. Thus, an n-type ion implantation layer 6 is formed using the transfer gate electrode 5 as a mask (FIG. 1D). Next, an oxide film of silicon dioxide is deposited on the entire surface of the semiconductor substrate 1 by a CVD method or the like, and is subjected to anisotropic etching to form a sidewall spacer 7 (FIG. 1E).

Then, phosphorus ions or arsenic ions, which are n-type impurity ions, are implanted into the entire surface of the semiconductor substrate 1 from its normal direction. Thus, the transfer gate electrode 5 and the side wall spacer 7 are used as a mask and n
A type ion implantation layer 8 is formed (FIG. 1F).

At this time, the ion implantation amount into the ion implantation layer 6 is LDD.
In order to form the structure, the concentration is set to be much lower than the concentration of the ion implantation layer 8.

Further, by performing heat treatment, each ion-implanted layer 6, 8
And a diffusion layer of impurity ions is formed.

In this embodiment, the p-type semiconductor substrate 1 is used as the substrate for forming the MOS LDD structure transistor. However, the p-type region, which is a p-type region at least at a predetermined depth from the substrate surface, is used instead. Can be used.

Further, the conductivity type on the substrate side is not limited to p-type, and the substrate side and the ion-implanted region 4 are made n-type.
It is also possible to form 6,8 as p-type.

FIG. 2 shows the impurity ion concentration distribution of the MOS LDD structure transistor manufactured as described above.

The profile and the channel potential distribution of the ion implantation region 4 when the oblique rotation implantation method is used are the shadowing effect of the transfer gate electrode 5 and the gate potential distribution in addition to the LSS theory which is the theory of the vertical ion implantation into the amorphous target. It can be calculated by numerical analysis that introduces a weight function taking into account the penetration effect. The distribution of the impurity ion concentration in FIG. 2 schematically shows the distribution on the surface of the channel region based on the calculation result.

Hereinafter, the outline of the theory of numerical analysis for obtaining the impurity ion concentration distribution of FIG. 2 will be described.

First, the distribution of the impurities implanted in the semiconductor substrate 1 is determined by the implantation amount, the acceleration voltage, and the implantation direction. This relationship can be known by analyzing the mechanism of collision between the implanted ions and the target atoms. A second factor that determines the impurity distribution is a heat treatment condition after implantation. That is, the distribution determined by collision with target atoms is deformed by diffusion during the heat treatment.

First, consider the first element that does not include heat treatment.
Even if the target material is crystalline, it can be regarded as amorphous if the ion implantation is performed in a random direction such that the channeling effect does not occur. Therefore, the theory of ion implantation in amorphous is applied.

The implanted ions collide with target atoms and are bent in the direction of movement, and draw a trajectory as shown in FIG. The distance R which ions move projected range, projected range as that the projection R _P to its injection direction.

The range of the implanted ions has a component R _{Xy in the} xy plane direction. Each of such ranges has a distribution around an average value and spreads because collisions occur at random. Lindhard and colleagues have derived integral equations that give the distribution of these ranges, and have given equations for the distribution of implanted ions that are in good agreement with experimental values. This is called the LSS theory (for example, “Industry Research Institute, Complete Works of Electronics (8) Ion Implantation Technology, pp. 29-40”).

The expression of the three-dimensional concentration distribution N (X, Y, Z) of impurity ions derived from this LSS theory is as shown below.

Here, <ΔR _P >: standard deviation of R _P <ΔX ² >, <ΔY ² >: mean square of deviation in x direction and y direction Next, a description will be given of a numerical analysis in which a weight function taking into account the shadowing effect and the gate punch-through effect of the transfer gate electrode 5 in addition to the LSS theory is introduced.

The oblique rotation injection includes the three factors shown in FIGS. 4A, 4B and 4C. First, there is a factor of shadowing (see FIG. 4A) with respect to the implanted ions at the edge of the transfer gate electrode 5, which is referred to as a factor [A].
And The second factor is due to direct entry of ions from the surface of the semiconductor substrate 1 to below the transfer gate electrode 5 (see FIG. 4B), which is referred to as factor [B]. The third factor is due to the penetration of ions through the polysilicon gate 5b on the side surface of the transfer gate electrode 5 (see FIG. 4C), which is referred to as factor [C].

Each of these three factors [A] [B] [C] is:
When the transfer gate electrode 5 does not exist, it acts to reduce the number of ions implanted into the semiconductor substrate 1. Therefore, the effect can be taken into the concept of probability. That is, what is the ratio of the number of ions implanted into the substrate when the transfer gate electrode 5 actually exists to the number of ions implanted into the semiconductor substrate 1 when the transfer gate electrode 5 does not exist? And this is called a weight. This weight depends firstly on the distance from the transfer gate electrode 5.

The impurity distribution formed by the oblique rotation ion implantation is roughly composed of two components. One is injected from the surface of the semiconductor substrate 1 and has a factor [A].
[B]. Others are implanted from the side of the polysilicon gate and contain factor [C]. Taking in the factors [A], [B], and [C] as weights, the impurity distribution N (x, z) formed by oblique rotation implantation is expressed as follows.

N (x, z) = No cos θ {W (x) ρ (z) + W _mod (X) ρ _mod (z)} where N ₀ : dose of impurity ions per unit area θ: perpendicular to the substrate Inclination angle of ion implantation direction with respect to direction W (x): Weight function in x direction by factor [A] [B] W _mod (x): Weight function in x direction by factor [C] ρ (x): W (x ) = 1.0, density distribution in the z direction when W _mod (x) = 0 ρ _mod (z): z when W (x) = 0, W _mod (x) = 1.0
The first term “No cos θW (x) ρ (z)” in the above equation represents a component injected from the surface of the semiconductor substrate, and the second term “No cos θ W _mod (x) ρ _mod ( "z)" represents a component injected from the side surface of the polysilicon gate 5b.

The coordinate system has an origin O on the surface of the semiconductor substrate 1 below the side surface of the transfer gate electrode 5, and as shown in FIG.
Take the x, y, and z axes.

As a specific example of the distribution of the weighting function, W (x), W _m0d (x), ρ for θ = 45 °, the irradiation energy of the implanted ions E _imp = 42 keV, and N ₀ = 2.8 × 10 ¹³ cm ⁻² The results of calculating (z) and ρ _m0d (z) are shown in FIGS. 6A and 6B.

The function value obtained in this way and the above N (x, y,
The result of obtaining the impurity ion concentration distribution in the vicinity of the channel surface from the expression of z) is a curve shown by a broken line in the graph of FIG.

As can be seen from this graph, the impurity ion profile formed by the oblique rotation ion implantation immediately after the completion of the ion implantation shows a tendency that the p-type ion concentration becomes high near both ends of the channel, but the oblique fixation shown in FIG. It changes more slowly than in the case of injection. This is considered to be due to the following reasons, as already described in the description of the related art. First, in the oblique fixed ion implantation, irradiation ions whose concentration distribution changes abruptly at the boundary of the shadow by being shielded by the transfer gate electrode 5 and the sidewall spacer 7 are irradiated at the same inclination angle for a certain time. In addition, the concentration distribution immediately after the completion of the ion implantation also changes drastically under the influence of the shadow. On the other hand, in the oblique rotation implantation, since the irradiation ions and the semiconductor substrate 1 rotate with respect to each other, the transfer gate electrode 5
It is thought that the influence of the shadow on the change in the impurity ion concentration distribution due to the shadow is moved from moment to moment, and the influence of the shadow on the change in the impurity ion concentration distribution is averaged and reduced, resulting in a concentration distribution having a gentle change.

As described above, since the impurity profile formed by the oblique rotation implantation changes gradually even immediately after the ion implantation, it is hardly affected by the heat treatment required thereafter. That is, since the diffusion of the impurity by the heat treatment is proportional to the spatial gradient of the impurity profile, the impurity profile formed by the oblique rotation implantation does not change much after the heat treatment. This is because the optimum distribution of the impurity profile after the heat treatment is determined by the heat treatment conditions required to maintain the device characteristics, such as the optimum heat treatment conditions for ensuring the refresh characteristics in a DRAM (Dynamic Random Access Memory). It means that it can be realized with things.
In other words, the impurity ion profile formed by oblique rotation implantation is not so strongly affected by the heat treatment under the optimum conditions for the device even if it is subsequently subjected to heat treatment under the optimal conditions for the device. It can be determined almost independently of the heat treatment conditions.

On the other hand, the impurity profile formed by, for example, oblique fixed ion implantation has a very sharp change immediately after the implantation, and is considerably affected by the heat treatment required thereafter. Therefore, the heat treatment conditions that can maintain the optimum distribution of the impurity ion profile are often not the optimum heat treatment conditions for the device. Conversely, if the optimal heat treatment is performed for the device, it is highly likely that an optimum impurity ion profile cannot be obtained after the heat treatment.

As described above, the more gradually the impurity ion profile immediately after the completion of the ion implantation, the more the optimum impurity ion profile can be obtained under the optimal heat treatment conditions for the device. In this sense, it can be said that oblique rotation implantation is a superior ion implantation method for device design than oblique fixed implantation.

Further, the threshold voltage substantially corresponds to the average value of the channel potential of the entire channel region. This will be described qualitatively as follows. Increasing the p-type impurity ion concentration in the portion near the length of the source / drain region (ΔL shown in FIG. 2) increases the threshold voltage in this portion, and causes carrier mobility due to impurity scattering in this portion, that is, the electric field of the electric field. This results in a decrease in drift speed proportional to the strength. Therefore, the threshold voltage V _{th of the} entire transistor also increases. Therefore, by making the p-type ion concentration at the center of the channel lower than that of a conventional transistor, the threshold voltage of this portion is reduced, and the mobility of this portion is increased. As a result, the threshold voltage V _{th of the} entire channel can be reduced. From the above, the threshold voltage V of the entire channel
_th is determined corresponding to an approximately average value of the p-type impurity ion concentration over the entire channel length (length L in FIG. 2).

Therefore, the distribution of the channel potential for obtaining the predetermined threshold voltage is obtained by oblique rotation injection.
The channel potential near the source / drain regions is higher than in the oblique fixed implantation method. As a result, this portion forms a potential barrier and suppresses the expansion of the depletion layer between the source / drain regions, so that the source / drain withstand voltage when no voltage is applied to the transfer gate electrode 5 is improved. Even if the α-particles penetrate through the source / drain regions and enter the channel region, a funneling phenomenon in which a depletion layer is transiently formed along the α-particle intrusion path is suppressed by the potential barrier. Therefore, a transient punch-through between the source and the drain caused by the ALPEN effect and a soft error (“L → H” error) due to the transient punch-through can be suppressed.

As described above, according to this embodiment, since a high potential barrier is formed near the source / drain at both ends of the channel region, good initial characteristics can be obtained even when the device is highly integrated and the effective channel length is reduced. Obtainable. In addition, the operation can be performed while maintaining good reliability with respect to transient characteristics.

Next, another embodiment of the present invention will be described with reference to FIGS. 7A to 7F.

In the manufacturing process of this embodiment, a transfer gate insulating film 3 is formed in a device forming region surrounded by a device isolation region 2 on a p-type semiconductor substrate 1 by a LOCOS method (FIG. 7A). (FIG. 7B) is the same as the embodiment shown in FIGS. 1A and 1B.

This embodiment is different from the above embodiment in that the p-type ion implantation region 4 for controlling the threshold voltage by oblique rotation ion implantation is formed after the n-type ion implantation layers 6 and 8 are formed. is there. That is, in this embodiment, after the n-type ion implantation layer 6 is formed by vertical ion implantation using the transfer gate electrode 5 as a mask (FIG. 7C), the sidewall spacer 7 is formed (FIG. 7D).

Next, an n-type ion implantation layer 8 is formed by vertical ion implantation using the transfer gate electrode 5 and the sidewall spacer 7 as a mask (FIG. 7E). Thereafter, ion implantation is performed at a predetermined inclination angle θ while rotating the semiconductor substrate 1 about the center normal line of the transfer gate electrode 5, thereby controlling the threshold voltage using the transfer gate electrode 5 and the sidewall spacer 7 as a mask. To form a p-type ion-implanted region 4 (FIG. 7F). Thereafter, a heat treatment for diffusing the implanted ions is further performed.

According to the manufacturing process of this embodiment, the profile and the channel potential distribution of each ion-implanted layer substantially similar to those shown in FIG. 2 can be obtained.

The first embodiment and the second embodiment described above both relate to the case where the present invention is applied to a MOS-type LDD transistor. However, the idea of the present invention is that a MOS-type transistor other than the LDD structure is used. It can also be applied to the manufacture of An embodiment in which the present invention is applied to the manufacture of a MOS transistor having a structure other than the LDD structure will be described below.

The steps of the third embodiment of the present invention are shown in FIGS. 8A to 8C. This embodiment relates to a method for manufacturing a MOS transistor in which a sidewall spacer is not formed on the side wall of the transfer gate electrode 5. In this embodiment, first, a transfer gate electrode 5 is formed on the transfer gate electrode 3 on the surface of the p-type semiconductor substrate 1 by photolithography and reactive ion etching (FIG. 8A). Next, using this transfer gate electrode as a mask, p-type impurities such as phosphorus or arsenic are vertically injected into the substrate surface to form an ion-implanted layer 6 serving as source / drain regions (FIG. 8B). Next, while rotating the semiconductor substrate 1 in a horizontal plane, p-type boron ions are irradiated from an oblique direction at a predetermined inclination angle to form an ion implantation region 4 for controlling the threshold voltage of the channel region (8C). Figure).

Next, a fourth embodiment of the present invention will be described with reference to FIGS. 9A to 9D. In this embodiment, the transfer gate electrode 5 is formed (FIG. 9A), and n-type ions are implanted using the transfer gate electrode 5 as a mask to form an ion-implanted layer 6 serving as a source / drain (FIG. 9B). This is common to the third embodiment. In this embodiment, after the ion implantation layer 6 is formed, the sidewall spacer 7 is formed on the side wall of the transfer gate electrode 5 (FIG. 9C), and the ion implantation region 4 is formed by oblique rotation ion implantation (FIG. 9D).

A fifth embodiment of the present invention is shown in FIGS. 10A to 10D. In the present embodiment, after the transfer gate electrode 5 is formed on the transfer gate electrode 3 (FIG. 10A), the ion implantation region 4 is formed by oblique rotation ion implantation using this as a mask (FIG. 10B). Next, after forming the sidewall spacers 7 (FIG. 10C), the ion implantation layer 6 is formed by vertical ion implantation (FIG. 10D).

A sixth embodiment of the present invention is shown in FIGS. 11A to 11D. In this embodiment, immediately after the gate electrode 5 is formed (the
11A) and a sidewall spacer 7 is formed (FIG. 11B).
In this state, oblique rotation ion implantation is performed to form an ion implantation region 4 (FIG. 11C), and an ion implantation layer 6 is formed by vertical ion implantation (FIG. 11D).

A seventh embodiment of the present invention is shown in FIGS. 12A to 12D.
In this embodiment, oblique rotation ion implantation of boron ions is performed using the transfer gate electrode 5 as a mask.
First, after the ion implantation region 4 is formed (FIG. 12A), the sidewall spacer 7 is formed (FIG. 12B). Thereafter, phosphorus ions are implanted by vertical ion implantation to form a relatively low-concentration ion-implanted layer 6 (FIG. 12C), and arsenic ions having a smaller thermal diffusion coefficient than phosphorus ions are implanted by vertical ion implantation. A high concentration ion implantation layer 9 is formed (FIG. 12D). Based on the same concept as the LDD structure, the double ion-implanted layers 6 and 9 with different concentrations formed in this way reduce the electric field intensity in the channel and prevent punch-through in the channel. It is. This structure is called a MOS type double diffused drain (DDD) structure transistor.

An eighth embodiment of the present invention is shown in FIGS. 13A to 13D.
This embodiment is similar to the seventh embodiment in that the present invention is applied to the formation of a MOS DDD transistor. In this embodiment, after forming the sidewall spacers 7 (FIG. 13A), boron ions are implanted by oblique rotation ion implantation to form p-type ion implanted regions 4 (FIG. 13A).
B figure). Thereafter, phosphorus ions are implanted by vertical ion implantation (FIG. 13C), and arsenic ions are further implanted (FIG. 13D
This is the same as in the seventh embodiment in that a DDD structure is formed by using FIG.

Also in the third to eighth embodiments described above, the ion implantation region 4 for setting the threshold voltage of the channel is
The distribution is almost the same as in the first embodiment. Therefore, even after the subsequent heat treatment, an impurity concentration distribution as shown by a two-dot chain line in FIG. 2 is obtained, a potential barrier is formed, and the source / drain breakdown voltage can be improved.

[Effects of the Invention] As described above, according to the present invention, the source / drain region and the opposite conductivity type are formed so as to cover the lower end of the high concentration region and the lower concentration region of the source / drain region from the main surface of the semiconductor substrate. Since the impurity region is formed, the channel potential distribution for setting a predetermined threshold voltage is significantly higher near the source / drain region than at the center of the channel region, and a high potential barrier is formed at this portion. And the extension of the depletion layer between the source / drain regions can be suppressed. As a result, the source / drain withstand voltage when no voltage is applied to the transfer gate electrode, that is, punch-through resistance can be improved without increasing the threshold voltage, and punch-through between the source / drain caused by the ALPEN effect can also be improved. Suppressed, new mode soft error (“L → H” error)
Is also prevented.

As a result, even if the device is highly integrated and the effective channel length is shortened, the initial characteristics and the long-term transient characteristics are kept good, and high reliability can be obtained.

In addition, since impurities of the opposite conductivity type to the source / drain regions are obliquely rotated and ion-implanted to form impurity regions covering the source / drain regions, an impurity concentration peak can be formed in the impurity regions. Thereby, the potential distribution in the channel region, that is, the potential barrier can be set to be remarkably high only in the vicinity of the source / drain regions, and the expansion of the depletion layer between the source / drain regions can be suppressed. In addition to improving the source / drain breakdown voltage when no voltage is applied, punch-through between the source / drain caused by the ALPEN effect is suppressed, and a highly reliable semiconductor device manufacturing method can be obtained.

[Brief description of the drawings]

1A, 1B, 1C, 1D, 1E, and 1F,
It is sectional drawing which shows the manufacturing process of the 1st Example of this invention typically sequentially. FIG. 2 shows a MOS LDD formed by the steps of this embodiment.
FIG. 4 is a diagram schematically showing a profile of an ion implantation layer near a channel of a structural transistor and a corresponding impurity ion concentration distribution. FIG. 3 is a diagram showing an ion range and a coordinate system for explaining the theory of numerical analysis for obtaining the impurity ion concentration distribution in each embodiment of the present invention. 4A, 4B, and 4C are diagrams for explaining three factors of the influence of the shielding of the transfer gate electrode 5 in the ion implantation. FIG. 5 is a diagram for explaining a coordinate system in the analysis of the oblique rotation ion implantation. FIGS. 6A and 6B show the weight function W in consideration of the shadowing effect and the punch-through effect of the transfer gate electrode 5. FIG.
(X), W _m0d (x), and distribution function ρ in the depth direction
(Z) shows the distribution of ρ _m0d (z). 7A, 7B, 7C, 7D, 7E, and 7F are:
It is sectional drawing which shows the manufacturing process of the 2nd Example of this invention typically sequentially. 8A, 8B, and 8C are cross-sectional views schematically schematically showing manufacturing steps in the third embodiment of the present invention. FIGS. 9A, 9B, 9C, and 9D are cross-sectional views schematically schematically showing manufacturing steps in a fourth embodiment of the present invention. 10A, 10B, 10C, and 10D show the fifth embodiment of the present invention.
FIG. 7 is a cross-sectional view schematically schematically illustrating a manufacturing process in the example of FIG. 11A, 11B, 11C, and 11D show the sixth embodiment of the present invention.
FIG. 7 is a cross-sectional view schematically schematically illustrating a manufacturing process in the example of FIG. FIGS. 12A, 12B, 12C, and 12D show the seventh embodiment of the present invention.
FIG. 7 is a cross-sectional view schematically schematically illustrating a manufacturing process in the example of FIG. 13A, 13B, 13C, and 13D show the eighth embodiment of the present invention.
FIG. 7 is a cross-sectional view schematically schematically illustrating a manufacturing process in the example of FIG. 14A, 14B, 14C, 14D, 14E, 14F
FIG. 2 is a cross-sectional view schematically showing the manufacturing steps in the first conventional example in sequence. 15A, 15B, 15C, and 15D are cross-sectional views schematically schematically showing the outline of the manufacturing process of the second conventional example. FIG. 16 is a diagram schematically showing a profile of an ion implantation layer near a channel and a corresponding impurity ion concentration of a MOS LDD structure transistor formed by the first conventional example. FIG. 17 is a diagram schematically showing a profile of an ion implantation layer near a channel of a MOS LDD transistor formed by a method similar to that of the second conventional example, and a corresponding distribution of impurity ions. . In the figure, 1 is a semiconductor substrate, 2 is an element isolation region, 3 is a transfer gate insulating film, 4 is an ion implantation layer, 5 is a transfer gate electrode, 7 is a side wall spacer,
8 and 9 are ion implantation layers. In the drawings, components denoted by the same reference numerals indicate the same or corresponding elements.

Claims (2)

(57) [Claims] A first conductive type semiconductor substrate; a pair of second conductive type first impurity regions disposed on a main surface of the semiconductor substrate with a channel region interposed therebetween; the channel region and the pair of first impurity regions; And a pair of second conductivity types, which are arranged with the first impurity region interposed therebetween and contain a higher concentration of impurities than the first impurity region, and become a source region and a drain region together with the pair of first impurity regions. A transfer gate electrode formed at a position covering the channel region on the surface of the semiconductor substrate with a gate insulating film interposed therebetween and having an impurity concentration substantially equal to that of the second impurity region. And forming a lower end of both the first and second impurity regions from the main surface of the semiconductor substrate closer to the pair of first impurity regions than a center of the channel region. A semiconductor device comprising a pair of third impurity regions of a first conductivity type. 2. A step of forming a transfer gate electrode on a main surface of a semiconductor substrate of a first conductivity type via an insulating film, and obliquely rotating ion implantation of an impurity of the first conductivity type to form a transfer gate electrode under the transfer gate electrode. Forming a first impurity region opposing the channel region on the main surface of the semiconductor substrate; and ion-implanting an impurity of a second conductivity type to form a second impurity region in the first impurity region. Forming an insulating sidewall spacer on the side wall of the transfer gate electrode; and ion-implanting a second conductivity type impurity to form the second impurity into the first impurity region. Forming a third impurity region containing a higher concentration of impurity than the impurity region and serving as a source region and a drain region together with the second impurity region. Law.