KR940000388B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

No content.

Description

Manufacturing Method of Semiconductor Device

1A to 1F are cross-sectional views schematically showing a manufacturing process of one embodiment of the present invention in sequence.

2 is a diagram schematically showing a profile of an ion implantation layer and a corresponding impurity ion concentration distribution in the vicinity of a channel of the MOS type LDD structure transistor formed by the process of this embodiment.

3A to 3F are sectional views schematically showing a manufacturing process of another embodiment of the present invention in sequence.

FIG. 4 is a diagram showing ion irregularities and coordinate systems in order to explain the theory of numerical analysis for obtaining impurity ion concentration distributions in the examples of the present invention.

5A to 5C are diagrams for explaining three factors of the influence of shielding of the transfer gate electrode 5 in ion implantation.

6 is a diagram for explaining a coordinate system in the analysis of gradient rotation ion implantation.

7A and 7B show weight functions (W (x), W _mod (x)) and depth direction distribution considering shadowing and punchthrough effects of the transfer gate electrode 5; Display the distribution of the function (ρ (z), ρ _mod (z)).

8A to 8F are sectional views schematically showing a manufacturing process sequentially in the first conventional example.

Fig. 9 is a diagram schematically showing the profile of the ion implantation layer and the impurity ion concentration corresponding thereto in the vicinity of the channel of the MOS type LDD structure transistor formed by this conventional example.

10A to 10D are cross-sectional views schematically showing an outline of a manufacturing process of a second conventional example.

FIG. 11 is a diagram schematically showing a profile of an ion implantation layer and a distribution of impurity ion concentrations corresponding thereto in the vicinity of a channel of a MOS type LDD transistor when formed by a method similar to the conventional example.

* Explanation of symbols for main parts of the drawings

1: semiconductor substrate 2: device isolation region

3: transfer gate insulating film 4: ion implantation layer

5: transfer gate electrode 7: side wall spacer

8: ion implantation layer

(In the drawings, the same symbols indicate the same or equivalent elements.)

This invention relates to a method for manufacturing a semiconductor device, in particular, MOS (Metal Oxide Semico)

A method of manufacturing a semiconductor device for forming an nductor) LDD (Lightly Doped Drain) structure transistor.

The basic structure of a MOS field effect transistor is a source for supplying a carrier to both sides of a so-called MOS capacitor having a metal oxide interposed therebetween on a Si substrate, and a drain for catching the carrier. And placed it.

The metal electrode on the oxide film is called a transfer gate electrode because it has a function of controlling conductance between the source and the drain.

As the material of the transfer gate electrode, a metal silicide formed by heat-treating a high melting point metal such as polysilicon doped with impurities or tungsten deposited on polysilicon in an inert gas is used.

In the state where the voltage (gate voltage) of the transfer gate electrode is lower than the threshold voltage (V _th ) required for inverting the conductivity type near the Si substrate surface (channel) between the source and the drain, the source / drain is separated by the pn junction. And no current flows. When a gate voltage of V _th or more is applied, the conductive type of the channel surface is inverted, a conductive type layer such as a source / drain is formed in this portion, and a current flows between the source / drain.

However, if the concentration distribution of impurities at the boundary between the source / drain and the channel is abrupt, the electric field strength of this portion is increased. When the carrier obtains energy by this electric field and a so-called hot carrier is generated, it causes the source / drain breakdown voltage to deteriorate.

The MOS type LDD structure is to reduce the electric field strengthening and improve the source / drain breakdown voltage by lowering the impurity concentration near the source / drain channel to smooth the concentration distribution change.

As a structure method of a conventional MOS LDD structure transistor, for example, shown in Figs. 8A to 8F. In this manufacturing method, first, the transfer gate oxide film 3 is formed on the p-type semiconductor substrate 1 in the element formation region surrounded by the element isolation insulating film 2 by the so-called LOCOS method (Fig. 8A).

Next, for the threshold voltage control, p-type impurities such as boron ions are implanted into the entire surface on the semiconductor substrate 1 to form the ion implantation layer 4 (Fig. 8B).

Thereafter, a polysilicon film is deposited on the entire surface of the transfer gate oxide film 3 by reduced pressure CVD or sputtering to form a transfer gate electrode 5 by photoetching (Fig. 8C).

As the transfer gate electrode 5, instead of polysilicon, tungsten or molybdenum (

molybdenum), high melting point metals such as titanium, or silicides thereof, and polysilicon two-layer films may be formed.

The transfer gate electrode 5 is doped with phosphorous ions to increase conductivity. In this case, the transfer gate electrode 5 is n-type, and is the same as the conductivity type of the channel, that is, the conductivity type of the source / drain. Therefore, in the state where the gate voltage is not applied to the transfer gate electrode 5, diffusion occurs on the surface of the p-type channel under the influence of the n-type impurity, and Vth is lowered. This is what happens.

The ion implantation layer 4 described above is intended to ensure Vth against the influence of the impurity ions doped in the transfer gate electrode 5 by injecting the p-type impurity in advance.

Next, with the gate electrode 5 as a mask, n-type impurities such as phosphorous ions are implanted perpendicularly to the surface of the semiconductor substrate 1 to form an n-type ion implantation layer 6 (Fig. 8D). ).

Thereafter, an insulating film, such as silicon dioxide, is deposited on the semiconductor substrate 1 on the entire surface by a reduced pressure CVD method or an atmospheric pressure CVD method, and anisotropic etching is performed on this to form the sidewall spacers 7. (Figure 8e).

Next, n-type impurities such as arsenic ions are implanted perpendicularly to the surface of the semiconductor substrate 1 using the transfer gate electrode 5 and the side wall spacers 7 as masks, and the ion implantation layer 6 An n-type ion implantation layer 8 having a higher concentration is formed (FIG. 8f).

Thereafter, through the heat treatment for thermal diffusion of the implanted impurity ions, a MOS type LDD structure transistor is completed.

In the above conventional example, a p-type semiconductor substrate is used as the substrate, but a p-wall which is a region in which p-type impurities are implanted at least in the vicinity of the substrate surface is used. In some cases, an n-type semiconductor substrate or a substrate formed with an n-month, which is an area in which n-type impurities are injected at least in the vicinity of a surface, may be used as the substrate. In this case, the transfer gate electrode 5 is p-type, the ion implantation layer 4 for threshold voltage control is n-type, and the p-type ion implantation layers 6 and 8 are formed in the source region and the drain region.

Since the conventional example is based on ion implantation only in the direction perpendicular to the surface of the semiconductor substrate 1, it is necessary to form the ion implantation layer 4 for the threshold voltage control before the transfer gate electrode 5 is formed.

On the other hand, as a method of forming each ion implantation layer after formation of the transfer gate electrode 5 by application of the gradient ion implantation method, the thing of Unexamined-Japanese-Patent No. 61-226968 is mentioned.

In the method for manufacturing a MOS semiconductor device described in the publication, with reference to FIGS. 10A to 10D, first, the field oxide film 12 and the gate 14 formed on the p-type semiconductor substrate 11 are masked. As a result, the phosphorus ion is implanted at an acceleration voltage of 20 keV to form the n-type region 18 (second).

10a degrees).

Subsequently, when boron ions are implanted using the gate electrode 14 as a mask at an incidence angle of 30 ° and an acceleration voltage of 30 keV, impurities are implanted in front of the incidence, and the channel formation region immediately below the gate 14 is an n-type region 18 on the right side wall. The p-type region is formed inside () (Fig. 10b).

The same gradient ion implantation is also performed on the opposite side to form p-type regions 19a and 19b in the form of enclosing all side and bottom surfaces of n-type region 18 (Fig. 10C).

Next, the photoresist 20 is patterned and formed around the gate 14, and when arsenic ions are implanted at a high concentration with a mask, an n-type region 21 serving as a source / drain is formed (FIG. 10D).

Finally, the silicon oxide film 22 is deposited on the entire surface by the CVD method, and contact holes are formed in a predetermined place of each region of the gate, source, and drain by a reactive ion etching method, and aluminum is deposited and patterned. An n-channel MOS semiconductor device is completed.

As described above, according to this conventional example, since the p-type regions 19a and 19b are formed by gradient ion implantation, each ion implantation layer is formed after the gate electrode 14 is formed.

In the conventional method of manufacturing a semiconductor device, in the case of the first conventional example, the diffusion layer for the threshold voltage control is formed by vertical ion implantation on the front surface of the semiconductor substrate 1 before the transfer gate electrode 5 is formed. The phosphorus ion implantation layer 4 is formed.

Therefore, the p-type impurity ion concentration distribution over the entire channel region is almost the same as indicated by the broken line in the graph of FIG.

After the process of thermal diffusion, this tendency does not change significantly, and it is distributed as shown by the two-point long line in FIG. Since the threshold voltage is determined corresponding to the almost average value of the channel potential of the entire channel region, the average value of the concentration distribution of the ion implantation layer 4 to be formed when the predetermined threshold voltage is set is also determined correspondingly.

In the first conventional example, the concentration distribution of the ion implantation layer 4 near the channel region, and moreover, the distribution of the channel potentials are almost the same, and the channel potentials near the source region and the drain region are relatively low, which is almost equal to the potential of the center of the channel. It becomes a value.

Therefore, a sufficient potential barrier is not formed near the source / drain regions at both ends of the channel region. Therefore, when the device is highly integrated, the length of the transfer gate electrode or the effective channel length becomes short, and penetration through the diffusion of the depletion layer between the source and the drain easily occurs, and the breakdown voltage characteristics between the source and the drain are improved. Lowers. Penetration easily occurs due to the diffusion of the depletion layer, and the breakdown voltage characteristic between the source and the drain decreases. In order to suppress diffusion of this depletion layer, when the concentration of the source / drain regions is increased, the effective channel length becomes short, and the threshold voltage decreases.

In addition, radiation of radioisotopes in the package is caused by a so-called ALPEN (Alpha Particle Source / Drain Penetration) effect in which the α particles penetrate the source / drain region, so that the α particles generate carriers in the channel region. funneling)

The electrons and holes of this carrier are separated by an electric field between the drain and the back surface of the substrate and depleted. As a result, transient punchthrough occurs between the source and the drain during the transistor operation, causing a new mode soft error (“L → H” soft error).

As described above, in the manufacturing method similar to the first conventional example, there is a problem that the source / drain breakdown voltage is deteriorated and soft errors are likely to occur with high integration of the device, resulting in deterioration of initial characteristics and long-term reliability of the device.

Incidentally, the gradient ion implantation method used in the formation of the p-type regions 19a and 19b in the second conventional example is applied to the ion implantation layer 4 in the manufacturing process of the MOS type LDD structure transistor having the configuration of the first conventional example. Although it may be applied to the formation of, in this case, the following problems arise.

In the first conventional example, the formation of the ion implantation layer 4 is performed by using the transfer gate electrode 5 and the sidewall spacer 7 as a mask, and injecting the ion inclined from the symmetrical two directions of the predetermined inclination angle (hereinafter, [the tilt fixing]). Ion implantation layer], and the impurity concentration distribution near the substrate surface corresponding to the ion implantation layer 4 immediately after completion of ion implantation are indicated by broken lines in FIG.

As can be seen from FIG. 11, when the gradient ion implantation is applied, the profile of the ion implantation layer 4 is strictly changed at right and left positions immediately below the center of the transfer electrode 5 immediately after ion implantation. .

This is because the impurity ion beam having a predetermined irradiation pattern is irradiated at a fixed inclination angle at the same position for a predetermined time in the same pattern by a masking action of the sidewall spacer 7, so that the influence of the irradiation pattern is affected by the impurity concentration. This is due to the significant spread of the distribution.

Corresponding to the profile of the ion implantation layer 4, the concentration distribution of impurity ions near the substrate surface is very high P-type impurity concentration immediately below the left and right sides of the transfer gate electrode 5 immediately after ion implantation is completed. Is displayed and is lowered at the center.

After the ion implantation is completed, a heat treatment step for diffusing the impurity ions is required. It is known that the rate of movement of impurity ions in this diffusion is proportional to the gradient of impurity concentration.

Therefore, in the region having a strict impurity concentration change such as indicated by the broken line in FIG. 11 immediately after completion of ion implantation, diffusion proceeds rapidly in an extremely short heat treatment. For this reason, if the heat treatment is to be performed under the necessary conditions in the device, the averaging is particularly easy in a region where the concentration distribution is rough, and after the heat treatment, a gentle concentration distribution indicated by the two-point long line in FIG. 11 is obtained.

As a result, as in the case of the first conventional example, the concentration distribution near the channel region, and further, the channel potential distribution, become close together, so that sufficient potential barrier is not formed near the source / drain regions at both ends of the channel region. there is a problem.

In order to solve the above problems, the present invention forms a high potential barrier only near the source / drain at both ends of the channel region, so that even if the device is highly integrated, characteristics such as the source / drain breakdown voltage do not deteriorate. It is an object to provide a method for manufacturing a semiconductor device.

A semiconductor device manufacturing method of the present invention comprises a first step of forming a transfer gate electrode on a semiconductor substrate having at least a conductive region near the surface with an insulating film therebetween, using the transfer gate electrode as a mask, Implanting impurity ions of a conductivity type opposite to that of the semiconductor substrate, forming a low concentration source region and a drain region, and forming a sidewall spacer of an insulator on the sidewalls of both sides of the transfer gate electrode. A third step and a fourth step of forming a highly concentrated source region and a drain region by implanting impurity ions of a conductivity type opposite to that of the semiconductor substrate on the surface of the semiconductor substrate using the sidewall spacer and the transfer gate electrode as masks; And a fifth step of performing a heat treatment for thermally diffusing the implanted impurity ions.

According to the present invention, between the second process and the third process, or between the fourth process and the fifth process, a predetermined inclination angle is made on the surface of the semiconductor substrate from the normal direction of the semiconductor substrate, and the semiconductor substrate is rotated by one normal line. And a step of implanting impurity ions of a conductive type such as a semiconductor substrate in the rotated state.

According to the present invention, by forming the ion implantation layer for the threshold voltage control by the gradient rotation injection method using the transfer gate electrode as a mask, the impurity concentration distribution immediately after the ion implantation is completed, compared with the gradient fixed ion implantation method. It becomes more gentle.

For this reason, in the subsequent diffusion process by heat treatment, even when heat treatment is performed under conditions necessary for the device, a sudden averaging of the concentration distribution does not occur.

Therefore, even after diffusion, a distribution almost similar to that immediately after ion implantation is maintained.

As a result, the concentration distribution of the impurity after diffusion can be made significantly higher in the source / drain vicinity at both ends of the channel than in the center vicinity of the channel region. Therefore, the channel potential of the channel region is also distributed corresponding to this concentration distribution, is low near the center of the channel region, and is markedly high at both ends. As a result, high potential barriers are formed at both ends of the channel region, and diffusion of the depletion layer between the source and drain regions is suppressed.

As a result, penetration of the depletion layer between the source and the drain is less likely to occur, and the breakdown voltage between the source and the drain is improved. In addition, even if alpha particles enter the source / drain region, the funneling phenomenon is also suppressed by the high potential barrier at both ends of the channel region, and transient punch-through between the source and the drain caused by the ALPEN effect is also prevented.

EXAMPLE

An embodiment of the present invention will be described below with reference to FIGS. A to 1f and 2.

The manufacturing process of the 1st Example of this invention is as showing in FIGS. 1A-1F.

First, the transfer gate insulating film 3 is formed on the p-type semiconductor substrate 1 in the element formation region surrounded by the element isolation region 2 by the LOCOS method (FIG. 1A).

Next, a polysilicon film is deposited on the entire surface of the transfer gate insulating film 3 by the reduced pressure CVD method to form the transfer gate electrode 5 by photoetching (FIG. 1B).

The transfer gate electrode 5 is photoetched by depositing two layers of high melting point metals such as tungsten, molybdenum and titanium, and silicon by pressure reduction CVD or sputtering, except in the case of forming a single layer of polysilicon. It can also form by doing.

In addition, a so-called high melting point metal silicide obtained by silicifying the high melting point metal may be deposited and formed by photoetching. The transfer gate electrode 5 is doped with, for example, impurity ions such as phosphorous ions for the purpose of enhancing its conductivity, and becomes a conductive type opposite to that of the semiconductor substrate, that is, a conductive type such as a channel.

As a result, ions, etc., enter the channel and the threshold voltage decreases. Therefore, it is necessary to raise the threshold voltage by forming the ion implantation layer 4 mentioned later.

Next, boron ions, which are the same p-type impurity ions as the semiconductor substrate 1, are injected into the front surface of the semiconductor substrate 1 from a direction in which a predetermined inclination angle θ is formed with respect to the normal direction. At the same time, the semiconductor substrate 1 is rotated around the normal line in the center of the transfer gate electrode 5. By this gradient rotation ion implantation, the p-type ion implantation layer 4 for the threshold voltage control is formed using the transfer gate electrode 5 as a mask (first

c).

If the inclination angle θ of ion implantation is about 10 degrees or less, the so-called channeling effect in which ions penetrate into the crystal axis direction to an unusual depth occurs, which is not preferable. Moreover, even if θ is about 10 degrees or more, when the angle is about 30 degrees or less, ion implantation is not sufficiently performed directly under the transfer gate electrode 5, and it is difficult to control the threshold voltage.

Moreover, when (theta) exceeds about 60 degrees, there exists a problem that the amount of ion implantation just under the transfer gate electrode 5 will increase, and a threshold voltage will become high. Therefore, the inclination angle θ of ion implantation is preferably set to 30 ° or more and 60 ° or less, and is usually performed at about 45 °.

After that, phosphorus ions which are n-type impurity ions opposite to the conductivity type of the semiconductor substrate 1 are injected into the front surface of the semiconductor substrate 1 from the normal direction.

Thus, the n-type ion implantation layer (using the transfer gate electrode 5 as a mask)

6) is formed (FIG. 1D).

Next, an oxide film of silicon dioxide is deposited on the front surface of the semiconductor substrate 1 by CVD or the like, and anisotropic etching is performed on this to form the sidewall spacers 7. Then, arsenic ions, which are n-type impurity ions, are injected into the front surface of the semiconductor substrate 1 from the normal direction.

As a result, the n-type ion implantation layer 8 is formed using the transfer gate electrode 5 and the side wall spacers 7 as mascots. At this time, the ion implantation amount into the ion implantation layer 6 is set to be much lower than the concentration of the ion implantation layer 8 because of the LDD structure formation.

Further, by performing heat treatment, the ion implantation layers 4, 6, and 8 are activated to form diffusion layers of impurity ions.

In this embodiment, a p-type semiconductor substrate 1 is used as the substrate for forming the MOS type LDD structure transistor. Instead, p-well (p-well), which is a p-type region at a predetermined depth from the substrate surface, is used instead. Well formed may also be used.

The conductivity type on the substrate side is not limited to the p-type, but the substrate side and the ion implantation layer

It is also possible to form (4) as n type and to form ion implantation layers 6 and 8 as p type.

The impurity ion concentration distribution of the MOS type LDD structure transistor manufactured as described above is as shown in FIG. The profile and channel potential distribution of the ion implantation layer 4 when the oblique rotation injection method is used, in addition to the LSS theory, which is the theory of vertical ion implantation of an amorphous target, the shadowing effect of the transfer gate electrode 5 and the gate It can be calculated by numerical analysis with a weight function considering the punch-through effect.

The distribution of impurity ion concentration in FIG. 2 schematically shows the distribution of the surface of the channel region on the basis of this calculation result. The outline of the theory of numerical analysis for obtaining the impurity ion concentration distribution in FIG. 2 will now be described. The distribution of impurities injected into the semiconductor substrate 1 is first determined by the injection amount, the acceleration voltage, and the injection direction. This relationship can be seen by analyzing the mechanism of collision between the implanted ion and the target atom.

In addition, a heat treatment condition after implantation is mentioned as a second element for determining impurity distribution. That is, the distribution determined by the collision with the target atom is deformed by the diffusion during the heat treatment. First, a first element that does not contain heat treatment is considered. Even if the target substance is crystalline, if ion implantation is performed in a random direction such that no channeling effect occurs, it is not considered to be amorphous.

Therefore, the theory of ion implantation in amorphous phase is applied. Implanted ions can collide with the target atom and bend its direction of motion, drawing a trajectory as shown in FIG. The distance (R) at which the ions move is determined and projected to the injection direction thereof.

Rp) is called private projection. In addition, the implantation ion has a xy plane direction component (R _xy ). Each of these irregularities is spreading with a distribution around the average value because collisions occur at random. Lindhard et al. Derived an integral equation that gives these non-uniform distributions, and presented an equation of the distribution of implanted ions that shows a good agreement with the experimental values. This is called LSS theory (for example, "Industrial Society of Japan, Electronics Collection (8) Ion Implantation Technique, p29-p40)").

The formula of the three-dimensional concentration distribution (N) (X, Y, Z) of impurity ions derived from this LSS theory is as shown below.

[Equation 1]

here,

Next, in addition to the LSS theory, a numerical analysis incorporating a weight function considering the shadowing effect and the gate punch through effect of the transfer gate electrode 5 will be described. Inclined rotation injection includes three factors shown in FIG. 5A, FIG. 5B, and FIG. 5C. First, the first factor is a factor of the shadow wing (see also FIG. 5A) to the implantation ions of the edge of the transfer gate electrode 5, which is referred to as factor [A].

The second factor is obtained by directly entering the lower portion of the transfer gate electrode 59 from the surface of the semiconductor substrate 1 (see also part 5b), which is referred to as factor [B]. The side of the gate electrode 5 is caused by punch-through of ions through the polysilicon gate 5b (see also FIG. 5C), which is referred to as factor [C].

These three factors [A] [B] [C] all work to reduce the number of ionized water injected into the semiconductor substrate 1 when the transfer gate electrode 5 does not exist. Therefore, the effect can be put into the concept of probability. In other words, it is thought that the ratio of the ionized water injected into the substrate when the transfer gate electrode 5 actually exists is relative to the ionized water injected into the semiconductor substrate 1 when the transfer gate electrode 5 does not exist. This is called weight. This weight first obviously depends on the distance from the transfer gate electrode 5.

Then, the impurity distribution formed by the gradient rotation ion implantation is roughly composed of two components. One is injected from the surface of the semiconductor substrate 1 and contains the factors [A] [B]. The other is injected from the polysilicon gate side, and contains a difactor [C]. Factor [A] [B] [C] is put in weight, and impurity distribution N (x, z) formed by oblique rotation injection is expressed as follows.

here,

N _o : The dose per unit area of impurity ions

θ: tilt angle of the ion implantation direction with respect to the direction perpendicular to the substrate

W (x): Weight function in the x direction by the factor [A] [B]

W _mod (X): Weight function in the x direction by the factor [C]

ρ (x): concentration distribution in the z direction when W _mod (X) = 0

ρ _mod (Z): concentration distribution in the z direction when W (x) = 0 and W _mod (X) = 1.0

In addition, the first term [N _o cosθW (x) ρ (z)] of the common sense indicates a component injected from the surface of the semiconductor substrate, and the second term [N _o cosθW _mod (X) ρ _mod (Z)] The component injected from the side surface of the polysilicon gate 5b is shown. The coordinate system takes the origin 0 on the surface of the semiconductor substrate 1 under the side surface of the transfer gate electrode 5, and takes the x, y, and z axes as shown in FIG. As a specific example of the distribution of the weight function, θ = 45 °, the irradiation energy E of ion implantation _{lmp = 42keV, N o = 2.8} × 10 13 W (x) with respect to the _{^{cm -2, W mod (X)}} , ρ (z ) and ρ _mod (Z) are shown in FIGS. 7A and 7B. The curve obtained by the broken line of the graph shown in FIG. 2 is a graph showing the result obtained by calculating the dispersion ion concentration distribution near the channel surface from the function value thus obtained and the equation of N (x, y, z).

As can be seen from this graph, the impurity immediately after completion of ion implantation formed by gradient rotation ion implantation tends to increase the p-type ion concentration near the both ends of the channel, but the slope shown in FIG. It is changing slowly compared to the fixed injection.

This is considered to be based on the following reasons, as described also in the description of the prior art. First, in the fixed fixed ion implantation, irradiation ions whose concentration distribution rapidly changes at the boundary of the shadow by being shielded by the transfer gate electrode 5 and the side wall spacer 7 are irradiated with a constant time at the same inclination angle. Therefore, the concentration distribution immediately after the completion of ion implantation is also sharply changed under the influence of the shadow.

On the other hand, in the oblique rotation injection, since the irradiation ions and the semiconductor substrate 1 rotate each other, the shadow by the shielding of the transfer gate electrode 5 and the side wall spacer 7 is moved at all times. It can be considered that the effect on the change of impurity ion concentration distribution caused by this is averaged and mitigated, resulting in a concentration distribution having a gentle change.

As described above, the impurity profile formed by the oblique rotation injection is changed slowly even after the ion implantation, and therefore, it is difficult to be affected by the necessary heat treatment thereafter. That is, since the diffusion of impurities by heat treatment is proportional to the spatial gradient of the impurity profile, the impurity profile formed by the oblique rotation injection does not change so much even after the heat treatment. This can realize the optimum distribution of the impurity profile after heat treatment under the heat treatment conditions required to maintain the characteristics of the device, for example, an optimum heat treatment condition for securing refresh characteristics in a DRAM (Dynamic Random Access Memory). It means.

That is, even if the impurity ion profile formed by the oblique rotation injection is subjected to heat treatment under the optimum conditions in the device afterwards, since the influence of diffusion due to the heat treatment is not so strong as that, the optimum impurity ion heat treatment conditions Can be determined almost independently.

On the other hand, for example, the impurity profile formed by inclined fixed ion implantation is as steep as possible immediately after implantation, and is strongly influenced by the necessary heat treatment thereafter. Therefore, the heat treatment conditions that can maintain the optimum distribution of the impurity ion profile are often not the optimum heat treatment conditions in the device. On the contrary, in the case where the optimum heat treatment is performed in the device, there is a high possibility that the optimum impurity ion profile cannot be obtained after the heat treatment.

As described above, as the impurity ion profile changes immediately after completion of ion implantation, the optimum impurity ion profile can be obtained under the optimum heat treatment conditions in the device. In this sense, the inclined rotational implantation can be said to be an ion implantation method which is superior in device design than inclined fixed implantation.

The threshold voltage almost corresponds to the average value of the entire channel region of the channel potential. If this is explained qualitatively, the outline will be as follows. Increasing the p-type impurity ion concentration in the portion of the length (ΔL shown in FIG. 2) near the source / drain region increases the threshold voltage of this portion, and thus the carrier mobility due to the scattering of impurities in this portion, that is, the electric field. A decrease in the drift speed in proportion to the intensity of. Therefore, the threshold voltage V _th of the entire transistor is also high.

Thereby, by lowering the p-type ion concentration in the center portion of the channel than the conventional transistor, the threshold voltage of this portion decreases, and the mobility of this portion is increased. This makes it possible to lower the threshold voltage V _th of the entire channel. From the above, the threshold voltage V _th of the entire channel is determined corresponding to an almost average value of the p-type impurity ion concentration of the entire length L of the channel length 2nd degree.

Therefore, the distribution of the channel potential for obtaining the predetermined threshold voltage is made by the oblique rotation injection, so that the channel potential near the source / drain region is higher than the oblique fixed injection method.

As a result, since this portion forms a potential barrier and suppresses the diffusion of the depletion layer between the source and drain regions, the source / drain breakdown voltage when no voltage is applied to the transfer gate electrode 5 is improved. In addition, the so-called funneling phenomenon that the? Particles enter the source / drain region into the punch-through channel region, which can be seen in the ALPEN effect, is reversed by this dislocation barrier. Therefore, excessive punch-through between the source and the drain caused by the ALPEN effect, and a soft error (“L → H” error) caused by the ALPEN effect are also suppressed.

As described above, according to this embodiment, a high potential barrier is formed near the source / drain at both ends of the channel region, so that even when the device is highly integrated and the effective channel length is shortened, good initial characteristics can be obtained.

In addition, the transient characteristics can be operated with good reliability. Next, another Example of this invention is described based on FIG. 3A-FIG. 3B. In the manufacturing process of this embodiment, the transfer gate insulating film 3 is formed in the element formation region surrounded by the element isolation region 2 on the p-type semiconductor substrate 1 by the LOCOS method (Fig. 3A). Moreover, the same as in the embodiment shown in FIG. 1 until the transfer gate electrode 5 is formed (FIG. 3B).

The present embodiment differs from the above embodiment by forming the p-type ion implantation layer 4 for suppressing the threshold voltage by the gradient rotation ion implantation after the n-type ion implantation layers 6 and 8 are formed. Is the point.

That is, in this embodiment, after the n-type ion implantation layer 6 is formed by vertical ion implantation using the transfer gate electrode 5 as a mask (FIG. 3C), the sidewall spacer 7

) (Fig. 3d).

Next, the n-type ion implantation layer 8 is formed by vertical ion implantation using the transfer gate electrode 5 and the sidewall spacer 7 as a mask (FIG. 3E). Thereafter, while the semiconductor substrate 1 is rotated about the normal line in the center of the transfer gate electrode 5, ion implantation is performed at a predetermined inclination angle θ, whereby the transfer gate electrode 5 and the sidewall spacer 7 Is used as a mask to form the p-type ion implantation layer 4 for suppressing the threshold voltage (Fig. 3E).

Thereafter, heat treatment for diffusing the implanted ions is performed. Also in the manufacturing process of this embodiment, the profile and channel potential distribution of each ion implantation layer almost similar to those shown in FIG. 2 can be obtained. As described above, according to the present invention, a channel potential distribution for setting a predetermined threshold voltage is formed by forming an ion implantation layer for suppressing a threshold voltage by a gradient rotation injection method using a transfer gate electrode as a mask. As a result, only near the source / drain can be made significantly higher than near the center of the channel region.

As a result, a high potential barrier is formed at both ends of the channel region without increasing the threshold voltage, thereby suppressing diffusion of the depletion layer between the source and drain regions.

This improves the source / drain breakdown voltage when no voltage is applied to the transfer gate electrode. In addition, the high potential barrier also suppresses punchthrough between the source and the drain caused by the ALPEN effect, and also prevents a new mode soft error (“L → H” error).

Therefore, even if the device is highly integrated and the effective channel length is shortened, the initial characteristics and the long-term transient characteristics are kept good, and the manufacture of a highly reliable semiconductor device is realized.

Claims (1)

A first step of forming a transfer gate electrode with an insulating film interposed therebetween on at least a semiconductor substrate having a limiting conductivity region near the surface; and using the transfer gate electrode as a mask, the surface of the semiconductor substrate is opposite to the semiconductor substrate. A second step of implanting impurity ions of a conductivity type to form a low concentration source region and a drain region, a third step of forming sidewall spacers of an insulator on sidewalls of both sides of the transfer gate electrode, and the sidewall A fourth step of implanting impurity ions of a conductivity type opposite to that of the semiconductor substrate on the surface of the semiconductor substrate by using a spacer and the transfer gate electrode as a mask, and forming a highly concentrated source region and a drain region; In the method for manufacturing a semiconductor device, comprising a fifth step of performing a heat treatment for thermal diffusion of ions, Between the second process and the third process, or between the fourth process and the fifth process, a predetermined inclination angle is formed on the surface of the semiconductor substrate from the normal direction of the semiconductor substrate, and the semiconductor substrate is one normal. And implanting impurity ions of the same conductivity type as that of the semiconductor substrate in a state where the rotation is performed with the rotation axis as the rotation axis.

Images