JPH03204754A - I/o bus control system - Google Patents

Abstract

PURPOSE:To execute the data transfer at a high speed by separating a peripheral control part and an I/O bus by a data transfer latch gate with respect to the constitution of an I/O peripheral equipment control circuit. CONSTITUTION:A data transfer latch gate 9 provided between each I/O peripheral equipment control part of a high speed file control part 3, a high speed data communication system control part 5, a low speed data communication control part 6 and a low speed file control part 7, and an I/O bus 10 separates the I/O bus 10 operated by a high speed cycle time and the peripheral control part operated by a comparatively low speed cycle time so that the independent operation can be executed. Data of the peripheral control part is stored temporarily in the data transfer latch gate 9, and thereafter, in accordance with the data transfer quantity of each peripheral control part, the I/O bus 10 is subjected to time division to a time slot and a multiplex transfer is executed. In such a way, the data transfer can be executed at a high speed by a simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control system for a microprocessor and a peripheral control unit in microprocessor application equipment.

[Conventional technology]

In the conventional I/O bus control method, as shown in Figure 5,
It was configured using a bus connection system that shared address lines and data input/output lines between the microprocessor and peripheral control unit. With such a configuration, the peripheral devices are controlled by the host processor, making it possible to improve the functionality of input/output control.

However, as microprocessors become faster and data transfer speeds of peripheral devices become faster, it has become necessary to process input/output data at higher speeds. Conventionally, in order to increase the speed of input/output processing, a dedicated data transfer bus has been provided for each I/O processing device to cope with the increase in speed. Also, JP-A-63
As described in Publication No. 177246, bus usage efficiency is improved by time-sharing I/O paths into fixed-length time slots and allocating slots according to the data transfer speed of each peripheral control device. , methods for high-speed, large-capacity data transfer have also been devised. Furthermore, the same I/O as high-speed I/O
Low-speed I/O connected to /O bus! There is also a time slot assignment for the me lid, making it possible to transfer data.

[Problem to be solved by the invention]

According to the above-mentioned prior art, high-speed, large-capacity data transfer is possible using a dedicated bus system or a time slot time division multiplex bus system. However, in the conventional configuration, the scale of the hardware is large, which is an obstacle to lowering the price.

An object of the present invention is to provide a control method that enables high-speed data transfer at low cost using an I/O peripheral device control circuit having a shared bus configuration.

(Means for Solving Problem a) The above object is to connect the peripheral control unit to the I/O bus through a data transfer latch gate without directly connecting it to the I/O path. This is achieved by using a shared bus configuration and a hardware configuration that performs high-speed data transfer by time-division multiplexing the input/output data.

[Effect]

A data transfer latch gate provided between each peripheral control unit and the I/O bus separates the I/O bus that operates at a high-speed cycle time from the peripheral control unit that operates at a relatively slow cycle time. The data of the 0 peripheral control units that enable independent operation is temporarily stored in the data transfer latch gate, and then the I/O bus is time-divided into time slots according to the data transfer amount of each peripheral control unit. Perform multiple transfer. This effect enables high-speed data transfer with a simple configuration.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 1, each I/O peripheral device control unit of the high-speed file control unit 3, high-speed data communication system control unit 5%, low-speed data communication system control unit 61, and low-speed file control unit 7 includes a peripheral control unit access controller. 8 and a data transfer latch gate 9 to the I/O path /O. The transfer data of each control section is transferred from the control section to the memory 4 by the DMA controller 2 . The data transfer speed of each 1/O peripheral device control unit, which controls the microprocessor IFX and processes input/output data, is different, and these data transfers may occur simultaneously. In the example, high-speed file control system 3 is 4
MB/s, high-speed data communication system control unit 5 /OMbps
(1,25MB/s), the low-speed data communication system control unit 6 has 4 IMbps communication lines (15MB/s)
, the low-speed file control unit 7 has an I Mbps (α125 Mbps)
The microprocessor 1 must also perform data processing at the same time.

The data transfer latch gate 9 is connected to each peripheral control a.
It is a bidirectional buffer for adjusting the data transfer timing of part 11 and I/O bus/O, and has the configuration as shown in Figure @3.0For example, the input/output data of high-speed file control part 5 is Figure 5 (a) FIFO memo IJ as shown in K
K is stored so that data access by the high-speed file control unit 5 and data transfer to the memory 4 can be performed independently. Here, the buffering amount of the data transformer 7/aratch gate 9 is twice the amount of data corresponding to 17 memory times of the I/O bus/O to be multiplexed, thereby preventing data loss. . The peripheral control unit access controller 8 controls the access timing of the high-speed 7-isle control unit 3 and inputs and outputs data between the data transfer latch gate 9 and the high-speed file control unit 50. , the low-speed data communication system control section 6, and the low-speed file control section 7 also have similar control blocks.

Next, FIG. 4 shows the data transfer timing in this embodiment. FIG. 4 shows the relationship between the data transfer timing of each peripheral control unit and the data transfer timing of the I/O bus/O, and the data of each peripheral control unit is transferred at the above-mentioned speed. Assuming that one frame of transfer is 16 μB, in this frame time, the high-speed file control unit 3 has 64 bytes, the high-speed data communication system control unit 5 has 20 bytes, the low-speed data communication system control unit 6 has 8 bytes, and the low-speed file control unit 7 transfers 2 bytes of data. The data of each peripheral control unit (D
After storing the data in the data transfer latch gate 9 shown in FIG. 4, the data is transferred to the I/O bus/ The data in the data transfer latch gate 9 is transferred to the memory 4. If no data is stored in the data transfer latch gate 9 at the timing assigned to the frame, the CPU 1 uses that time slot.

As in this embodiment, the data of each peripheral control unit is temporarily stored in the data transfer latch gate 9, and then
- Since data is transferred to the memory 4 once per frame, the access method for the memory 4 is continuous access, which allows the use of DRAM's high-speed access modes (page mode, static column mode), and allows the memory 4 to be used as a low-cost DRAM. It can be composed of

In addition, the ts5 diagram shows the data transfer timing of the I/O bus/O when the time slot is fixed length. In this example, the time slot is fixed length of 54n8 or less (frame time/1!g data transfer amount). The time slots are arranged according to the data transfer amount of each peripheral control unit, and the frame internal pressure is averaged. The engineering/O bus/O and each peripheral control unit perform data transfer, latch, and
Data is transferred between the gate 9 and the I/O bus/O, and if no data is stored on the I/O bus/O at the time slot in question, that time slot is accessed by the microprocessor. FIG. 3(b) shows the configuration of the data transfer latch gate 9 of the above-mentioned embodiment. In this embodiment, the data transfer latch gate 9 is composed of a latch in the direction of the peripheral control section, and
The /O bus direction is configured with through gates, but may also be configured with bidirectional latches, and the circuit configuration can be simplified since the latches only need to have stages of several bytes.

In this embodiment, data transfer, latch, and
Although the gate 9 is provided, this function may be incorporated in each peripheral control section.

〔Effect of the invention〕

According to the present invention, the configuration of the I/O peripheral device control circuit is such that the peripheral control section and the I/O bus are connected to data transfer, latch,
By separating the I/O bus and the peripheral control unit with gates, it is possible to operate the I/O bus and the peripheral control unit independently.
Since the /O bus is configured to perform nine time slot multiplex transfers according to the amount of transfer, continuous data transfer is possible, and a high-speed access mode of the RAM can be used, making it possible to easily speed up data transfer. Furthermore, by allocating time slots to each peripheral control unit, the bus access timing is fixed and bus conflict determination becomes easier.

Therefore, the configuration of the machine/o peripheral device control circuit can be simplified and the cost can be reduced.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram of I/O/O peripheral device control according to an embodiment of the present invention, FIG. 2 is a block diagram of a data transfer latch gate included in FIG. 1, and FIG. 3 is a block diagram of a data transfer latch gate included in FIG. 4 is a block diagram of a conventional I/O peripheral device control circuit, FIG. 4 is a timing chart of variable time slot time division multiplexed data transfer of an I/O bus according to the present invention, and FIG. 5 is a timing chart of a fixed time slot of an I/O bus. A timing chart for dividing and multiplexing data transfer is shown. 1...Microprocessor 2...DM controller 3...High speed file control unit 4...Memory 5...High speed data communication system control unit 1 6...Low speed data communication system control unit 7... - Low-speed file control unit 8...Peripheral control unit access controller 9...Data transfer latch gate 0...I/O bus. 20th 50th 40th

Claims (1)

[Scope of Claims] 1. In a microcomputer application device in which a microprocessor and a peripheral control unit such as a file device or a communication control device are connected by a bus that shares data input/output lines and address lines, the microprocessor and the peripheral control unit Bus between classes
A transceiver latch gate, a shared bus access timing control section, and a peripheral control section timing control section are provided, and the bus access of the microprocessor and the bus access of the peripheral control section can be operated independently. I/O bus control method. 2. The control method according to claim 1, wherein time slots are set for each data transfer to the memory of the peripheral control unit and access of the microprocessor according to the amount of input/output data transfer, and the I/O bus is time-divided. An I/O bus control method characterized by the use of 3. The control method according to claim 2, wherein the I/O is configured such that the microprocessor can use the bus when input/output data is not transferred in the assigned time slot. Bus control method.