JPH03202791A - Arbitrary logic pattern generator - Google Patents

Abstract

PURPOSE:To generate various kinds of logic patterns required for many kinds of functions of a logical circuit by providing a generating circuit which is constituted of a logic pattern signal generator and generates an optional logic pattern signal. CONSTITUTION:A circuit functional data corresponding to a logic function of a desired logic pattern generator among a library is transferred from a controller 1 to a programmable logic device (PLD) of a logic pattern signal generator 3. The signal generator 3 forms a circuit having a timing generating function necessary to generate and output a desired logic pattern signal and a function to generate a logic pattern signal by the circuit functional data from the controller 1 and an oscillator 2. When a trigger signal is input owing to the logic pattern signal generating function and timing generating function of the circuit 3 from an external circuit such as an objective logical circuit 6 or the like through an input circuit 4 which converts the signal into a signal satisfying inputting conditions of the signal generator 3, the signal generator 3 generates the desired logic pattern signal.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a logic pattern generator that generates logic pattern signals necessary for operating the function of a logic circuit having a predetermined function. ,
In particular, the present invention relates to a logic pattern generator used in a testing device that tests the functions of various logic circuits that require generation of various logic pattern signals.

(Prior Art) Generally, various logic pattern generators have been devised specifically for target logic circuits. 87th
The figure shows one example of a logic pattern generator that is used in an inspection device that tests the functionality of various logic circuits.

The oscillator 51, the clock reference signal generator 52, the clock frequency setter 53, the clock generator 54, and the timing generation circuit 5 form a timing signal generator. A RAM 57 stores a logic pattern to be output to the target logic circuit 60. 56 is an address counter that generates an address for extracting a logic pattern based on data stored in the RAM 7. 50 is a microcomputer that writes logic pattern designation data into the logic pattern RAM 57 and controls the timing signal generator 55 by giving a trigger signal for starting the logic pattern generator. Reference numeral 58 denotes an output section that converts a logic pattern signal that does not occur into a signal suitable for 60 in order to provide it to the target logic circuit 60.

(Problems to be Solved by the Invention) Conventionally, target logic circuits are limited, and in many cases, the pattern generator is a dedicated pattern generator that cannot be used as a pattern generator for other logic circuits. The previous example taken up as a conventional example is also a pattern generator for various logic circuits, but it is possible to change the timing signal generation conditions in the timing signal generator, add the number of logic pattern signal outputs, and change the address counter. Changes in function or performance, such as changes in the address output procedure, require addition or modification of circuits, and cannot be easily done.

In addition, the components forming the circuit of a conventional pattern generator are standard SSI and MSI logic devices,
Since it is mainly an ASIC device, the circuit (hardware) manufactured as a predetermined pattern generator cannot be easily modified, and the component parts are standard SSI and M
The SI logic device cover turn generator has a problem in that it requires a large number of parts.

It is an object of the present invention to be able to generate various logic pattern signals required for the operation of various logic circuit functions, and to generate internal signals of the logic device used using hardware of the same circuit configuration and without modification of the hardware. The object of the present invention is to provide a null logic pattern generator that allows simple polarization of circuits to be formed.

(Means for Solving the Problems) The arbitrary logic pattern generator of the present invention stores various circuit function data of the pattern generator necessary to generate logic pattern signals corresponding to the target logic circuit, and A controller that sends the required circuit function data of the pattern generator before starting operation; an oscillator that is the basis for generating a clock signal required for timing generation in the logic pattern signal generation of the pattern generator; A circuit that generates a corresponding logic pattern signal is formed using the circuit function data sent from the controller, a logic pattern signal is generated using this formed circuit and an oscillator, and a logic pattern signal is generated by a trigger signal from the target circuit, etc. and a circuit for generating an arbitrary logic pattern signal including a logic pattern signal generator for outputting a logic pattern signal.

In a preferred embodiment of the present invention, the logic pattern signal generator is configured to include defining circuit function data such as a logic cell array (LCA), programmable array logic (PAL), etc.;
A logic pattern generator characterized in that it is mainly composed of an arbitrary logic device (PLD) and a small number of devices.

(Operation) In order to achieve the above object, the present invention, as shown in FIG. an oscillator 2 that is the basis for generating
A logic pattern signal is generated by the circuit formed by the circuit function data from the controller 1 and the oscillator 2, and the generated logic pattern signal is generated by a trigger signal obtained from the target logic circuit 76 etc. via the input circuit 4. A logic pattern generator consisting of a logic pattern signal generator 3 mainly using a programmable logic device (PLO) that enables output via an output circuit 5 is used.

By the following operations, desired logic pattern signals can be generated for various logic possibilities.

A PLD created based on an already designed logic circuit diagram or logic description representing a logic function that can be replaced by a PLD among the logic functions of various logic pattern generators.
It is assumed that the internal wiring data, that is, the circuit function data, is registered in advance in the storage means in the controller 1 as a library. Before starting the logic pattern signal generation operation, from this registered library,
Circuit function data corresponding to the logic function of a desired logic pattern generator is transferred from the controller 1 to the PLD in the logic pattern signal generator 3. Based on the transferred circuit function data, the logic pattern signal generator 3
A circuit having a desired timing generation function necessary for generating and outputting a desired logic pattern signal and a function of generating the logic pattern signal by an oscillator 2 connected to the logic pattern signal generator 3. The logic pattern signal generator 3 that forms the trigger signal ti+ is converted into a signal that satisfies the input conditions of the logic pattern signal generator 3 by the logic pattern signal generation function and timing generation function of the circuit formed inside. When an input is received from an external circuit such as a target logic circuit 6 through an input circuit 4, a desired logic pattern signal is generated and output.

The output logic pattern signal is applied to the target logic circuit 6.
The signal is output to the target logic circuit 6 through the output circuit 5 which converts it into a signal that satisfies the input conditions.

(Example) An example of the present invention will be described based on FIGS. 2 and 3. Figure 2 is a configuration diagram of an embodiment of the present invention, and Figure 3 is a PLD.
1 is an equivalent block diagram of an example circuit formed in a logic cell array (LCA) device of FIG.

In FIG. 2, the same components as those shown in FIG. 1 are denoted by the same reference numerals. A computer (μmcom) 11, a PLD (in this example, a storage unit 12 storing a library of circuit function devices for LCA, etc.), and a memory (RAMI) used to send only the circuit function devices of a desired logic pattern generator to LCA. )13,
The logic pattern signal generator 3 is composed of an LCA 31 equipped with a desired timing generation function based on the transferred circuit function data, and a memory (RAM 2) 32 equipped with a desired logic pattern signal generation function based on the transferred logic pattern signal generation data. Here is an example.

First, in this example, the L
The circuits that can be formed in the CA 31, including the circuit represented by the equivalent block diagram shown in FIG. Register on 12. In addition, in advance, the logic pattern generator of this example, that is, the logic pattern signal generation memory (RAM2) 3
The example logic pattern signal generation data shown in Table 1, which is set to 2, is created and stored in the storage unit 12.

If you need various logic pattern signal generation data,
Similarly, it is possible to store it in the storage unit 12 as a library.

Table 1 Furthermore, an operation sequence program for the logic pattern generator of this example to generate a desired logic pattern signal is also stored in the storage unit 12. Here, the following explanation of this example will proceed on the assumption that an operation sequence program for forming a circuit shown in the equivalent block diagram of FIG. 3 inside the LCA 31 is stored in the storage unit 12.

At the start of operation of the logic pattern generator in this example, the μ-coI 1111 in the controller 1 stores information in the storage unit 1.
From the circuit function data library of the timing generation function formed inside the LCA 31 in the logic pattern signal generator 3 registered in 2, the desired circuit function data, that is, the circuit of the circuit shown in the equivalent block diagram of FIG. The functional data is read and stored in the memory (RAMI) 13. Naturally, here, the operation of transferring circuit function data to the LCA 31 is prohibited. Next, already created and storage part 1
The desired logic pattern signal generation data stored in the logic pattern signal generator 3 is read out by the storage unit 12 and is stored in the logic pattern signal generation function memory (
The data is transferred to RAM2)12 and stored. Thereby, the memory (RAM2) 12 has a function of generating a desired logic pattern signal. Furthermore, the logic pattern signal generation function memory (RAM2) 12 is set to a write state. Next, the computer (μmcow) 11 has a memory (RA
M2) In order to transfer the circuit function data of the desired timing generation function from 13 to the LCA 31, send a circuit function data read permission command to the LCA 31. The LCA 31 receives this command and enters an operation sequence state in which it receives circuit function data from the memory (RAMI) 13 and forms a circuit internally based on this circuit function data, and has a desired timing generation function.

To obtain the desired timing generation functionality for this example, we
The circuit formed inside 31 will be explained with reference to the equivalent block diagram of FIG. The clock reference signal generation section 101 generates a reference signal that is the basis for generating a clock using a signal inputted by the oscillator 2 which is located outside the logic pattern signal generator 3 and is connected to the LCA 31, and outputs it to the frequency divider 102. do. The frequency divider 102 is a block frequency setting section 103
The frequency of the clock reference signal is divided based on the data set in , and a clock of the set frequency is generated. A clock of a desired frequency, which is a reference for timing signal generation, obtained by the clock generator lOO is output to the timing signal generator 104. The timing signal generator 104 receives a trigger signal trig input from outside the LCA 31.
1 and trig2 are received, trigger signal trig
A clock synchronized with 1 and 1rig2 is output to the address counter 105. Trigger signal trig 1 or tri
When the input to g2 disappears, the clock output is stopped. When the address counter 105 inputs a clock and trigger signal trig 2, it synchronizes with the clock and first sets the address data to "0" and then increments it every clock input and transfers it to the AO to At lines. Output.

When the trigger signal 1rig2 is no longer input, output of address data is stopped and address data "θ" is output.

The desired logic pattern signal generation function of the memory (RAM2) 32 in this example will be explained. The logic pattern data corresponding to the address data AO to Al input at the desired timing from the LCA 31 of the timing generation function is based on the internally stored logic pattern signal generation data as shown in the data example in Table 1. hand,
In synchronization with the timing of input address data Ao-Al, signals PD1 . P.D.
2. ..., is output from DO1 to Don as PDn.

In this way, the logic pattern signal generator 3 becomes capable of generating and outputting a desired logic pattern signal using the desired timing generation function and logic pattern signal generation function formed inside.

Next, the operation of generating a desired logic pattern signal will be explained. Computer (μmcom) 1 in controller 1
1 to the logic pattern signal generator 3, that is, the timing generation function LCA 31, as a command to start the generation operation.
Outputs trigger signal trig2.

The logic generator in this example is in a desired logic pattern signal generation state. From the target logic circuit 6, via the input circuit 4 that converts it into a signal that satisfies the input conditions of the logic pattern signal generator 3, that is, the internal LCA 31,
When the trigger signal trig 1 is input to the logic pattern signal generator 3, the logic pattern signal generator 3 generates desired logic pattern signals PDI to PDI by the timing generation and logic pattern signal generation functions described above.
The logic pattern signals PDI to PDn are outputted to the target logic circuit 6 through an output circuit 5 which generates the signal Dn and converts the signal into a signal that satisfies the input conditions of the target logic circuit 6.

The computer (μcom) 11 of the controller 1 receives the trigger signal trig2, or the target logic circuit 6 receives the signal t.
When the output of rig 1 is stopped, the logic pattern signal generator 6 stops generating and outputting the logic pattern signals PDI to PDn.

In the logic pattern generator of this example, when changing the desired logic pattern signal to be generated, the timing generation function can be changed using the computer (μmC0III 11 is a timing generation function that changes the selection identification data used in the operation of selecting required circuit function data from the circuit function data library of the timing generation function registered in the storage unit 12. This is possible by modifying the data that points to the circuit function digital-to-analog converter.For changes related to logic pattern signal generation, modify the logic pattern signal generation data that has been created in advance and stored in the storage unit 12, and then store it again in the storage unit 12. This can be done by re-storing the data, or if the library of logic pattern signal generation data has already been registered in the storage unit 12, it can be done by making the same modification as change 7 regarding the timing generation function.

By modifying some of the data stored in the storage unit 12 in this way, the desired logic pattern signal to be generated can be changed very easily.

Furthermore, in this example, the basic configuration of the logic pattern signal generator 3 can be easily made with two devices, LCA and RAM. In the above description of this example, the logic pattern signal generation memory (RAM2) 32 in the logic pattern signal generator 3 is an input/output separated type RAM, but the present invention is of course not limited to this. , even if the input/output is common to RAM, a circuit for latching and outputting the generated logic pattern signal is configured in addition to the circuit for the type generation function in LCA31, and the memory (RAM2) 3
It goes without saying that the output of 2 is once input to the LCA 31, passed through this circuit, and then the logic pattern signal is output from the LCA 31.

(Second Embodiment) A first embodiment of the present invention will be described based on FIG. 4. Fourth
The figure is a configuration diagram of an embodiment of the present invention.

In FIG. 4, the same reference numerals as in FIGS. 1 and 2 indicate the same parts, and in this example, the timing generation of the logic pattern signal generator 3 in the first embodiment is explained. In contrast to the PLD that is configured using LCA as a PLD equipped with functions, it is configured using multiple programmable array logic (PLD).
AL) type electrically erasable PLD (GAL, PEE
In this example, the controller 1 is configured using a PLD that sends circuit function data to each PLD instead of the memory (RAMI) 13 for sending out circuit function data, in contrast to the first embodiment. The logic pattern signal generator 3 is an LCA that has a desired timing generation function based on the transferred circuit function data.
31, the clock reference signal generating section 10 of the clock generating section 100 is used instead of the internally formed circuit shown in FIG.
1 in the clock reference signal generation circuit 41
The circuit function to which the timing signal generation unit 104 is transferred is in the clock generation unit 40, which is composed of a clock generation PLD (1) 42 and a clock generation PLD (2) 43, which are provided with a clock generation function by the circuit function data to which the timing signal generation unit 104 is transferred. The timing signal generation PLD 44 has a timing signal generation function based on data, and the address counter 105 is configured with an address counter PLD(1) 46 and an address counter PLD(2) 47, which has an address counter function based on the circuit function data transferred. An example configured with an address counter 45 is shown.

This example is substantially the same as the first embodiment except for the explanation of the operation described later, so the explanation thereof will be omitted.

In this example, the method of registering the PLD circuit function data of the soil timing generation function as a library in the storage unit 12 in the controller 1 in advance is as in the first embodiment.
- Each PLD424 in the block that performs the timing generation function in the logic pattern signal generator 3, excluding the clock reference signal generation function, without registering the integrated timing generation function data.
4.46.47 is divided into each function in charge, and the circuit function data for each function is registered as a library of circuit function data of the timing generation function.

In this example, (μmcom) 11 in controller 1
However, the method of transferring circuit function data of a desired timing generation function to a PLD equipped with a timing generation function in the logic pattern signal generator 3 is to Transfers all the circuit function data for the functions performed by the PLD writer 14 to the PLD writer 14, and simultaneously puts all the PLDs 42 to 44, 46, and 47 that perform the timing generation function in the logic pattern signal generator 3 into a circuit function data reading state. 14 to each PLD 42 to 44, 46, 47, one by one, each PL for the desired timing generation function.
Write only the circuit function data for the function performed by D,
Each PLD 42 to 44, 46, and 47 is brought into operation. Each of the PLDs 42 to 44, 46, and 47 receives and receives circuit function data.
．． 47 is formed internally.

In this example, when changing the desired logic pattern signal to be generated due to a partial function of the timing generation function, the timing generation function is stored in the storage section 12 in the controller 1 in each PLD in the logic pattern signal generator 3.
Divide into each PL by function performed by 42-44, 46, and 47.
It is registered as a library of circuit function data corresponding to D44 to 44.46.47, and usually each PLD4.
2 to 44, 46, and 47, the identification data for circuit function data selection in the operation sequence program stored in the storage unit 12 is changed. One PLO to do
This is possible by modifying the data to point to the corresponding circuit function data of the function corresponding to the function, but if there is no corresponding circuit function data in the circuit function data library registered in the storage unit 12, and you have to create a new one. If this is not possible, it is possible by modifying or creating a new circuit function data only for a function corresponding to one PLO with a timing generation function.

In this way, the logic pattern generator of this example can extremely easily change the logic pattern signal generated due to the timing generation function by simply modifying only a part of the constituent circuit or the data used in this circuit. It can be carried out.

(Third example) One embodiment of the present invention will be described based on FIG.

FIG. 5 is a block diagram of one embodiment of the present invention.

In FIG. 5, the same parts as those shown in FIGS. 1 and 2 are designated by the same reference numerals. In this example, in the first embodiment, the logic pattern signal generator 3 is configured with the LCA 31 equipped with a timing generation function and the memory (RAM2) 32 equipped with a logic pattern signal generation function, whereas the logic pattern signal generator 3 is configured with a timing generation function and a logic pattern signal generation function. An example in which only LCA devices are used as a device with a signal generation function, that is, logic pattern signal generator 3
An example is shown in which a logic pattern signal generation LCA 33 is used instead.

The operation of this embodiment is substantially the same as that described for the first embodiment, except for the explanation of the operation described later, so the explanation thereof will be omitted.

In this example, the library of PLD circuit function data registered in advance in the storage unit 12 in the controller 1 is a logic pattern signal including a timing generation function and a logic pattern signal generation function formed inside the logic pattern signal generation LCA 33 of this example. It is about various circuits of generation function. Therefore, there is no need to create logic pattern signal generation data for the logic pattern signal generation function memory (RAM2) 32 and store it in the storage unit 12.
Naturally, the logic pattern signal generation function memory (RAM2
)32. Regarding the logic pattern signal generation LCA 33 of this example, the operation of an example of a circuit formed inside to obtain a desired logic pattern signal generation function will be described with reference to an equivalent block diagram shown inside the logic pattern signal generation LCA 33 in FIG.

The circuit formed inside the LCA 33, which is a part of the timing generation function, and the circuit from the clock generation section 100 to the timing signal generation section 104 was explained using the equivalent block diagram of FIG. 3 in the explanation of the first embodiment. Same as operation. Here, it is assumed that one bit corresponds to the pulse period of the clock signal that is the reference for the timing signal CP used to generate the desired logic pattern signal, and the desired logic pattern signal is output in a period of the total number of bits P. . The timing signal CP output from the timing signal generation section 104 is sent to the timing bit generation divider 106.
When input to
Pulse output timing signal j1. t2+j3゜~+t
timing bit generation divider 106
The signal is output from the pattern output matrix switch 07. Here, the number of output channels of the desired logic pattern signal is assumed to be n. The bit unit pattern setting unit 108 includes a setting unit T1. 〜＋T
The pattern data of the desired logic pattern signal for the number n of output channels of the bone logic pattern signal during each corresponding bit is set in the setting section, and the pattern data is divided for each output channel. ,
For example, in the case of the setting part T1 of bit 1 in the first 1-bit period, T, , T2 . , . . .+T n l signals and output to the pattern output matrix switch 107. The bits and pattern data explained here are the first bits and pattern data used in the explanation in the first embodiment.
This corresponds to the logic pattern signal output step and logic pattern data in the table. The pattern output matrix switch 107 receives the input timing signal t of each bit.
, (y=1.2..., p) and each output channel pattern signal T, y (x=1.2..., n) of each bit.
Therefore, T xy times signal 1. Signal S synchronized with the signal
zy is obtained, and the signals Sxl to Sxp, which have a total of 9 bits for each channel, are summed and synthesized in time series to generate a desired logic pattern signal PD for each output channel.
, (PDI~PDn) are generated on the lines PD,~PD. The logic pattern signal generation LcA 33 is equipped with a timing generation function and a logic pattern signal generation function, that is, a logic pattern signal generation function. In response to the trigger signals trigl and trig2 from the controller 1, desired logic pattern signals PD, -PD are output.

In this example, when changing the desired logic pattern signal to be generated, it is possible to make the same modification as the change regarding the timing generation function in the first embodiment.

In this way, the logic pattern generator of this example has at least one logic pattern signal generator 3 in the example.
It can be easily manufactured by being composed of several LCA devices, and the desired logic pattern signal to be generated can be easily changed by modifying one data.

In this example, the number of output channels of the desired logic pattern signal to be generated and the output per channel (
If it is desired to increase the number of bits, this can be easily done by increasing the number of logic pattern signal generation LCA 33 points.

(Fourth Embodiment) A fourth embodiment of the present invention will be described based on FIG. 7. 7th
FIG. 4 is a configuration diagram of one embodiment of the present invention, and FIG. 7(a)
is for the first embodiment, and FIG. 7(b) is for the second embodiment.
This is for the embodiment, and FIG. 7(C) is for the third embodiment.

In FIG. 7, the same parts as those shown in FIGS. 1 to 5 are designated by the same reference numerals. In this example, the logic pattern signal generator 3 is configured with a FROM (1) 15 that stores circuit function data for generating a desired logic pattern signal of the timing generation function LCA 31 instead of the controller 1 in the first embodiment. An example configured with logic pattern signal generation function memory (RAM2) 34 (
FIG. 7(a)), an example of the configuration in which the controller 1 is omitted in the second embodiment (FIG. 7(b)), and the third embodiment shown in FIG.
P that stores circuit function data of the logic pattern signal generation LCA 33 instead of the controller 1 in the embodiment
This is an example (FIG. 7(C)) configured with ROM(1) 15.

In this example, the controller 1 performs the function of easily changing the desired logic/turn signal to be generated and easily responding to the generation of any desired logic/turn signal.
This is an example of a nearly specialized logic/socket turn generator that can be used in applications where there is no problem even if the desired logic/socket pattern signal generated by omitting is limited to one type.

In this example, as a first step necessary to generate one desired type of logical/sonic turn signal, in the example of FIG. 7(a), the circuit of the timing generation function LCA31 is FROM function data (1)
15, convert the logic turn signal generation data to FR.
OM (2) Write to 34, and in the example of FIG. 7(b), write to PL.
The circuit function data is written to PLD42 to 44, 46, and 47 of each electrically erasable PROM type that performs a timing generation function using a D writer, etc. In the example of FIG. 7(C), the PROM
The circuit function data of the logic pattern signal generation LCA 33 is written and stored using a writer or the like.

LCA is FROM that is automatically connected when the power is turned on.
A FROM or electrically erasable PROM type PLD has a function of reading circuit function data from a ROM and forming a circuit based on the circuit function data internally, and if data or circuit function data is already stored inside, A function or circuit is formed based on the data or circuit function data. Therefore, in this example, a desired logic pattern signal generation function is provided during the operation of generating logic pattern signals.

Regarding the operation of generating the logic pattern signal in this example, the examples in FIGS. 7(a), (b), and (c) are the same as those in the first embodiment, the second embodiment, and the third embodiment. Therefore, its explanation will be omitted.

In this example, when changing the desired logic pattern signal to be generated, use the PROM writer or PLD writer to select PROM (1) 15, FROM (2) 34 or PL
This can be achieved by erasing all the previous data stored in the circuit function data or data of the corresponding functions D42 to D44, 46, and 47, and rewriting the data to write new desired data.

The logic pattern generator in this example can be easily manufactured and provided as a dedicated logic pattern generator with a small number of parts that generates one type of desired logic pattern signal, and can be easily incorporated into the target logic circuit. can be incorporated into

(Effects of the Invention) According to the present invention, it is possible to easily provide all necessary logic pattern signals to various target logic circuits with the same configuration.

Furthermore, since the logic pattern generator can be easily configured with a small number of parts, manufacturing, debugging, and modification can be easily performed, and the development period for a newly manufactured logic pattern generator can be shortened.

Furthermore, since the main device configuring it is a PLD,
You can freely create internal circuits, and logic pattern generators created in the past can be stored as a library of circuit function data, which can be used for future applications.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing the principle configuration of an arbitrary logic pattern generator of the present invention, FIGS. 2 to 5 are block circuit diagrams showing preferred embodiments of the logic pattern generator of the present invention, and FIG. 6 is a bit unit Waveform diagrams showing timing signals of different pulse outputs; FIGS. 7(a) to 7(c) are block diagrams showing various modifications of the logic pattern generator of the present invention; FIG. 8 is a general logic pattern. FIG. 2 is a block circuit diagram showing the configuration of a generator. Target logic circuit computer storage unit AM PLD writer CA AM

Claims (1)

[Claims] 1. Various circuit function data of the pattern generator required to generate a logic pattern signal corresponding to the target logic circuit are stored, and before starting the operation of generating the logic pattern signal, A controller that sends circuit function data of the pattern generator to be generated, an oscillator that is the base for generating the clock signal required for timing generation in the logic pattern signal generation of the pattern generator, and circuit function data that is sent from the controller. A logic circuit that forms a circuit that generates a corresponding logic pattern signal, generates a logic pattern signal using this formed circuit and an oscillator, and outputs the generated logic pattern signal in response to a trigger signal from a target circuit, etc. 1. An arbitrary logic pattern generator comprising a circuit for generating an arbitrary logic pattern signal composed of a pattern signal generator. 2. In claim 1, the logic pattern signal generator is capable of forming an arbitrary logic circuit using defined circuit function data such as a logic cell array (LCA), programmable array logic (PAL), etc. An arbitrary logic pattern generator characterized in that it is mainly composed of a small number of possible programmable logic devices (PLDs).