JPH03201592A - Manufacture of printed circuit board - Google Patents

Manufacture of printed circuit board

Info

Publication number
JPH03201592A
JPH03201592A JP34271589A JP34271589A JPH03201592A JP H03201592 A JPH03201592 A JP H03201592A JP 34271589 A JP34271589 A JP 34271589A JP 34271589 A JP34271589 A JP 34271589A JP H03201592 A JPH03201592 A JP H03201592A
Authority
JP
Japan
Prior art keywords
hole
catalyst
circuit
electroless plating
metal foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34271589A
Other languages
Japanese (ja)
Inventor
Kazuyuki Tazawa
田沢 和幸
Atsuhiro Haneda
羽田 篤弘
Katsuhiro Nemoto
根本 克宏
Takashi Nakamura
孝 中村
Seiji Honma
本間 政治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Lincstech Circuit Co Ltd
Original Assignee
Hitachi AIC Inc
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi AIC Inc, Hitachi Chemical Co Ltd filed Critical Hitachi AIC Inc
Priority to JP34271589A priority Critical patent/JPH03201592A/en
Publication of JPH03201592A publication Critical patent/JPH03201592A/en
Pending legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To simply obtain a printed circuit board having excellent productivity by forming a through hole, then making plating catalyst adhere to the entire surface, and then removing the catalyst of the surface layer by physical polishing. CONSTITUTION:A hole 4 to become a through hole is opened at a metal foil- plated laminated board adhered with a metal foil 1 through an insulating board 2. The board is dipped in solution containing electroless plating catalyst 5 to apply the catalyst 5 to the entire surface including the hole. In order to remove the catalyst 5 adhered to the position except the inner wall of the hole 4, the surface of the foil 1 is polished. The inner wall of the hole 4 to become a through hole is protected, an etching resist 6 for protecting the foil 1 of the part to become a circuit is formed, the foil 1 of the part not becoming a circuit is removed by etching, and the resist 6 is removed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、2層以上の回路層を有するプリント配線板の
製造法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a printed wiring board having two or more circuit layers.

(従来の技術〕 プリント配線板の製造法は、銅張り積層板の銅箔の不要
な箇所をエツチング除去して製造するサブトラクト法、
必要な箇所に無電解めっきによって回路導体を絶縁基板
上に形成するアデティブ法、部分的に無電解めっきを用
いて導体を形成する部分アデティブ法が知られており、
2層以上の回路導体層を有するプリント配線板を製造す
るときに、異なる導体層間を接続するスルーホールを金
属化するために、無電解めっきによる方法も知られてい
る。〜 このような製造法であって、スルーホールの内壁を金属
化する方法として、特開昭61−252689号公報に
開示されているように、絶縁基板にレジストを全面に形
成した後に、スルーホールとなる穴をあけ、無電解めっ
き用触媒を穴内を含む全表面に付着させ、レジストを剥
離して、スルーホールとなる穴内のみに触媒を残す方法
、特開昭52−116866号公報に開示されているよ
うに、疎水性を有する永久ソルダーレジストを絶縁基板
上の回路とならない部分に形成し、無電解めっきの不要
なレジスト表面上に触媒を付着させない方法、特開昭5
9400596号公報に開示されているように、銅張り
積層板にスルーホールとなる穴をあけ、銅張り積層板の
銅箔の不要な箇所をエツチング除去して回路を形成し、
その穴内部を含む全表面に無電解めっき用触媒を付着さ
せた後、穴部以外の触媒を薬品によって除去する方法、
特開昭60−187094号公報に開示されているよう
に、鋼張り積層板にスルーホールとなる穴をあけ、銅張
り積層板のw4箔の不要な箇所をエツチング除去して回
路を形成し、スルーホール穴内壁面にのみ導電性の樹脂
を塗布する方法、または、特開昭61−2386号公報
に開示されているように、スルーホールが形成された銅
張り積層板全体に無電解めっき用触媒を付着させた後、
銅張り積層板の銅箔の不要な箇所をエツチング除去して
回路を形成するとともに、エツチング除去する部分に付
着した触媒を除去する方法等が知られている。
(Prior art) Printed wiring boards are manufactured using the subtract method, which involves removing unnecessary parts of the copper foil from a copper-clad laminate by etching;
The additive method, in which circuit conductors are formed on an insulating substrate by electroless plating at the required locations, and the partial additive method, in which conductors are partially formed using electroless plating, are known.
When manufacturing a printed wiring board having two or more circuit conductor layers, a method using electroless plating is also known for metallizing through holes connecting different conductor layers. ~ As a method of metallizing the inner wall of a through hole in such a manufacturing method, as disclosed in Japanese Patent Application Laid-open No. 61-252689, a resist is formed on the entire surface of an insulating substrate, and then a through hole is formed. A method is disclosed in JP-A-52-116866, in which a hole is made, a catalyst for electroless plating is attached to the entire surface including the inside of the hole, and the resist is peeled off, leaving the catalyst only in the hole that will become a through hole. As shown in Japanese Patent Laid-open No. 5, a method of forming a permanent solder resist with hydrophobicity on a portion of an insulating substrate that does not form a circuit, and preventing a catalyst from adhering to the resist surface where electroless plating is not necessary.
As disclosed in Japanese Patent No. 9400596, a circuit is formed by drilling holes to serve as through holes in a copper-clad laminate and etching away unnecessary portions of the copper foil on the copper-clad laminate.
A method of attaching an electroless plating catalyst to the entire surface including the inside of the hole, and then removing the catalyst other than the hole with a chemical;
As disclosed in Japanese Unexamined Patent Publication No. 60-187094, a circuit is formed by drilling holes to serve as through holes in a steel-clad laminate and etching away unnecessary parts of the W4 foil of the copper-clad laminate. There is a method of applying a conductive resin only to the inner wall surface of the through-hole, or a method of applying a catalyst for electroless plating to the entire copper-clad laminate in which through-holes are formed, as disclosed in JP-A No. 61-2386. After attaching the
A method is known in which a circuit is formed by etching unnecessary parts of the copper foil of a copper-clad laminate, and at the same time, a catalyst adhering to the parts to be etched is removed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の方法における問題点を以下に説明する。 Problems with the conventional method will be explained below.

前記第一のレジストによってスルーホール内のみに無電
解めっき用触媒を付与する方法は、そのレジストを形成
する工程が増加し、煩雑になることと、穴内部のみにし
か触媒を付与できず、回路導体の一部を厚くすることが
できない。
The method of applying the electroless plating catalyst only to the inside of the through-hole using the first resist increases the number of steps to form the resist, making it more complicated. Part of the conductor cannot be made thicker.

前記第二の疎水性を有する永久ソルダーレジストを使用
する方法は、ぬれ性の高い無電解めっき用触媒を復溶液
は、そのソルダーレジスト表面に発生した前工程でのす
り傷等のわずかなくぼみに、無電解めっきによる金属が
析出し、不要な回路を形成することがある。
In the second method of using a permanent solder resist having hydrophobic properties, a highly wettable electroless plating catalyst is applied to the reconstituted solution into slight depressions such as scratches generated in the previous process on the surface of the solder resist. , metal deposited by electroless plating may form unnecessary circuits.

前記第三のスルーホールと回路形成後に触媒を付着させ
る方法は、その後の研磨や薬品処理を行っても、回路導
体のない部分の絶縁基板や接着剤表面に付着した触媒の
残さを完全に取り去ることが困難であるため、その残さ
による絶縁劣化が発生し信頼性が低下する。
The method of attaching the catalyst to the third through-hole and after the circuit is formed completely removes any catalyst residue attached to the insulating substrate or adhesive surface in areas where there is no circuit conductor, even after subsequent polishing or chemical treatment. Since it is difficult to do so, insulation deterioration due to the residue occurs and reliability decreases.

前記第四の穴壁のみに導電樹脂を塗布する方法は、穴壁
に確実に塗布することが難かしく、塗布という煩雑さと
、導電樹脂の導電率を金属と同等の程度にすることが困
難であるため接続の信頼性が低い。
The method of applying conductive resin only to the fourth hole wall is difficult to reliably apply to the hole wall, is complicated to apply, and is difficult to make the conductivity of the conductive resin equivalent to that of metal. This makes the connection unreliable.

前記第五の触媒を不要な導体とともに除去する方法は、
触媒が回路パターン間に残らないため、絶縁劣化の原因
にならず、工程も簡便であるが、必要な回路となる銅表
面に触媒が付着しているため、回路形成を行うためのエ
ツチングレジストと銅箔との密着性が低下し、エツチン
グ精度が低下し、また、最後の仕上げに用いるソルダー
レジストと回路銅箔との密着性も低下するので、剥がれ
易い。
The method for removing the fifth catalyst together with unnecessary conductors is as follows:
Since the catalyst does not remain between the circuit patterns, it does not cause insulation deterioration and the process is simple. However, since the catalyst is attached to the copper surface that forms the necessary circuit, it is difficult to use etching resist for forming the circuit. Adhesion with the copper foil decreases, etching accuracy decreases, and adhesion between the solder resist used for final finishing and the circuit copper foil also decreases, making it easy to peel off.

本発明は、このような問題点を解消し、簡便で量産性に
優れるプリント配線板の製造方法を提供するものである
The present invention solves these problems and provides a method for manufacturing printed wiring boards that is simple and has excellent mass productivity.

[課題を解決するための手段] 本発明の製造法は、第1図(a)〜(g)に示すように
、以下の工程からなることを特徴とする。
[Means for Solving the Problems] The manufacturing method of the present invention is characterized by comprising the following steps, as shown in FIGS. 1(a) to (g).

A、絶縁基板2に金属箔1を貼り合わせた金属箔張り積
層板にスルーホールとなる穴4をあける工程(第1図(
a)に示す。)。
A. Step of drilling a hole 4 to serve as a through hole in a metal foil-clad laminate in which a metal foil 1 is bonded to an insulating substrate 2 (see Fig. 1).
Shown in a). ).

B、前記積層板を無電解めっき用触媒5を含む溶液に浸
漬し、無電解めっき用触媒5を穴内部を含む全表面に付
与する工程(第1図(b)に示す。)。
B. Step of immersing the laminate in a solution containing the electroless plating catalyst 5 and applying the electroless plating catalyst 5 to the entire surface including the inside of the hole (as shown in FIG. 1(b)).

C1前記スルーホールとなる穴4の内壁以外の箇所に付
着した無電解めっき用触媒5を除去するために、金属箔
1の表面を研磨する工程(第1図(C)に示す、)。
C1 A step of polishing the surface of the metal foil 1 in order to remove the electroless plating catalyst 5 attached to a portion other than the inner wall of the hole 4 that will become the through hole (as shown in FIG. 1(C)).

D、前記スルーホールとなる穴4の内壁を保護し、回路
となる部分の金属箔1を保護するエツチングレジスト6
を形成しく第1図(d)に示す、)、回路とならない部
分の金属箔1をエツチング除去し、エツチングレジスト
6を除去する工程(第1図(e)に示す。)。
D. Etching resist 6 that protects the inner wall of the hole 4 that will become the through hole and protects the metal foil 1 that will become the circuit.
(shown in FIG. 1(d)), the step of etching away the portions of the metal foil 1 that will not form a circuit, and removing the etching resist 6 (shown in FIG. 1(e)).

E、無電解めっき液に耐えることができ、永久に残るソ
ルダーレジスト7を、スルーホールとなる穴4の周囲お
よび回路として厚さの必要な箇所もしくは位置合わせ精
度の確保が必要な箇所を除いて形成する工程(第1図(
f)に示す。
E. Apply solder resist 7 that can withstand electroless plating solution and remains permanently, except around the holes 4 that will serve as through holes and in areas where thickness is required for circuits or where alignment accuracy is required. Forming process (Fig. 1 (
Shown in f).

)。).

F、前記ソルダーレジスト7から露出する導体上にのみ
無電解めっきを行いスルーホール内および回路として厚
さの必要な箇所もしくは位置合わせ精度の確保が必要な
箇所にめっき金属8を析出させる工程(第1図(g)に
示す、)。
F. A step of electroless plating only on the conductor exposed from the solder resist 7 and depositing the plating metal 8 in the through holes and in the places where thickness is required for the circuit or where it is necessary to ensure alignment accuracy (step (shown in Figure 1 (g)).

本発明の工程に用いるものは、すべて従来のプリント配
線板に使用していたものが使用できる。
All materials used in the process of the present invention can be those used in conventional printed wiring boards.

すなわち、工程Aの絶縁基板2には、ガラス布−エポキ
シ樹脂、ガラス短繊維含有エポキシ樹脂、祇−エポキシ
樹脂、または紙−フェノール樹脂等のいわゆるリジッド
板と呼ばれる基板や、ポリイミドフィルム、ポリエステ
ルフィルム、ポリエチレンフィルム、ポリテトラフロオ
ロエチレンフィルム等の可続性の基板が使用でき、金属
M1としては、銅箔、アルミニウム箔、その他が使用で
き、穴あけは、ドリル、金型、等を用いることができる
That is, the insulating substrate 2 in step A includes a so-called rigid board such as a glass cloth-epoxy resin, an epoxy resin containing short glass fibers, a paper-epoxy resin, or a paper-phenol resin, a polyimide film, a polyester film, A flexible substrate such as a polyethylene film or a polytetrafluoroethylene film can be used, and as the metal M1, copper foil, aluminum foil, or the like can be used. For drilling, a drill, a mold, etc. can be used. .

工程Bの無電解めっき用触媒5としては、パラジウム、
金、白金、銅、およびこれらの塩からなる群から選択し
たものを使用でき、また、これらの群から選択したもの
を組み合わせたものを用いることもできる。
The electroless plating catalyst 5 in step B includes palladium,
Materials selected from the group consisting of gold, platinum, copper, and salts thereof can be used, and combinations of materials selected from these groups can also be used.

工程Cのスルーホールとなる穴4の内壁以外の箇所に付
着した無電解めっき用触媒5を除去するために、金属箔
1の表面を研磨する方法としては、ブラシや紙やすり等
を手作業によって行うこともできるが、回転式のブラシ
等を用いる方が、工程の時間短縮や作業の均一化のため
に好ましい。
In order to remove the electroless plating catalyst 5 that has adhered to areas other than the inner wall of the hole 4 that will become the through hole in step C, the surface of the metal foil 1 can be polished manually using a brush, sandpaper, etc. Although this can be done, it is preferable to use a rotary brush or the like in order to shorten the process time and make the work more uniform.

工程りのスルーホールとなる穴4の内壁を保護し、回路
となる部分の金属箔lを保護するエツチングレジスト6
としては、通常に用いられるエツチングレジスト用イン
クや光硬化型エツチングレジストフィルムとして市販さ
れているものであればどのようなものでも使用でき、そ
れぞれ、シルクスクリーン印刷法や硬化させる部分に光
が透過するネガフィルムを用いて行う焼付法によって、
所望の形状にエツチングレジスト6を形成することがで
き、化学的に特定の金属を溶解できるものたとえば、銅
ならば塩化第二銅や塩化第二鉄等を水溶液とし、シャワ
ー状に噴霧して、回路とならない部分の金i箔1をエツ
チング除去することができ、エツチングレジスト6を除
去する方法としては、前記エツチングレジストインクを
溶解するものや、フィルム状のエツチングレジストを溶
解もしくは分解除去するものならばどのようなものでも
使用できる。
Etching resist 6 that protects the inner wall of hole 4, which will be a through hole in the process, and protects the metal foil l of the part that will become a circuit.
Any commonly used etching resist ink or photo-curable etching resist film that is commercially available can be used as the etching resist film. By the printing method using negative film,
The etching resist 6 can be formed into a desired shape and can chemically dissolve a specific metal. For example, in the case of copper, an aqueous solution of cupric chloride or ferric chloride is sprayed in a shower. The portions of the gold i-foil 1 that do not form a circuit can be removed by etching, and the etching resist 6 can be removed by dissolving the etching resist ink or by dissolving or decomposing the etching resist in the form of a film. You can use anything.

工程Eの無電解めっき液に耐えることができ、永久に残
るソルダーレジストマとしては、硬化した状態で無電解
めっき液に侵されないものであればどのようなものでも
使用でき、これも前記エツチングレジストと同様の方法
によって形成することができる。
As the solder resist that can withstand the electroless plating solution in step E and remains permanently, any material can be used as long as it is not attacked by the electroless plating solution in a hardened state, and this is also the same as the etching resist mentioned above. It can be formed by a method similar to that of .

工程Fの無電解めっきとしては、析出させる金属によっ
てそれぞれ従来用いられていたものならばどのようなも
のでも使用できる。
As the electroless plating in step F, any conventional plating can be used depending on the metal to be deposited.

また、金属8を析出させる形状が、プリント配線板とし
たときに電気的接続をプリント配線板の外に一括してで
きるようなものである場合には、この無電解めっきに代
えて、電解めっきを用いることもできる。
In addition, if the shape in which the metal 8 is deposited is such that when it is made into a printed wiring board, electrical connections can be made all at once outside the printed wiring board, electrolytic plating may be used instead of electroless plating. You can also use

このめっき金属は銅が望ましいが、Ni、Au等の最低
限、導電性を有するものであっても良い。
This plating metal is preferably copper, but it may also be a metal that has at least electrical conductivity, such as Ni or Au.

〔作用) めっき触媒は、プリント配線板のスルーホール以外に付
着すると、絶縁劣化や回路形威用エッチングレジストお
よびソルダーレジストの密着性低下の原因となるが、本
発明はスルーホール形成後、全面にめっき触媒を付着さ
せ、次いで表層のめっき触媒を物理的研磨で除去する製
法であり、回路が形成されていないため表面が平滑であ
ることから、容易に触媒を除去することができる。
[Function] If the plating catalyst adheres to areas other than the through-holes of a printed wiring board, it will cause insulation deterioration and a decrease in the adhesion of etching resists and solder resists used for circuit shapes. This is a manufacturing method in which a plating catalyst is attached and then the surface layer of the plating catalyst is removed by physical polishing.Since there are no circuits formed and the surface is smooth, the catalyst can be easily removed.

また、研磨に用いるブラシが多少スルーホール内に侵入
し、スルーホール内部の一部の触媒が除去されても、ブ
ラシの毛先が届く範囲のスルーホール内部は、金属箔に
近く、本来触媒を必要とする箇所は、スルーホールの内
部に位置する絶縁層部分のみ5だからである。
In addition, even if the brush used for polishing penetrates into the through-hole to some extent and some of the catalyst inside the through-hole is removed, the inside of the through-hole within the reach of the brush bristles is close to the metal foil and does not originally contain catalyst. This is because the only required portion is the insulating layer portion 5 located inside the through hole.

実施例1 絶縁基板に、両面銅張り積層板であるMCL−[−67
N (日立化成工業株式会社製、商品名)厚さ1.6開
を用い、パンチング法にてスルーホールとなる穴あけを
行い、無電解銅めっき用触媒を含む溶液であるCUST
201 (日立化威工業株式会社。
Example 1 MCL-[-67, which is a double-sided copper-clad laminate, was mounted on an insulating substrate.
Using N (manufactured by Hitachi Chemical Co., Ltd., trade name) with a thickness of 1.6 mm, holes were made to become through holes using the punching method, and CUST, a solution containing a catalyst for electroless copper plating, was prepared.
201 (Hitachi Chemical Industries, Ltd.)

商品名)に浸漬し、乾燥した後、回転式ナイロンブラシ
を用いた研磨機によって銅はく表面のめりき触媒を除去
した。
After drying, the plated catalyst on the surface of the copper foil was removed using a polisher using a rotating nylon brush.

次いで、エツチングレジストとして、紫外線感光型フィ
ルムであるフォテック887AP−25(日立化或工業
株式会社製、商品名)をラミネートし、回路バクーンの
焼付、現像後、塩化第二銅によるエツチングを行い、約
3%の炭酸ナトリウム溶液によってエツチングレジスト
の除去を行い回路パターンを形成した。
Next, as an etching resist, an ultraviolet-sensitive film Photec 887AP-25 (manufactured by Hitachi Chemical Co., Ltd., trade name) was laminated, and after baking and development of a circuit board, etching was performed with cupric chloride. The etching resist was removed using a 3% sodium carbonate solution to form a circuit pattern.

次いで、無電解めっき用のソルダーレジストとして紫外
線感光型フィルムであるフォテック5R−3000−2
2(日立化威工業株式会社製、商品名)を真空ラミネー
タを用いてラミネートし、焼付、現像、アフターキュア
を行い、ソルダーレジストを形成した。
Next, Photek 5R-3000-2, an ultraviolet-sensitive film, was used as a solder resist for electroless plating.
2 (manufactured by Hitachi Kaei Kogyo Co., Ltd., trade name) using a vacuum laminator, baking, development, and after-curing were performed to form a solder resist.

次いで、硫酸銅、ホルムアルデヒド、錯化剤、苛性ソー
ダおよびシアン化ソーダ等からなる無電解銅めっき液で
あるCC−4めっき液(日立化成工業株式会社、商品名
)に9時間浸漬し、厚さ18μmのめっき銅を析出させ
た。
Next, it was immersed for 9 hours in CC-4 plating solution (trade name, Hitachi Chemical Co., Ltd.), which is an electroless copper plating solution consisting of copper sulfate, formaldehyde, a complexing agent, caustic soda, soda cyanide, etc., to a thickness of 18 μm. Plated copper was deposited.

実施例2 フレキシブル用として開発されたポリイミドフィルムを
基材とする両面銅張り積層板F−30νC225RC2
1にッカン工業株式会社製、商品名)を用い、NC制御
のドリルマシンでスルーホールとなる穴あけを行い、無
電解銅めっき用触媒を含む溶液であるCUST201 
(日立化威工業株式会社。
Example 2 Double-sided copper-clad laminate F-30νC225RC2 based on polyimide film developed for flexible use
1. Using CUST201, a solution containing a catalyst for electroless copper plating, a through-hole was drilled using an NC-controlled drill machine using CUST201, a solution containing a catalyst for electroless copper plating.
(Hitachi Chemical Industries, Ltd.

商品名)に浸漬し、乾燥した後、回転式ナイロンブラシ
を用いた研磨機によって銅はく表面のめっき触媒を除去
した。
After drying, the plating catalyst on the surface of the copper foil was removed by a polisher using a rotating nylon brush.

次いで、エツチングレジストとして、紫外線感光型フィ
ルムであるフオテック887AF−25(日立化戒工業
株式会社製、商品名)をラミネートし、回路パターンの
焼付、現像後、塩化第二銅によるエツチングを行い、約
3%の炭酸ナトリウム溶液によってエツチングレジスト
の除去を行い回路パターンを形成した。
Next, as an etching resist, an ultraviolet-sensitive film FOTECH 887AF-25 (manufactured by Hitachi Kakai Kogyo Co., Ltd., trade name) was laminated, and after the circuit pattern was printed and developed, it was etched with cupric chloride. The etching resist was removed using a 3% sodium carbonate solution to form a circuit pattern.

次いで、無電解めっき用のソルダーレジストとして紫外
線感光型フィルムであるフオテック5R−3000−2
2(日立化或工業株式会社製、商品名)を真空ラミネー
タを用いてラミネートし、焼付、現像、アフターキュア
を行い、ソルダーレジストを形成した。
Next, FOTECH 5R-3000-2, an ultraviolet-sensitive film, was used as a solder resist for electroless plating.
2 (manufactured by Hitachi Kakogyo Co., Ltd., trade name) using a vacuum laminator, baking, development, and after-curing were performed to form a solder resist.

次いで、硫酸銅、ホルムアルデヒド、錯化剤、苛性ソー
 ダおよびシアン化ソーダ等からなる無電解銅めっき液
であるCC−4めっき液(日立化威工業株式会社、商品
名)に9時間浸漬し、厚さ18μmのめっき銅を析出さ
せた。
Next, it was immersed for 9 hours in CC-4 plating solution (trade name, Hitachi Chemical Co., Ltd.), which is an electroless copper plating solution consisting of copper sulfate, formaldehyde, a complexing agent, caustic soda, soda cyanide, etc. Plated copper with a thickness of 18 μm was deposited.

このようにして作成したプリント配線板のエツチングレ
ジストおよびソルダーレジストの密着性および絶縁劣化
の程度を調べた結果、触媒を全く使用しない場合と、は
ぼ同様な結果が得られ、めっき触媒が、残存していない
ことが確認できた。
As a result of examining the adhesion of the etching resist and solder resist and the degree of insulation deterioration of the printed wiring board produced in this way, it was found that the results were almost the same as those obtained when no catalyst was used at all. I was able to confirm that this was not the case.

〔発明の効果〕〔Effect of the invention〕

以上に述べたように、本発明によって、密着性や絶縁性
能に悪影響を及ぼすめっき触媒を、スルーホール内のみ
に付着させることができ、信頼性に優れ、また、無電解
めっき触媒に対するレジストを形成することなく、部分
的に導電性樹脂を塗布する等の難かしい工程が無いので
1.効率よく製造する方法を提供することができた。
As described above, according to the present invention, the plating catalyst, which has a negative effect on adhesion and insulation performance, can be deposited only inside the through-hole, which is highly reliable, and also forms a resist for the electroless plating catalyst. 1. There is no difficult process such as applying conductive resin partially. We were able to provide an efficient manufacturing method.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(g)は本発明の一実施例の製造工程を
示す断面図である。 1、金属箔     2.絶縁基板 3、内層導体    4.スルーホールとなる穴5、め
っき触媒   6.エツチングレジスト7、ソルダーレ
ジスト 8 無電解めっき金属 旧
FIGS. 1(a) to 1(g) are cross-sectional views showing the manufacturing process of an embodiment of the present invention. 1. Metal foil 2. Insulating substrate 3, inner layer conductor 4. Hole 5 that becomes a through hole, plating catalyst 6. Etching resist 7, solder resist 8 Electroless plated metal old

Claims (1)

【特許請求の範囲】[Claims] 1.以下の工程からなるプリント配線板の製造法。 A.絶縁基板(1)に金属箔(1)を貼り合わせた金属
箔張り積層板にスルーホールとなる穴(4)をあける工
程。 B.前記積層板を無電解めっき用触媒(5)を含む溶液
に浸漬し、無電解めっき用触媒(5)を穴内部を含む全
表面に付与する工程。 C.前記スルーホールとなる穴(4)の内壁以外の箇所
に付着した無電解めっき用触媒(5)を除去するために
、金属箔(1)の表面を研磨する工程。 D.前記スルーホールとなる穴(4)の内壁を保護し、
回路となる部分の金属箔(1)を保護するエッチングレ
ジスト(6)を形成し、回路とならない部分の金属箔(
1)をエッチング除去し、エッチングレジスト(6)を
除去する工程。 E.無電解めっき液に耐えることができ、永久に残るソ
ルダーレジスト(7)を、スルーホールとなる穴(4)
の周囲および回路として厚さの必要な箇所もしくは位置
合わせ精度の確保が必要な箇所を除いて形成する工程。 F.前記ソルダーレジスト(7)から露出する導体上に
のみ無電解めっきを行いスルーホール内および回路とし
て厚さの必要な箇所もしくは位置合わせ精度の確保が必
要な箇所にめっき金属(8)を析出させる工程。
1. A method for manufacturing printed wiring boards that consists of the following steps. A. A process of drilling holes (4) to serve as through holes in a metal foil-clad laminate in which a metal foil (1) is bonded to an insulating substrate (1). B. A step of immersing the laminate in a solution containing an electroless plating catalyst (5) and applying the electroless plating catalyst (5) to the entire surface including the inside of the hole. C. A step of polishing the surface of the metal foil (1) in order to remove the electroless plating catalyst (5) that has adhered to areas other than the inner wall of the hole (4) that will become the through hole. D. Protecting the inner wall of the hole (4) serving as the through hole,
An etching resist (6) is formed to protect the metal foil (1) in the part that will become a circuit, and the metal foil (1) in the part that will not become a circuit is formed.
1) and removing the etching resist (6). E. The solder resist (7), which can withstand electroless plating solution and remains permanently, is inserted into the through-hole (4).
The process of forming the circuit by excluding areas where thickness is required or alignment accuracy is required. F. A step in which electroless plating is performed only on the conductor exposed from the solder resist (7), and plating metal (8) is deposited in the through holes and in areas where thickness is required for the circuit or where alignment accuracy is required. .
JP34271589A 1989-12-28 1989-12-28 Manufacture of printed circuit board Pending JPH03201592A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34271589A JPH03201592A (en) 1989-12-28 1989-12-28 Manufacture of printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34271589A JPH03201592A (en) 1989-12-28 1989-12-28 Manufacture of printed circuit board

Publications (1)

Publication Number Publication Date
JPH03201592A true JPH03201592A (en) 1991-09-03

Family

ID=18355929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34271589A Pending JPH03201592A (en) 1989-12-28 1989-12-28 Manufacture of printed circuit board

Country Status (1)

Country Link
JP (1) JPH03201592A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07302965A (en) * 1993-12-06 1995-11-14 Enthone Omi Inc Manufacture of printed circuit board
EP0762814A1 (en) * 1995-08-22 1997-03-12 Macdermid Incorporated Method for the manufacture of printed circuit boards
US6264851B1 (en) * 1998-03-17 2001-07-24 International Business Machines Corporation Selective seed and plate using permanent resist
WO2023189744A1 (en) * 2022-03-29 2023-10-05 住友電気工業株式会社 Substrate for printed wiring board and printed wiring board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07302965A (en) * 1993-12-06 1995-11-14 Enthone Omi Inc Manufacture of printed circuit board
EP0762814A1 (en) * 1995-08-22 1997-03-12 Macdermid Incorporated Method for the manufacture of printed circuit boards
JPH09102676A (en) * 1995-08-22 1997-04-15 Macdermid Inc Manufacture of printed circuit board
US6264851B1 (en) * 1998-03-17 2001-07-24 International Business Machines Corporation Selective seed and plate using permanent resist
WO2023189744A1 (en) * 2022-03-29 2023-10-05 住友電気工業株式会社 Substrate for printed wiring board and printed wiring board

Similar Documents

Publication Publication Date Title
US4152477A (en) Printed circuit board and method for making the same
US4770900A (en) Process and laminate for the manufacture of through-hole plated electric printed-circuit boards
TWI400024B (en) Wiring substrate and its manufacturing process
JP2006278774A (en) Double-sided wiring board, method for manufacturing the same and base substrate thereof
JP4129665B2 (en) Manufacturing method of substrate for semiconductor package
JPH06275950A (en) Manufacture of wiring board
JP2001110940A (en) Semiconductor package substrate and manufacturing method thereof
JPH03201592A (en) Manufacture of printed circuit board
JPS646555B2 (en)
JP2001111201A (en) Method of manufacturing wiring board and wiring board using the same
JPH09307216A (en) Manufacture of wiring board, and wiring board
JPH05259611A (en) Production of printed wiring board
JPH0964538A (en) Production of printed wiring board
JPH08148810A (en) Manufacture of printed wiring board
EP0848585A1 (en) Process for the manufacture of printed circuit boards with plated resistors
JPS6345887A (en) Manufacture of printed wiring board
JP2001085567A (en) Electronic member and production thereof
JPH05175653A (en) Manufacture of printed wiring board
JPS59175797A (en) Method of producing multilayer printed plate
JPH0653640A (en) Printed wiring board and manufacture thereof
JPS5850040B2 (en) Manufacturing method of printed circuit board
JPH0449795B2 (en)
JPS63302593A (en) Manufacture of printed circuit board
JPH03194992A (en) Manufacture of printed board
JPH0453189A (en) Manufacture of wiring board