JPH0320048A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0320048A JPH0320048A JP15539389A JP15539389A JPH0320048A JP H0320048 A JPH0320048 A JP H0320048A JP 15539389 A JP15539389 A JP 15539389A JP 15539389 A JP15539389 A JP 15539389A JP H0320048 A JPH0320048 A JP H0320048A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- hole
- photoresist
- etching
- whole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 17
- 238000005530 etching Methods 0.000 abstract description 5
- 238000005336 cracking Methods 0.000 abstract description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造方法に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a method for manufacturing a semiconductor device.
従来の技術
高周波用の半導体素子では、ソースインダクタンス或分
低減のため、ンース部をすみやかに接地する必要がある
。このため素子裏面を接地部とし、これとソース部とを
直結する貫通孔を基板に形威し、この貫通孔を金属によ
って埋め、ソース部を最短距離で接地する方法が用いら
れる。又、大電力を扱う素子では、放熱を良くするため
に、基板の厚みを、できるだけ薄くしたいという要請が
ある。この必要を満たすため、従来、第2図aに示す様
に半導体基板1を、機械研摩やウェットエッチングによ
り、第2図bに示す様に30μlから40μ鳳程度の厚
みにした後、第2図Cに示すように、フォトレジスト等
をマスクとし,ドライエッチングにより、貫通孔を形威
していた。In conventional high frequency semiconductor devices, it is necessary to quickly ground the ground portion in order to reduce the source inductance to some extent. For this reason, a method is used in which the back surface of the element is used as a grounding section, a through hole is formed in the substrate to directly connect this to the source section, and this through hole is filled with metal to ground the source section at the shortest distance. Furthermore, in devices that handle large amounts of power, there is a demand for the thickness of the substrate to be as thin as possible in order to improve heat dissipation. In order to meet this need, conventionally, as shown in FIG. 2a, the semiconductor substrate 1 is made into a thickness of about 30 μl to 40 μl as shown in FIG. 2b by mechanical polishing or wet etching, and then As shown in C, through holes were formed by dry etching using a photoresist or the like as a mask.
発明が解決しようとする課題
しかし上記の様に、基板を薄くしてから、貫通孔の形或
工程を行うと、工程中の機械的歪や熱歪等によク、基板
に割れが生じる。Problems to be Solved by the Invention However, as described above, if a process for forming through holes is performed after the substrate is made thin, cracks will occur in the substrate due to mechanical strain, thermal strain, etc. during the process.
課題を解決するための手段
上記の課題を解決するため、本発明の製造方法では、従
来よりも厚い状態の基板に貫通孔を形戊し、その後貫通
孔内のみを、埋め込み、全面をエッチングすることによ
り、貫通孔を持つ薄い基板を得る。Means for Solving the Problems In order to solve the above problems, in the manufacturing method of the present invention, a through hole is formed in a substrate that is thicker than before, and then only the inside of the through hole is filled and the entire surface is etched. By this, a thin substrate with through holes is obtained.
作用
上記の方法では、貫通孔を形或する段階では、従来の方
法に比べ、基板が厚く強度が高いため、貫通孔形戊工程
中の基板の割れが発生しない。Effect: In the above-mentioned method, the substrate is thicker and stronger than the conventional method at the stage of forming the through-hole, so that cracking of the substrate does not occur during the step of forming the through-hole.
実施例
第1図は、本発明の一実施例を示す工程の断面図で、G
aAs基板に貫通孔を形戊する工程を示すものである。Embodiment FIG. 1 is a sectional view of a process showing an embodiment of the present invention.
This figure shows the process of forming a through hole in an aAs substrate.
第1図八のように、例えば120μlの厚みにした半絶
縁性G&▲S基板3上に、選択的にフォトレジスト4を
形戊し、次に第1図bのように、cc4 2F 2と▲
rの混合ガスを用いたりアクティブイオンエッチング(
RIB )により、フォトレジスト4をマスクとしてG
a▲S基板を削り、基板を貫通する穴を形或する。フォ
トレジスト4を除去した後、基板全面にボジ形7才トレ
ジスト6を塗布し、全面露光,現像を施すことにより、
第1図Cのように、先に形戊した貫通孔の内部にのみ、
フォトレジスト5を残す。その後りん酸系のエッチング
液によシ、第1図dのように基板全面をウェットエッチ
ングする。残ったフォトレジスト6を除去することによ
り、第1図6のように、選択的に貫通孔の形或された、
厚さ30μmのGaAg基板を得る。尚本実施例では、
120μl厚のGaAs 基板を、フォトレジストをマ
スクとして、COl2F2と▲rの混合ガスを用いたR
IBにより、ドライエッチングし、りん酸系のエッチン
グ液で、30μm厚筐でウエットエッチングを行ったが
、同様の方法をSi,InP等の基板に用いることがで
キル。1たマスクもフォトレジストに限らず、SiN膜
やSi02膜などの誘電体膜、あるいは金属膜でも良く
、ドライエッチング及びウエットエッチングの方法も、
本実施例の方法に限ったものではない。As shown in FIG. 18, a photoresist 4 is selectively formed on the semi-insulating G&▲S substrate 3 with a thickness of, for example, 120 μl, and then as shown in FIG. 1b, cc4 2F 2 and ▲
Active ion etching (
RIB) using photoresist 4 as a mask.
a▲S Cut the substrate to form a hole that passes through the substrate. After removing the photoresist 4, a positive-type 7-year-old photoresist 6 is applied to the entire surface of the substrate, and the entire surface is exposed and developed.
As shown in Figure 1C, only inside the previously formed through hole,
Leave photoresist 5. Thereafter, the entire surface of the substrate is wet-etched using a phosphoric acid-based etching solution as shown in FIG. 1d. By removing the remaining photoresist 6, as shown in FIG. 1, through-holes are selectively formed.
A GaAg substrate with a thickness of 30 μm is obtained. In this example,
A 120 μl thick GaAs substrate was subjected to R treatment using a mixed gas of COl2F2 and ▲r using a photoresist as a mask.
Dry etching was performed using IB, and wet etching was performed using a phosphoric acid-based etching solution on a 30 μm thick casing, but the same method can be used for substrates such as Si and InP. The first mask is not limited to photoresist, but may also be a dielectric film such as SiN film or Si02 film, or a metal film, and dry etching and wet etching methods are also available.
The method is not limited to the method of this embodiment.
発明の効果
以上の様に本発明は、従来よシも厚い状態の半導体基板
に、貫通孔を形或した後、形或した貫通孔の内部を、基
板以外の物質で埋め込み、基板全面をウェットエッチン
グすることにより、基板の割れを防ぎ、かつ貫通した側
の面積が均一な貫通孔を持つ、薄い半導体基板を得るこ
とを可能とするもので、その実用的効果は大なるものが
ある。As described above, the present invention has the following advantages: After forming a through hole in a semiconductor substrate which is thicker than conventional ones, the inside of the formed through hole is filled with a substance other than the substrate, and the entire surface of the substrate is wetted. By etching, it is possible to prevent the substrate from cracking and to obtain a thin semiconductor substrate that has through holes with a uniform area on the penetrated side, and has great practical effects.
第1図a〜eは本発明の製造方法による、貫浦孔を有す
る薄い半導体基板の形戊工程を示す断面図、第2図a〜
Cぱ従来の製造方法による貫通孔を有する薄い半導体基
板の形或工程を示す断面図である。
1・・・・・・半導体基板、2・・・・・・フォトレン
スト、3・・・・・半絶縁性GaAs基板、4・・・・
・・フォトレジスト、5・・・・・・フォトレジスト。1A to 1E are cross-sectional views showing the process of forming a thin semiconductor substrate having through-holes according to the manufacturing method of the present invention, and FIGS.
FIG. 3 is a cross-sectional view showing the shape and process of a thin semiconductor substrate having a through hole according to a conventional manufacturing method. 1...Semiconductor substrate, 2...Photorenst, 3...Semi-insulating GaAs substrate, 4...
...Photoresist, 5...Photoresist.
Claims (1)
と、その後半導体基板を薄くする工程とからなる、半導
体装置の製造方法。A method for manufacturing a semiconductor device, comprising the steps of embedding a through hole in a semiconductor substrate provided with a through hole, and then thinning the semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15539389A JPH0320048A (en) | 1989-06-16 | 1989-06-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15539389A JPH0320048A (en) | 1989-06-16 | 1989-06-16 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0320048A true JPH0320048A (en) | 1991-01-29 |
Family
ID=15604976
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15539389A Pending JPH0320048A (en) | 1989-06-16 | 1989-06-16 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0320048A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6974972B1 (en) | 1999-10-21 | 2005-12-13 | Matsushita Electric Industrial Co., Ltd. | Thin-film transistor, and liquid crystal display device using the same |
-
1989
- 1989-06-16 JP JP15539389A patent/JPH0320048A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6974972B1 (en) | 1999-10-21 | 2005-12-13 | Matsushita Electric Industrial Co., Ltd. | Thin-film transistor, and liquid crystal display device using the same |
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