JPH03200310A - Laminated thin-film dielectric element and manufacture thereof - Google Patents

Laminated thin-film dielectric element and manufacture thereof

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Publication number
JPH03200310A
JPH03200310A JP33978489A JP33978489A JPH03200310A JP H03200310 A JPH03200310 A JP H03200310A JP 33978489 A JP33978489 A JP 33978489A JP 33978489 A JP33978489 A JP 33978489A JP H03200310 A JPH03200310 A JP H03200310A
Authority
JP
Japan
Prior art keywords
film
films
electrode
thickness
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33978489A
Other languages
Japanese (ja)
Inventor
Tetsuya Urano
浦野 哲也
Masayuki Fujimoto
正之 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP33978489A priority Critical patent/JPH03200310A/en
Publication of JPH03200310A publication Critical patent/JPH03200310A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To enable forming the title dielectric element according to a thin film thickness by forming double electrode films having SnO2 thin film on the front and Cr, Ni or Cu thin film on the rear and further TiO2 dielectric thin films through causing these films to make an epitaxial growth respectively by means of vapor deposition and by laminating these two sorts of films alternately. CONSTITUTION:A part or the whole of plural layers of double electrode films 2, 3, as internal electrode layers for obtaining capacity, is composed of at least 2 groups connected with lead-out ends differing from each other. In this case, the double electrode films 2, 3 belonging to the same group are respectively taken out to the same side end and connected with the terminal electrode 20 of Cu or Ni arranged or formed at the side end and having Ni metallic deposit 21 on the surface. Thus, a low-cost glass substrate 1 is used so that internal electrode thin films can alternately be laminated on the glass substrate according to a thin thickness while holding dielectric thin films between them.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、積層構造を有する薄膜誘電体素子およびそ
の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film dielectric element having a laminated structure and a method for manufacturing the same.

[従来の技術] 従来、小型かつ大容量を有する誘電体素子としてセラミ
ック積層体コンデンサが多用されており、リード線のな
いチップ型積層コンデンサでは、薄い誘電体セラミック
ス層をはさんで、容量を取得するための内部電極層が交
互に対向して積層されていて、その内部電極末端部は直
接半田付は可能な外部端子電極に接続されている。
[Conventional technology] Conventionally, ceramic multilayer capacitors have been widely used as dielectric elements with small size and large capacity.In chip-type multilayer capacitors without lead wires, capacitance is obtained by sandwiching thin dielectric ceramic layers. Internal electrode layers are alternately stacked to face each other, and the terminal ends of the internal electrodes are connected to external terminal electrodes that can be directly soldered.

この積層型コンデンサにおいて素子の取得容量を上げる
ために通常、誘電体層1層あたりの厚さを薄くすること
が試みられている。しかし積層セラミックコンデンサの
場合、厚さ10血以下のセラミックス誘電体層を実現し
ようとすると、薄いグリーンシートの作成、電極ペース
トのシートアタック、圧着成形、焼成後の誘電体粒子の
粒径コントロールなど多くの困難な技術的課題があり、
現状では、誘電体層厚5血を切るセラミック積層コンデ
ンサは公表されていない。
In order to increase the acquisition capacity of the element in this multilayer capacitor, attempts are usually made to reduce the thickness of each dielectric layer. However, in the case of multilayer ceramic capacitors, in order to realize a ceramic dielectric layer with a thickness of 10 mm or less, there are many steps such as creating a thin green sheet, sheet attack of electrode paste, pressure molding, and controlling the particle size of dielectric particles after firing. difficult technical challenges,
At present, no ceramic multilayer capacitor with a dielectric layer thickness of less than 5 mm has been announced.

一方、蒸着、スパッタリングなどの蒸着技術を用いて、
高い静電容量を有する薄膜コンデンサを作製する試みも
なされているが、高い静電容量の取得が期待できるチタ
ン酸バリウム、鉛系ペロブスカイトなど強誘電体材料系
薄膜では、キュリー点通過時の結晶相転移による歪の問
題から良質の誘電体薄膜は得られていない。またこの結
晶相転移時に発生する歪の問題を回避するためには下地
基板からエピタキシャル成長させる方法もあるが、下地
基板が高価な単結晶(例えばSrTiO3、ptなど)
に限られてしまうため、実用化の目途は立っていない。
On the other hand, using vapor deposition techniques such as vapor deposition and sputtering,
Attempts have been made to fabricate thin film capacitors with high capacitance, but thin films based on ferroelectric materials such as barium titanate and lead-based perovskite, which can be expected to obtain high capacitance, have a crystalline phase when passing the Curie point. Good quality dielectric thin films have not been obtained due to the problem of distortion caused by dislocation. In addition, in order to avoid the problem of distortion that occurs during this crystal phase transition, there is a method of epitaxial growth from a base substrate, but the base substrate is made of an expensive single crystal (for example, SrTiO3, PT, etc.).
Since it is limited to , there is no prospect of practical application.

[発明が解決しようとする課題] 前述のように、積層セラミックコンデンサの一層の小型
化に対する要望に対して種々検討されているにもかかわ
らず、誘電体の膜厚が51μmmを下回るような製品は
まだ実用化されておらず、また蒸着を用いた薄膜コンデ
ンサでも前述のような欠点があった。したがって、良質
な誘電体膜を10m、好ましくは5Raを下回る厚さで
、低コストかつ簡便に積層化する技術がなかった。
[Problems to be Solved by the Invention] As mentioned above, despite various studies being conducted to meet the demand for further miniaturization of multilayer ceramic capacitors, products with a dielectric film thickness of less than 51 μmm have not been produced. It has not yet been put to practical use, and even thin film capacitors using vapor deposition have the drawbacks mentioned above. Therefore, there has been no technology for simply laminating high-quality dielectric films to a thickness of 10 m, preferably less than 5 Ra, at low cost.

本発明の目的は、高価な単結晶基板を用いないで、膜厚
が1Ou1n1好ましくは5urnを下回る誘電体薄膜
で形成した積層薄膜誘電体素子を提供することにある。
An object of the present invention is to provide a laminated thin film dielectric element formed of a dielectric thin film having a thickness of less than 1 urn, preferably less than 5 urn, without using an expensive single crystal substrate.

[課題を解決するための手段および作用]本発明者等は
上記目的を達成すべく研究の結果、安価なガラス基板を
用い、その上に蒸着法で表面にSnO,薄膜、裏面にC
r、NiまたはCu薄膜を有する2重電極膜(以下Sn
O2/(Cr、NiまたはCu)2重電極膜と略記する
)を、さらにTiO2誘電体薄膜をそれぞれエピタキシ
ャル成長させて形成し、これら2種の膜を交互に積層さ
せることによって従来の積層セラミックコンデンサと同
様な構造をもち、しかも膜厚がlOm、好ましくは5D
よりも薄く約l umをも可能とする積層型薄膜誘電体
素子が得られることを見い出し本発明に到達した。
[Means and effects for solving the problem] In order to achieve the above object, the present inventors conducted research and found that they used an inexpensive glass substrate and deposited a thin film of SnO on the surface and a carbon film on the back surface using an evaporation method.
r, double electrode film with Ni or Cu thin film (hereinafter referred to as Sn
By epitaxially growing an O2/(Cr, Ni or Cu) double electrode film and a TiO2 dielectric thin film, and alternately stacking these two types of films, a conventional multilayer ceramic capacitor can be formed. It has a similar structure and a film thickness of 10m, preferably 5D.
The present inventors have discovered that it is possible to obtain a laminated thin-film dielectric element that is thinner than the above-described method and can be made thinner to about lumen.

すなわち、本発明は第一に下記の如き積層型薄膜誘電体
素子を提供するものである。
That is, the present invention first provides a laminated thin film dielectric element as described below.

ガラス基板上に、表面にSnO2薄膜、裏面にCr5N
iまたはCu薄膜を有する厚さto、ccm以下、好ま
しくは5血以下の2重電極膜と厚さ10Il−以下、好
ましくは5重m以下のTiO2誘電体膜とが交互に積層
された基本構造を持ち、前記複数層の2重電極膜の内の
一部または全部は、容量を取得するための内部電極層と
して、互いに異なる導出端に接続された少な、くとも2
群からなっていて、同じ群に属する2重電極膜はそれぞ
れ同じ側端部に引き出され、該側端部に配置または形成
された、表面にNiメッキ層を有するCuまたはNiの
端子電極に接続されていることを特徴とする積層型薄膜
誘電体素子。
On the glass substrate, SnO2 thin film on the front side and Cr5N on the back side
A basic structure in which dual electrode films with a thickness of 1 or Cu thin films having a thickness of to, less than 5 ccm, preferably less than 5 cm, and TiO2 dielectric films with a thickness of less than 10 Il, preferably less than 5 m are laminated alternately. A part or all of the plurality of double electrode films has at least two layers connected to different lead-out ends as internal electrode layers for obtaining capacitance.
The double electrode films belonging to the same group are each drawn out to the same side edge and connected to a Cu or Ni terminal electrode arranged or formed on the side edge and having a Ni plating layer on the surface. A multilayer thin film dielectric element characterized by:

本発明は第二に、下記の如き積層型薄膜誘電体素子の製
法を提供するものである。
Second, the present invention provides a method for manufacturing a laminated thin film dielectric element as described below.

(イ)ガラス基板上にCVD法により所定の形状と面積
をもつ厚さ10um以下、好ましくは5血以下のSnO
2/((:r、NiまたはCu)2重電極膜(表面にS
nO2薄膜、裏面にCr5NiまたはCu薄膜を有する
2重電極膜)を形成し、不要な部分をウェットエツチン
グにより除去して・第1のS n 02 / CCr、
NiまたはCu) 2重電極膜(1)とし; (ロ)このSnO2/(Cr、NiまたはCu)2重電
極膜(1)の上にCVD法により、下地SnO2膜に対
してエピタキシャル成長させて厚さ101tla以下、
好ましくは5IIIa以下のT i O2誘電体膜を形
成し、不要な部分をドライエツチング法で除去して第1
のTiO2膜(1)とし;(ハ)上記T i O2膜(
1)の上にCVD法によりエピタキシャル成長させて厚
さ1oI11a以下、好ましくは5ura以下のS n
 O2/ (Cr SN lまたはCu)2重電極膜を
形成し、不要な部分をウェットエツチングにより除去し
て第2のS n 02 / (Cr、NiまたはCo)
’;1重電極膜(わとし;(ニ)上記SnO2/(Cr
、NiまたはCu)2重電極膜(りの上に(ロ)と同じ
要領で第2のTiO2膜(りを形成し、 上記(イ)〜(ニ)の全部または一部を繰り返した後、
積層体の側端部を一部切断除去して複数の2重電極膜の
端部が切断面に現われるようにし、該切断面に表面にN
iメッキ層を有するCuまたはNiの端子電極を形成す
ることからなる下記の誘電体素子、すなわち、ガラス基
板上に、表面にSnO2薄膜、裏面にCr5Niまたは
Cu薄膜を有する厚さ10μm以下、好ましくは511
!a以下の2重電極膜と厚さ10m以下、好ましくは5
11M以下のTiO2誘電体膜とが交互に積層された基
本構造を持ち、前記複数層の2重電極膜の内の一部また
は全部は、容量を取得するための内部電極層として、互
いに異なる導出端に接続された少なくとも2群からなっ
ていて、同じ群に属する2重電極膜はそれぞれ同じ側端
部に引き出され、該側端部に配置または形成された、表
面にNiメッキ層を有するCuまたはNiの端子電極に
接続されていることを特徴とする積層型薄膜誘電体素子
の製法。
(b) SnO with a thickness of 10 um or less, preferably 5 um or less, having a predetermined shape and area by CVD on a glass substrate.
2/((:r, Ni or Cu) double electrode film (S on the surface
A double electrode film having an nO2 thin film and a Cr5Ni or Cu thin film on the back surface is formed, and unnecessary portions are removed by wet etching to form a first Sn02/CCr,
(Ni or Cu) double electrode film (1); (b) On this SnO2/(Cr, Ni or Cu) double electrode film (1), epitaxial growth is performed on the base SnO2 film by CVD method to form a thick layer. less than 101 tla,
Preferably, a TiO2 dielectric film with a thickness of 5IIIa or less is formed, and unnecessary portions are removed by dry etching to form the first film.
Assume that the TiO2 film (1) is; (c) the above TiO2 film (
1) is epitaxially grown by the CVD method to a thickness of 1oI11a or less, preferably 5ura or less.
A double electrode film of O2/(Cr, Ni, or Co) is formed, and unnecessary portions are removed by wet etching to form a second Sn02/(Cr, Ni, or Co).
';Single electrode film (Watoshi);(d)The above SnO2/(Cr
, Ni or Cu) on the double electrode film (2) in the same manner as in (2), and after repeating all or part of the above (a) to (d),
A portion of the side edges of the laminate is cut and removed so that the ends of the plurality of double electrode films appear on the cut surface, and N is applied to the surface of the cut surface.
The following dielectric element consists of forming a Cu or Ni terminal electrode with an i-plated layer, i.e., a glass substrate with a SnO thin film on the front surface and a Cr5Ni or Cu thin film on the back surface with a thickness of 10 μm or less, preferably 511
! A double electrode film of less than a and a thickness of less than 10 m, preferably 5
It has a basic structure in which TiO2 dielectric films of 11M or less are laminated alternately, and some or all of the plurality of double electrode films are used as internal electrode layers to obtain capacitance. It consists of at least two groups connected to the ends, and the double electrode films belonging to the same group are each drawn out to the same side end, and the Cu layer having a Ni plating layer on the surface is disposed or formed on the side end. Or a method for manufacturing a laminated thin film dielectric element, characterized in that the element is connected to a Ni terminal electrode.

第1図は本発明の積層薄膜誘電体素子製造における成膜
順序を示す模式断面図であって、同図(h)に示される
ように、ガラス基板1上にSnO□/(Cr、Niまた
はCu)2重電極膜およびT i O2誘電体膜が交互
に積層され、薄膜の両端に外部端子電極が設けられ、内
部電極であるSnO2/ (CrSNiまたはCu)2
重電極膜が引き出された構造となって、従来の積層セラ
ミックコンデンサと同様の構造を有している。
FIG. 1 is a schematic cross-sectional view showing the film formation order in manufacturing the laminated thin film dielectric element of the present invention. As shown in FIG. Cu) dual electrode films and TiO2 dielectric films are alternately laminated, external terminal electrodes are provided at both ends of the thin film, and internal electrodes of SnO2/(CrSNi or Cu)2
It has a structure in which the heavy electrode film is drawn out, and has a structure similar to that of a conventional multilayer ceramic capacitor.

また、ガラス基板または誘電体膜との密着を良好にする
ため、電極膜の裏面にはCr、NiおよびCuのうちい
ずれか1種からなる薄膜を配して2重膜構造とした。し
たがって、安価なガラス基板を用いて以上のような積層
構造を形成することにより、低コストかつ簡便に101
na以下、好ましくは5血よりも薄い誘電体膜を持つ積
層薄膜誘電体素子を提供することができるようになった
Further, in order to improve adhesion to the glass substrate or dielectric film, a thin film made of any one of Cr, Ni, and Cu was disposed on the back surface of the electrode film to form a double film structure. Therefore, by forming the above-described laminated structure using an inexpensive glass substrate, the 101
It is now possible to provide a laminated thin film dielectric element having a dielectric film thinner than 500 nm, preferably less than 500 nm.

以下実施例により本発明をさらに説明する。The present invention will be further explained below with reference to Examples.

[実施例1] 前述の第1図(a)〜(h)に従って、本発明の積層薄
膜誘電体素子の作製順序を説明する。
[Example 1] The manufacturing order of the laminated thin film dielectric element of the present invention will be explained according to the above-mentioned FIGS. 1(a) to (h).

(a)ホウケイ酸ガラス基板(コーニング社製#705
9) 1上にSnO□膜3の表面層・とCr膜2の裏面
層からなり、各膜厚が0.5血の2重電極膜を形成し、
このSnO2/Cr2重電極膜の片側端部をウェットエ
ツチングにより除去、SnO2/Cr2重電極電極膜(
1)とした。
(a) Borosilicate glass substrate (Corning #705
9) A double electrode film consisting of a surface layer of SnO □ film 3 and a back layer of Cr film 2, each having a thickness of 0.5 mm, is formed on 1.
One end of this SnO2/Cr double electrode film was removed by wet etching, and the SnO2/Cr double electrode film (
1).

(b)2重電極膜■にCVD法によりTiO2膜4を下
地SnO2膜3に対してエピタキシャル成長により、1
伽の厚さで形成し、TiO2誘電体膜■とする。
(b) A TiO2 film 4 is epitaxially grown on the base SnO2 film 3 by the CVD method on the double electrode film (1).
The TiO2 dielectric film 2 is formed to have a thickness of 100 cm.

(c)このTiO2誘電体膜■に上述のようなSnO2
/Cr2重電極膜5を各膜厚0.5zcmで成膜し、そ
の片側端部をウェットエツチング法により除去してSn
O2/Cr2重電極膜(つとした。
(c) This TiO2 dielectric film ■ has SnO2 as described above.
A /Cr double electrode film 5 was formed with a thickness of 0.5 zcm each, and one end of the film was removed by wet etching to form an Sn
O2/Cr double electrode film (Tsutsuto).

(d)次に、CVD法によりTiO2膜6を下地SnO
2膜に対してエピタキシャル成長により1伽の膜厚で形
成し、TiO2!!!誘電体膜(つとした。このとき、
TiO2誘電体膜(りはTiO□誘電体膜■と直接に接
合してSnO2/Cr2重電極膜■の片側端部を覆うよ
うな形状となる。
(d) Next, the TiO2 film 6 is coated with SnO as an underlayer by CVD method.
TiO2! is formed by epitaxial growth to a film thickness of 1. ! ! Dielectric film (Tsutsuto. At this time,
The TiO2 dielectric film (the TiO2 dielectric film (2) is directly bonded to the TiO2 dielectric film (2) and has a shape that covers one end of the SnO2/Cr double electrode film (2).

(e)さらにTiO、誘電体膜(りに前述のようなS 
n 02 / Cr 2重電極膜7を1urmの膜厚(
各膜厚0.5111m)で成膜し、片側端部をウェット
エツチングにより除去してSnO2/Cr2重電極膜■
とした。
(e) Furthermore, TiO, dielectric film (S
The n 02 /Cr double electrode film 7 has a film thickness of 1 urm (
A SnO2/Cr double electrode film
And so.

(f)さらにCVD法によりTiO2膜8を下地SnO
2膜に対してエピタキシャル成長により1ilpaの膜
厚で形成し、TiO□誘電体膜■とした。
(f) Furthermore, the TiO2 film 8 is coated with SnO as an underlayer by CVD method.
Two films were formed with a thickness of 1 ilpa by epitaxial growth to form a TiO□ dielectric film ■.

このとき、TiO2誘電体膜■はTiO2誘電体膜(つ
と直接に接合してSnO□/C「2重電極膜■の片側端
部を覆うような形状となる。
At this time, the TiO2 dielectric film (2) is directly bonded to the TiO2 dielectric film (2) and has a shape that covers one end of the SnO2/C double electrode film (2).

(g)以上の工程から得られた積層膜上に、前述のよう
なS n O2/ Cr 2重電極膜9を1111mの
膜厚(各膜厚0.5ItIa)で成膜し、片側端部をウ
ェットエツチング法により除去してSnO□/ Cr 
2重電極膜に)とした。
(g) On the laminated film obtained from the above steps, a SnO2/Cr double electrode film 9 as described above is formed to a film thickness of 1111 m (each film thickness 0.5 ItIa), and one end was removed by wet etching method to form SnO□/Cr
double electrode film).

(h)上記(a)〜(g)の工程を繰り返すことで、T
iO2誘電体膜をはさんで、SnO2/Cr2重電極膜
が交互にバターニングされた積層膜を形成した。
(h) By repeating the steps (a) to (g) above, T
A laminated film was formed in which SnO2/Cr double electrode films were patterned alternately with iO2 dielectric films in between.

(i)次いで、同図(g)に示す仮想線に沿って試料を
切断し、断面に電極を露出させた。
(i) Next, the sample was cut along the imaginary line shown in FIG. 4(g) to expose the electrodes on the cross section.

(j)切断面にCuペーストを塗布し、窒素雰囲気中で
500℃、2時間の焼成を行い、同図(h)に示される
ようにCu端子電極20を形成した。
(j) A Cu paste was applied to the cut surface and baked at 500°C for 2 hours in a nitrogen atmosphere to form a Cu terminal electrode 20 as shown in (h) of the figure.

さらにこの端子電極20の上にメッキによりNi層21
を形成した。
Furthermore, a Ni layer 21 is formed on this terminal electrode 20 by plating.
was formed.

同方法により、同一積層数で比較した場合、最も高い静
電容量を得ることができる。
By this method, the highest capacitance can be obtained when comparing the same number of laminated layers.

[実施例2] 第2図(a)〜(g)に従って、本発明の積層薄膜誘電
体素子の作製順序を説明する。
[Example 2] The manufacturing order of the laminated thin film dielectric element of the present invention will be explained according to FIGS. 2(a) to 2(g).

(a)ホウケイ酸ガラス基板(コーニング社製#705
9) 1上にSnO2膜3の表面層とCr膜2の裏面層
からなり、各膜厚が0.5mの2重電極膜を形成し、こ
のSnO□/C「2重電極膜の両側端部をウェットエツ
チングにより除去、SnO□/C「2重電極電極膜(1
)とした。
(a) Borosilicate glass substrate (Corning #705
9) A double electrode film consisting of the surface layer of the SnO2 film 3 and the back layer of the Cr film 2, each having a thickness of 0.5 m, is formed on the SnO□/C double electrode film. The SnO□/C double electrode film (1) was removed by wet etching.
).

(b)2重電極膜■にCVD法によりTiO2膜4を下
地SnO2膜3に対してエピタキシャル成長により、1
伽の厚さで形成し、TiO2誘電体膜■とする。
(b) A TiO2 film 4 is epitaxially grown on the base SnO2 film 3 by the CVD method on the double electrode film (1).
The TiO2 dielectric film 2 is formed to have a thickness of 100 cm.

(c)このTiO□誘電体膜■に上述のようなSnO,
/Cr2重電極85を各膜厚0.5血で成膜し、その片
側端部をウェットエツチング法により除去してSnO2
/Cr2重電極膜(つとした。
(c) This TiO□dielectric film■ has SnO as described above,
A /Cr double electrode 85 is formed with a film thickness of 0.5 mm each, and one end thereof is removed by wet etching to form SnO2.
/Cr double electrode film (Tsutsuto.

(d)次に、CVD法によりT i 02 M6を下地
SnO2膜に対してエピタキシャル成長により1血の膜
厚で形成し、T i 02膜誘電体膜(りとした。この
とき、T i O2誘電体膜(りはTiO2誘電体膜■
と直接に接合してSnO2/Cr2重電極膜(つの片側
端部を覆うような形状となる。
(d) Next, T i 02 M6 is epitaxially grown on the base SnO2 film by CVD method to a film thickness of 1 cm, and the Ti 02 dielectric film (reduced) is formed. Body membrane (TiO2 dielectric film)
The SnO2/Cr dual electrode film is directly bonded to the SnO2/Cr double electrode film (to form a shape that covers one end of the SnO2/Cr double electrode film).

(e)さらにTiO2誘電体膜■に前述のようなSnO
2/Cr2重電極膜7をμmlfaの膜厚(各膜厚0.
5m+)で成膜し、片側端部をウェットエツチングによ
り除去してS口0□/Cr2重電極膜■とした。
(e) Furthermore, the TiO2 dielectric film
The 2/Cr dual electrode film 7 has a film thickness of μmlfa (each film thickness 0.
A film of 5m+) was formed, and one end was removed by wet etching to form an S opening 0□/Cr double electrode film ■.

(f)さらにCVD法によりTtO□膜8を下地SnO
2膜に対してエピタキシャル成長により1血の膜厚で形
成し、TiO2誘電体膜■とした。
(f) Further, by CVD method, the TtO□ film 8 is coated with SnO
A TiO2 dielectric film (2) was formed by epitaxial growth to a thickness of one layer for two films.

このとき、T i O2誘電体膜■はTiQ、誘電体r
m<つと直接に接合してS n 02 / Cr 2重
電極膜■の片側端部を覆うような形状となる。
At this time, the TiO2 dielectric film ■ is TiQ, the dielectric r
The shape is such that it is directly bonded to the S n 02 /Cr double electrode film and covers one end of the S n 02 /Cr double electrode film.

(g)以上の工程から得られた積層膜上に、前述のよう
なSnO2/Cr2重電極膜9をl ilmの膜厚(各
膜厚0.5za++)で成膜し、片側端部をウェットエ
ツチング法により除去してSnO2/Cr2重電極膜に
)とした。
(g) On the laminated film obtained from the above steps, a SnO2/Cr double electrode film 9 as described above is formed to a film thickness of 1 ilm (each film thickness 0.5za++), and one end is wetted. It was removed by an etching method to form a SnO2/Cr double electrode film).

(h)次にCVD法によりTiO2膜lOを下地S n
 O2膜に対してエピタキシャル成長により1鴎の膜厚
で形成し、T t 02誘電体膜に)とした。
(h) Next, a TiO2 film lO is deposited as a base S n by CVD method.
The O2 film was epitaxially grown to a thickness of 1 mm to form a T t 02 dielectric film.

このとき、TiO2誘電体膜に)はTiO□誘電体誘電
体膜法に接合してS n 02 / Cr 2重電極膜
に)の片側端部を覆うような形状となる。
At this time, the TiO2 dielectric film) is bonded to the TiO□ dielectric film method to form a shape that covers one end of the Sn02/Cr double electrode film).

(i)さらにT i Q2誘電体膜に)に前述のような
SnO2/Cr2重電極膜11を111Mの膜厚(各膜
厚0.5μm)で成膜し、片側端部をウェットエツチン
グにより除去してSnO2/Cr2重電極膜■とした。
(i) Further on the T i Q2 dielectric film), a SnO2/Cr double electrode film 11 as described above was formed to a film thickness of 111M (each film thickness 0.5 μm), and one end was removed by wet etching. This resulted in a SnO2/Cr double electrode film (2).

(j)さらにCvD法ニヨリTiO2膜12を下地S 
n 02膜に対してエピタキシャル成長により1血の膜
厚で形成し、T i O2誘電体膜■とした。
(j) Furthermore, a CvD method Niyori TiO2 film 12 is applied as a base layer S.
A T i O2 dielectric film (2) was formed by epitaxial growth on the n02 film to a thickness of one layer.

このとき、TiO2誘電体膜■はTiO□誘電体誘電体
膜法に接合してS n O2/ Cr 2重電極膜■の
片側端部を覆うような形状となる。
At this time, the TiO2 dielectric film (2) is bonded to the TiO□ dielectric film method so as to cover one end of the S n O2/Cr double electrode film (2).

必要に応じて、(aSb)、(cSd)、(esf)(
あるいはg、h)(あるいは1Sj)の操作の全部また
は一部を繰り返すことができるが、ここでは省略する。
(aSb), (cSd), (esf)(
Alternatively, all or part of the operations g, h) (or 1Sj) can be repeated, but they are omitted here.

(k)以上の工程から得られた積層膜上に、前述のよう
なSnO2/Cr2重電極膜13をIIIMの膜厚(各
膜厚0.5IIn)で成膜し、両側端部をウェットエツ
チング法により除去してSnO2/Cr2重電極膜■と
した。
(k) On the laminated film obtained from the above steps, the SnO2/Cr double electrode film 13 as described above is formed to a film thickness of IIIM (each film thickness 0.5IIn), and both side edges are wet etched. The SnO2/Cr double electrode film (2) was removed by the method.

(p)次いで、同図(k)に示す仮想線に沿って試料を
切断し、断面に電極を露出させた。
(p) Next, the sample was cut along the imaginary line shown in (k) of the figure to expose the electrodes on the cross section.

切断面にCuペーストを塗布し、窒素雰囲気中で500
℃2時間の焼成を行い、同図(R)に示されるようにC
u端子電極20を形成した。
Apply Cu paste to the cut surface and heat it for 500 min in a nitrogen atmosphere.
After baking for 2 hours at ℃, as shown in the same figure (R),
A u-terminal electrode 20 was formed.

さらにこの端子電極20の上にメッキによりNi層21
を形成した。この結果、SnO2/Cr電極膜13は両
側の端子電極から独立した第3の電極となる。
Furthermore, a Ni layer 21 is formed on this terminal electrode 20 by plating.
was formed. As a result, the SnO2/Cr electrode film 13 becomes a third electrode independent of the terminal electrodes on both sides.

(m)以上の結果、T i O2膜からなる誘電体層を
はさんで、SnO2/Cr2重電極が交互に積層され、
かつ全部または一部のSnO2電極は、その端部が素子
の端部に設けられた外部電極に接続されるか、あるいは
素子の端部に集められて、互いに接触しない3つ(以上
)の電極となる構造が提供された。
(m) As a result of the above, SnO2/Cr double electrodes are alternately stacked with dielectric layers made of TiO2 films in between,
and all or some of the SnO2 electrodes are connected at their ends to external electrodes provided at the ends of the element, or are assembled at the ends of the element to form three (or more) electrodes that do not touch each other. A structure was provided.

[実施例3〜7コ 実施例1において、工程(a)、(c)、(e)および
(g)で成膜されるSnO□/Cr2重電極膜、ならび
に工程(j)で用いられるCuペーストをそれぞれ第1
表のように変えた以外は実施例1と同様な操作を行って
積層型薄膜誘電体素子を作製した。
[Examples 3 to 7] In Example 1, the SnO□/Cr double electrode film formed in steps (a), (c), (e) and (g), and the Cu used in step (j) Paste each
A multilayer thin film dielectric element was manufactured by performing the same operations as in Example 1 except for the changes shown in the table.

(以下余白) 第  1  表 [実施例8〜12] 実施例2において、文中すべてのSnO2/Cr2重電
極膜、ならびに工程(j)で用いられるCuペーストを
それぞれ第2表のように変えた以外は実施例2と同様な
操作を行って積層型薄膜誘電体素子を作製した。
(Margin below) Table 1 [Examples 8 to 12] In Example 2, all the SnO2/Cr double electrode films and the Cu paste used in step (j) were changed as shown in Table 2. A laminated thin film dielectric element was manufactured by performing the same operation as in Example 2.

(以下余白) 第2表 序を示す模式断面図である。(Margin below) Table 2 FIG.

符号の説明 1・・・・ガラス基板 [発明の効果] 以上説明したように、本発明によれば、従来の積層セラ
ミックコンデンサと同様な構造を持ちながら、安価なガ
ラス基板を用いてその上に誘電体薄膜をはさんで内部電
極用薄膜が共に10血、好ましくは51uaよりも薄い
厚さで交互に積層された積層薄膜誘電体素子を提供する
ことができる。
Explanation of symbols 1...Glass substrate [Effects of the invention] As explained above, according to the present invention, although it has the same structure as a conventional multilayer ceramic capacitor, an inexpensive glass substrate is used and a It is possible to provide a laminated thin film dielectric element in which internal electrode thin films are alternately laminated with dielectric thin films sandwiched therebetween to a thickness of less than 10 mm, preferably less than 51 ua.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の積層薄膜誘電体素子の一実施例にお
ける成膜順序を示す模式断面図である。 第2図は、本発明の別の実施例における成膜順4・・・
・TiO2膜■ 5・・・・2重電極膜(り 6・・・・TiQ、膜(り 7・・・・2重電極膜■ 8・・・・TiO□膜■ 9・・・・2重電極膜に) 10・・・・TiO2膜に) 11・・・・2重電極膜■ 12・・・・TiO2膜■ 13・・・・2重電極膜(6) 20・・・・Cu端子電極 21・・・・Niメッキ層
FIG. 1 is a schematic cross-sectional view showing the sequence of film formation in one embodiment of the laminated thin film dielectric element of the present invention. FIG. 2 shows the film formation order 4 in another embodiment of the present invention.
・TiO2 film ■ 5...Double electrode film (ri6...TiQ, film (ri7...double electrode film■ 8...TiO□ film■ 9...2 (For heavy electrode film) 10...For TiO2 film) 11...Double electrode film■ 12...TiO2 film■ 13...Double electrode film (6) 20...Cu Terminal electrode 21...Ni plating layer

Claims (2)

【特許請求の範囲】[Claims] (1)ガラス基板上に、表面にSnO_2薄膜、裏面に
Cr、NiまたはCu薄膜を有する厚さ10μm以下の
2重電極膜と厚さ10μm以下のTiO_2誘電体膜と
が交互に積層された基本構造を持ち、前記複数層の2重
電極膜の内の一部または全部は、容量を取得するための
内部電極層として、互いに異なる導出端に接続された少
なくとも2群からなっていて、同じ群に属する2重電極
膜はそれぞれ同じ側端部に引き出され、該側端部に配置
または形成された、表面にNiメッキ層を有するCuま
たはNiの端子電極に接続されていることを特徴とする
積層型薄膜誘電体素子。
(1) A basic structure in which dual electrode films with a thickness of 10 μm or less and TiO_2 dielectric films with a thickness of 10 μm or less are alternately laminated on a glass substrate, with a SnO_2 thin film on the front surface and a Cr, Ni, or Cu thin film on the back surface. structure, and part or all of the plurality of layers of dual electrode films are composed of at least two groups connected to mutually different lead-out ends as internal electrode layers for obtaining capacitance, and the same group is connected to different lead-out ends. The dual electrode films belonging to the above are each drawn out to the same side end and are connected to a Cu or Ni terminal electrode having a Ni plating layer on the surface, which is arranged or formed on the side end. Laminated thin film dielectric element.
(2)(イ)ガラス基板上にCVD法により所定の形状
と面積をもつ厚さ10μm以下のSnO_2/(Cr、
NiまたはCu)2重電極膜(表面にSnO_2薄膜、
裏面にCr、NiまたはCu薄膜を有する2重電極膜)
を形成し、不要な部分をウェットエッチングにより除去
して第1のSnO_2/(Cr、NiまたはCu)2重
電極膜(1)とし; (ロ)このSnO_2/(Cr、NiまたはCu)2重
電極膜(1)の上にCVD法により、下地SnO_2膜
に対してエピタキシャル成長させて厚さ10μm以下の
TiO_2誘電体膜を形成し、不要な部分をドライエッ
チング法で除去して第1のTiO_2膜(1)とし; (ハ)上記TiO_2膜(1)の上にCVD法によりエ
ピタキシャル成長させて厚さ10μm以下のSnO_2
/(Cr、NiまたはCu)2重電極膜を形成し、不要
な部分をウェットエッチングにより除去して第2のSn
O_2/(Cr、NiまたはCu)2重電極膜(2)と
し; (ニ)上記SnO_2/(Cr、NiまたはCu)2重
電極膜(2)の上に(ロ)と同じ要領で第2のTiO_
2膜(2)を形成し、 上記(イ)〜(ニ)の全部または一部を繰り返した後、
積層体の側端部を一部切断除去して複数の2重電極膜の
端部が切断面に現われるようにし、該切断面に表面にN
iメッキ層を有するCuまたはNiの端子電極を形成す
ることからなる下記の誘電体素子、すなわち、ガラス基
板上に、表面にSnO_2薄膜、裏面にCr、Niまた
はCu薄膜を有する厚さ10μm以下の2重電極膜と厚
さ10μm以下のTiO_2誘電体膜とが交互に積層さ
れた基本構造を持ち、前記複数層の2重電極膜の内の一
部または全部は、容量を取得するための内部電極層とし
て、互いに異なる導出端に接続された少なくとも2群か
らなっていて、同じ群に属する2重電極膜はそれぞれ同
じ側端部に引き出され、該側端部に配置または形成され
た、表面にNiメッキ層を有するCuまたはNiの端子
電極に接続されていることを特徴とする積層型薄膜誘電
体素子の製造方法。
(2) (a) SnO_2/(Cr with a thickness of 10 μm or less with a predetermined shape and area by CVD method on a glass substrate,
Ni or Cu) double electrode film (SnO_2 thin film on the surface,
(Double electrode film with Cr, Ni or Cu thin film on the back side)
and remove unnecessary portions by wet etching to form a first SnO_2/(Cr, Ni or Cu) double electrode film (1); (b) this SnO_2/(Cr, Ni or Cu) double electrode film (1); On the electrode film (1), a TiO_2 dielectric film with a thickness of 10 μm or less is formed by epitaxially growing the base SnO_2 film using the CVD method, and unnecessary portions are removed by dry etching to form the first TiO_2 film. (1); (c) SnO_2 with a thickness of 10 μm or less is epitaxially grown on the TiO_2 film (1) by CVD method.
/(Cr, Ni or Cu) double electrode film is formed and unnecessary parts are removed by wet etching to form a second Sn
O_2/(Cr, Ni or Cu) double electrode film (2); (d) On top of the SnO_2/(Cr, Ni or Cu) double electrode film (2), a second layer is formed in the same manner as in (b). of TiO_
After forming two films (2) and repeating all or part of the above (a) to (d),
A portion of the side edges of the laminate is cut and removed so that the ends of the plurality of double electrode films appear on the cut surface, and N is applied to the surface of the cut surface.
The following dielectric element consists of forming a Cu or Ni terminal electrode with an i-plated layer, i.e., a glass substrate with a thickness of 10 μm or less having a SnO_2 thin film on the front surface and a Cr, Ni or Cu thin film on the back surface. It has a basic structure in which double electrode films and TiO_2 dielectric films with a thickness of 10 μm or less are laminated alternately, and a part or all of the plurality of layers of double electrode films are used as internal layers for obtaining capacitance. The electrode layer consists of at least two groups connected to different lead-out ends, and the double electrode films belonging to the same group are each drawn out to the same side edge, and the surface arranged or formed on the side edge. A method for manufacturing a laminated thin film dielectric element, characterized in that the element is connected to a Cu or Ni terminal electrode having a Ni plating layer.
JP33978489A 1989-12-27 1989-12-27 Laminated thin-film dielectric element and manufacture thereof Pending JPH03200310A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33978489A JPH03200310A (en) 1989-12-27 1989-12-27 Laminated thin-film dielectric element and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33978489A JPH03200310A (en) 1989-12-27 1989-12-27 Laminated thin-film dielectric element and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH03200310A true JPH03200310A (en) 1991-09-02

Family

ID=18330778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33978489A Pending JPH03200310A (en) 1989-12-27 1989-12-27 Laminated thin-film dielectric element and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH03200310A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014024538A1 (en) * 2012-08-07 2014-02-13 株式会社村田製作所 Laminated ceramic capacitor and production method for laminated ceramic capacitor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014024538A1 (en) * 2012-08-07 2014-02-13 株式会社村田製作所 Laminated ceramic capacitor and production method for laminated ceramic capacitor
CN104508771A (en) * 2012-08-07 2015-04-08 株式会社村田制作所 Laminated ceramic capacitor and production method for laminated ceramic capacitor
JP5892252B2 (en) * 2012-08-07 2016-03-23 株式会社村田製作所 Multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor
US9728333B2 (en) 2012-08-07 2017-08-08 Murata Manufacturing Co., Ltd. Method for manufacturing a ceramic laminated body
US10121591B2 (en) 2012-08-07 2018-11-06 Murata Manufacturing Co., Ltd. Laminated ceramic capacitor and method for manufacturing laminated ceramic capacitor

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