JPH03200309A - Laminated thin-film dielectric element and manufacture thereof - Google Patents

Laminated thin-film dielectric element and manufacture thereof

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Publication number
JPH03200309A
JPH03200309A JP33978389A JP33978389A JPH03200309A JP H03200309 A JPH03200309 A JP H03200309A JP 33978389 A JP33978389 A JP 33978389A JP 33978389 A JP33978389 A JP 33978389A JP H03200309 A JPH03200309 A JP H03200309A
Authority
JP
Japan
Prior art keywords
film
thickness
thin film
films
sno
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33978389A
Other languages
Japanese (ja)
Inventor
Tetsuya Urano
浦野 哲也
Masayuki Fujimoto
正之 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP33978389A priority Critical patent/JPH03200309A/en
Publication of JPH03200309A publication Critical patent/JPH03200309A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To enable forming the title dielectric element according to a thin film thickness by forming double electrode films having SnO2 thin film on the surface and Cr, Ni or Cu thin film on the rear surface and further TiO2 dielectric thin films through causing these films to make an epitaxial growth respectively by means of vapor deposition and by laminating these two sorts of films alternately. CONSTITUTION:The title dielectric element has a fundamental structure, in which double electrode films 2, 3 which the thickness of 10mum and less having SnO2 thin film 3 on the front and Cr, Ni or Cu thin film 2 on the rear and TiO2 dielectric films 4 with the thickness of 10mum and less are alternately laminated on a glass substrate 1. In this case, a part or the whole of plural SnO2/(Cr, Ni or Cu) double electrode films 2, 3, 5, 7 and 9, as internal electrode layers for obtaining capacity, is composed of at least two groups connected with lead-out ends differing from each other. Thus, a low-cost glass substrate 1 is used so that internal electrode thin films can alternately be laminated on the glass substrate according to a thin thickness while holding dielectric thin films 4, 6 and 8 between them.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、積層構造を有する薄膜誘電体素子およびそ
の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film dielectric element having a laminated structure and a method for manufacturing the same.

[従来の技術] 従来、小型かつ大容量を有する誘電体素子としてセラミ
ック積層体コンデンサが多用されており、リード線のな
いチップ型積層コンデンサでは、薄い誘電体セラミック
ス層をはさんで、容量を取得するための内部電極層が交
互に対向しで積層されていて、その内部電極末端部は直
接半田付は可能な外部端子電極に接続されている。
[Conventional technology] Conventionally, ceramic multilayer capacitors have been widely used as dielectric elements with small size and large capacity.In chip-type multilayer capacitors without lead wires, capacitance is obtained by sandwiching thin dielectric ceramic layers. Internal electrode layers are alternately stacked to face each other, and the terminal ends of the internal electrodes are connected to external terminal electrodes that can be directly soldered.

この積層型コンデンサにおいて素子の取得容量を上げる
ために通常、誘電体層1層あたりの厚さを薄くすること
が試みられている。しかし積層セラミックコンデンサの
場合、厚さ1O1t1a以下のセラミックス誘電体層を
実現しようとすると、薄いグリーンシートの作成、電極
ペーストのシートアタック、圧着成形、焼成後の誘電体
粒子の粒径コントロールなど多くの困難な技術的課題が
あり、現状では、誘電体層厚511!mを切るセラミッ
ク積層コンデンサは公表されていない。
In order to increase the acquisition capacity of the element in this multilayer capacitor, attempts are usually made to reduce the thickness of each dielectric layer. However, in the case of multilayer ceramic capacitors, in order to realize a ceramic dielectric layer with a thickness of 101t1a or less, there are many steps such as creating a thin green sheet, sheet attack of electrode paste, pressure molding, and controlling the particle size of dielectric particles after firing. Due to difficult technical issues, the current dielectric layer thickness is 511! Ceramic multilayer capacitors with a diameter of less than m have not been announced.

一方、蒸着、スパッタリングなどの蒸着技術を用いて、
高い静電容量を有する薄膜コンデンサを作製する試みも
なされているが、高い静電容量の取得が期待できるチタ
ン酸バリウム、鉛系ペロブスカイトなど強誘電体材料系
薄膜では、キュリー点通過時の結晶相転移による歪の問
題から良質の誘電体薄膜は得られていない。またこの結
晶相転移時に発生する歪の問題を回避するためには下地
基板からエピタキシャル成長させる方法もあるが、下地
基板が高価な単結晶(例えばSrTiO3、ptなど)
に限られてしまうため、実用化の目途は立っていない。
On the other hand, using vapor deposition techniques such as vapor deposition and sputtering,
Attempts have been made to fabricate thin film capacitors with high capacitance, but thin films based on ferroelectric materials such as barium titanate and lead-based perovskite, which can be expected to obtain high capacitance, have a crystalline phase when passing the Curie point. Good quality dielectric thin films have not been obtained due to the problem of distortion caused by dislocation. In addition, in order to avoid the problem of distortion that occurs during this crystal phase transition, there is a method of epitaxial growth from a base substrate, but the base substrate is made of an expensive single crystal (for example, SrTiO3, PT, etc.).
Since it is limited to , there is no prospect of practical application.

[発明が解決しようとする課題] 前述のように、積層セラミックコンデンサの一層の小型
化に対する要望に対して種々検討されているにもかかわ
らず、誘電体の膜厚が5伽を下回るような製品はまた実
用化されておらず、また蒸着を用いた薄膜コンデンサで
も前述のような欠点があった。したがって、良質な誘電
体膜を10m、好ましくは5血を下回る厚さで、低コス
トかつ簡便に積層化する技術がなかった。
[Problems to be Solved by the Invention] As mentioned above, despite various studies being conducted to meet the demand for further miniaturization of multilayer ceramic capacitors, products with a dielectric film thickness of less than 5 mm have been developed. has not been put into practical use, and even thin film capacitors using vapor deposition have the drawbacks mentioned above. Therefore, there has been no technology for simply laminating high-quality dielectric films at a thickness of less than 10 m, preferably less than 5 m, at low cost.

本発明の目的は、高価な単結晶基板を用いないで、膜厚
が10μm1好ましくは5umを下回る誘電体薄膜で形
成した積層型薄膜誘電体素子を提供することにある。
An object of the present invention is to provide a multilayer thin film dielectric element formed of a dielectric thin film having a thickness of less than 10 μm, preferably less than 5 μm, without using an expensive single crystal substrate.

[課題を解決するための手段および作用]本発明者等は
上記目的を達成すべく研究の結果、安価なガラス基板を
用い、その上に蒸着法で表面にS n O2薄膜、裏面
にCr5NiまたはCu薄膜を有する2重電極膜(以下
5nOz/(Cr、NiまたはCu)2重電極膜と略記
する)を、さらにT i O2誘電体薄膜をそれぞれエ
ピタキシャル成長させて形成し、これら2種の膜を交互
に積層させることによって従来の積層セラミックコンデ
ンサと同様な構造をもち、しかも膜厚がLOuss好ま
しくは5血よりも薄く約1血をも可能とする積層型薄膜
誘電体素子が得られることを見い出し本発明に到達した
[Means and effects for solving the problem] In order to achieve the above object, the inventors of the present invention have conducted research using an inexpensive glass substrate, and deposited a thin film of SnO2 on the surface and a Cr5Ni or Cr5Ni film on the back surface using an evaporation method. A double electrode film (hereinafter abbreviated as 5nOz/(Cr, Ni or Cu) double electrode film) having a Cu thin film was formed by epitaxially growing a TiO2 dielectric thin film, and these two types of films were It has been discovered that by alternately laminating layers, it is possible to obtain a laminated thin film dielectric element having a structure similar to that of a conventional laminated ceramic capacitor, and having a film thickness preferably thinner than 5 LOss, but even about 1 LOuss. We have arrived at the present invention.

すなわち、本発明は第一に下記の如き積層型薄膜誘電体
素子を提供するものである。
That is, the present invention first provides a laminated thin film dielectric element as described below.

ガラス基板上に、表面にSnO2薄膜、裏面にCr、N
iまたはCu薄膜を有する厚さ1ou−以下、好ましく
は5血以下の2重電極膜と厚さ10(至)以下、好まし
くは5血以下のTiO2誘電体膜とが交互に積層された
基本構造を持ち、前記複数のSnO2/(CrSNiま
たはCu)2重電極膜の内の一部または全部は、容量を
取得するための内部電極層として、互いに異なる導出端
に接続された少なくとも2群からなっていることを特徴
とする積層型薄膜誘電体素子。
On the glass substrate, SnO2 thin film on the front surface, Cr and N on the back surface.
A basic structure in which dual electrode films with a thickness of 1 or less, preferably 5 or less, and a TiO2 dielectric film with a thickness of 10 or less, preferably 5 or less, having a thin Cu or Cu thin film are laminated alternately. and some or all of the plurality of SnO2/(CrSNi or Cu) double electrode films are composed of at least two groups connected to mutually different lead-out ends as internal electrode layers for obtaining capacitance. A multilayer thin film dielectric element characterized by:

本発明は第二に、下記の如き積層型薄膜誘電体素子の製
造方法を提供するものである。
Second, the present invention provides a method of manufacturing a laminated thin film dielectric element as described below.

(イ)ガラス基板上にCVD法により所定の形状と面積
をもつ厚さ1OI11n以下、好ましくは57ZII+
以下のSnO2/ (Cr、NiまたはCu)2重電極
膜(表面にSnO2薄膜、裏面にCr5NiまたはCu
薄膜を有する2重電極膜)を形成し、不要な部分をウェ
ットエツチングにより除去して第1のSnO2/ (C
r、NiまたはCu)2重電極膜(Dとし; (ロ)このSnO2/ (Cr、NiまたはCu)2重
電極膜(1)の上にCVD法により、下地SnO□膜に
対してエピタキシャル成長させて厚さ10血以下、好ま
しくは5μm以下のTiO□誘電体膜を形成し、不要な
部分をドライエツチング法で除去して第1のTiO2膜
(1)とし;(ハ)上記T i O2膜(Dの上にCV
D法によりエピタキシャル成長させて厚さlOZ/ff
1以下、好ましくは5膜m以下のS n 02 / (
CrSN iまたはCu)2重電極膜を形成し、不要な
部分をウェットエツチングにより除去して第2のS n
 02 / (Cr。
(a) A glass substrate with a thickness of 1OI11n or less, preferably 57ZII+, having a predetermined shape and area by CVD method.
The following SnO2/ (Cr, Ni or Cu) double electrode film (SnO2 thin film on the surface, Cr5Ni or Cu on the back side)
A first SnO2/(C
(r, Ni or Cu) dual electrode film (r) (r) Double electrode film (D); to form a TiO□ dielectric film with a thickness of 10 μm or less, preferably 5 μm or less, and remove unnecessary portions by dry etching to form a first TiO2 film (1); (c) the above TiO2 film; (CV on top of D
Epitaxially grown using the D method to a thickness of lOZ/ff
S n 02 / (
CrSN i or Cu) double electrode film is formed, unnecessary portions are removed by wet etching, and the second Sn
02/(Cr.

NiまたはCu)2重電極膜(■とし;(ニ)上記S 
n 02 / (Cr、NiまたはCu)2重電極膜(
りの上に(ロ)と同じ要領で第2のTiO2膜(りを形
成し、 上記(イ)〜(ニ)の全部または一部を繰り返すことか
らなる下記の誘電体素子、すなわち、ガラス基板上に、
表面にSnO2薄膜、裏面にCr。
Ni or Cu) double electrode film (■); (d) above S
n 02 / (Cr, Ni or Cu) double electrode film (
A second TiO2 film is formed on the substrate in the same manner as in (b), and all or a part of the above (a) to (d) are repeated to form the following dielectric element, that is, a glass substrate. above,
SnO2 thin film on the front surface, Cr on the back surface.

NiまたはCu薄膜を有する厚さ10w以下、好ましく
は5uItl以下の2重電極膜と厚さ101!ja以下
のTiO2誘電体膜とが交互に積層された基本構造を持
ち、前記複数のSnO2/ (CrSNiまたはCu)
2重電極膜の内の一部または全部は、容量を取得するた
めの内部電極層として、互いに異なる導出端に接続され
た少なくとも2群からなっていることを特徴とする積層
型薄膜誘電体素子の製造方法。
A double electrode film with a thickness of 10W or less, preferably 5uItl or less, with a Ni or Cu thin film and a thickness of 101! It has a basic structure in which TiO2 dielectric films of ja or less are laminated alternately, and the plurality of SnO2/
A laminated thin film dielectric element characterized in that part or all of the double electrode film is composed of at least two groups connected to different lead-out ends as internal electrode layers for obtaining capacitance. manufacturing method.

第1図は本発明の積層型薄膜誘電体素子製造における成
膜順序を示す模式断面図であって、同図(g)に示され
るように、ガラス基板1上に表面がSnO□膜で裏面が
Cr膜からなる2重電極膜および誘電体T i 02膜
が交互に積層され、外部端子として2重電極膜を引き出
した構造であって、従来の積層セラミックコンデンサと
実質上同様の構造を有している。またガラス基板または
誘電体膜との密着を良好にするため、電極膜の裏面には
C「膜を配し2重構造とした。したがって、安価なガラ
ス基板を用いて、低コストかつ簡便に10zon、好ま
しくは5如より薄い誘電体膜を持つ積層薄膜誘電体素子
を提供することができる。
FIG. 1 is a schematic cross-sectional view showing the film forming order in manufacturing a laminated thin film dielectric element of the present invention. As shown in FIG. It has a structure in which a double electrode film made of Cr film and a dielectric TiO2 film are alternately laminated, and the double electrode film is drawn out as an external terminal, and has substantially the same structure as a conventional multilayer ceramic capacitor. are doing. In addition, in order to improve adhesion to the glass substrate or dielectric film, a C film is placed on the back side of the electrode film to create a double structure. It is possible to provide a laminated thin film dielectric element having a dielectric film thinner than, preferably, 5 or more.

以下実施例により本発明をさらに説明する。The present invention will be further explained below with reference to Examples.

[実施例1] 前述の第1図(a)〜(g)に従って、本発明の積層薄
膜誘電体素子の作成順序を説明する。
[Example 1] The order of fabrication of the laminated thin film dielectric element of the present invention will be explained according to the above-mentioned FIGS. 1(a) to 1(g).

(a)ホウケイ酸ガラス基板(コーニング社製#705
9) 1上に上下層にそれぞれSnO2膜3とCr膜2
とを有してなり各膜厚が0.5μmの2重膜を形成し、
この2重膜の片側端部をウェットエツチングにより除去
して5膜02/Cr2重電極膜(1)とした。
(a) Borosilicate glass substrate (Corning #705
9) SnO2 film 3 and Cr film 2 are placed on top and bottom of 1, respectively.
to form a double film each having a thickness of 0.5 μm,
One end of this double film was removed by wet etching to obtain a 5 film 02/Cr double electrode film (1).

(b)この2重電極膜■にCVD法によりTiO2膜4
を下地SnO2膜に対してエピタキシャル成長により、
1μmの膜厚で形成し、このTiO2膜の両側の端部を
ドライエツチングにより除去してTiO2膜(1)とし
た。
(b) TiO2 film 4 is applied to this double electrode film 4 by CVD method.
By epitaxial growth on the underlying SnO2 film,
A TiO2 film (1) was formed by forming a film with a thickness of 1 μm, and removing both end portions of this TiO2 film by dry etching.

(c)このTiO2膜■に上述のようなSnO2/C「
2重電極膜5を各膜厚0.5血で成膜し、片側端部をウ
ェットエツチングにより除去して2重電極膜■とした。
(c) This TiO2 film ■ has SnO2/C as described above.
A double electrode film 5 was formed with a thickness of 0.5 mm each, and one end was removed by wet etching to obtain a double electrode film (2).

(d)次に、CVD法によりT i O2膜6を下地S
nO2膜に対してエピタキシャル成長により1血の膜厚
で形成し、両端を同図(d)のようにドライエツチング
により除去してTiO2膜(りとした。このとき、Ti
O2膜(りはTiO2膜■と直接に接合して2重電極膜
(0の片側端部を覆うような形状となる。
(d) Next, the TiO2 film 6 is deposited on the base layer S by the CVD method.
The nO2 film is epitaxially grown to a thickness of one layer, and both ends are removed by dry etching as shown in the figure (d) to form a TiO2 film.
The O2 film (2) is directly bonded to the TiO2 film (2) to form a shape that covers one end of the double electrode film (0).

(e)さらにT i O2膜(りに前述のようなSnO
2/Cr2重電極膜(各膜厚0.5IIM) 7を形成
し、片側端部をウェットエツチングにより除去して2重
電極膜G)とした。この結果、2重電極膜(1)の片側
端部と2重電極膜■とが直接接触した構造となる。
(e) Furthermore, a TiO2 film (SnO as mentioned above)
A 2/Cr double electrode film (each film thickness 0.5IIM) 7 was formed, and one end was removed by wet etching to obtain a double electrode film G). As a result, a structure is obtained in which one end of the double electrode film (1) and the double electrode film (2) are in direct contact.

(f)さらにCVD法によりTiO2膜8を下地SnO
2膜に対してエピタキシャル成長によりIIIMの膜厚
で形成し、このTiO2膜の両側をドレイエツチングに
より除去してTiO2膜■とした。このとき、TiO2
膜O)はTiO2膜(りと直接に接合して2重電極膜G
)の片側端部を覆うような形状となる。
(f) Furthermore, the TiO2 film 8 is coated with SnO as an underlayer by CVD method.
Two films were formed with a thickness of IIIM by epitaxial growth, and both sides of this TiO2 film were removed by dry etching to form a TiO2 film (2). At this time, TiO2
The film O) is directly bonded to the TiO2 film (G) to form a double electrode film G.
) is shaped to cover one end of the

(g)以上の工程から得られた積層膜上に、前述のよう
なSnO2/Cr2重電極膜(各膜厚0.5 M) 9
を形成し、片側端部をウェットエツチングにより除去し
て2重電極膜に)とした。
(g) On the laminated film obtained from the above steps, the SnO2/Cr double electrode film (each film thickness 0.5 M) as described above was applied.
was formed, and one end was removed by wet etching to form a double electrode film).

(h)上記(a)〜(g)の工程を繰り返すことで、T
 i 02誘電体膜をはさんで、SnO2/Cr2重電
極膜が交互にそれぞれ端部の電極に接続された、実質上
従来の積層セラミックコンデンサと同様の構造をもつ積
層型薄膜誘電体素子が形成される。
(h) By repeating the steps (a) to (g) above, T
A multilayer thin film dielectric element with substantially the same structure as a conventional multilayer ceramic capacitor is formed, in which SnO2/Cr dual electrode films are alternately connected to end electrodes with i02 dielectric films in between. be done.

同方法により、同一積層数で比較した場合、最も高い静
電気容量を得ることができる。
By this method, the highest electrostatic capacitance can be obtained when comparing the same number of laminated layers.

[実施例2] 第2図(a)〜(k)に従って、本発明の積層薄膜誘電
体素子の作成順序を説明する。
[Example 2] The order of manufacturing a laminated thin film dielectric element of the present invention will be explained with reference to FIGS. 2(a) to (k).

(a)ホウケイ酸ガラス基板(コーニング社製#705
9) 1上に上下層にそれぞれSnO2膜3とCr膜2
とを有してなり各膜厚が0.5−の2重膜を形成し、こ
の2重膜の両側端部をウェットエツチングにより除去し
てS n 02 / Cr 2重電極膜q)とした。
(a) Borosilicate glass substrate (Corning #705
9) SnO2 film 3 and Cr film 2 are placed on top and bottom of 1, respectively.
A double film having a thickness of 0.5-2 was formed, and both ends of this double film were removed by wet etching to form a Sn 02 /Cr double electrode film q). .

(b)この2重電極膜■にCVD法によりTiO□膜4
を下地SnO,膜に対してエピタキシャル成長により、
1血の膜厚で形成し、このTiO□膜の両側の端部゛を
ドライエツチングにより除去してTiO2膜(1)とし
た。
(b) TiO□ film 4 is applied to this double electrode film ② by CVD method.
By epitaxial growth on the underlying SnO film,
A TiO 2 film (1) was formed by dry etching to remove both ends of this TiO□ film.

(c)このT i O,膜■に上述のようなSnO2膜
 Cr 2重電極膜5を各膜厚0.5血で成膜し、片側
端部をウェットエツチングにより除去して2重電極膜(
つとした。
(c) A SnO2 film and a Cr double electrode film 5 as described above are formed on this TiO film 5 with a thickness of 0.5 mm each, and one end is removed by wet etching to form a double electrode film. (
It was.

(d)次1:、CV D 法1: ヨリT i O2I
t! 6を下地S n O2膜に対してエピタキシャル
成長により1血の膜厚で形成し、両端を同図(d)のよ
うにドライエツチングにより除去してTiO2膜(つと
した。このとき、TiO2膜(■はTiO2膜■と直接
に接合して2重電極膜(りの片側端部を覆うような形状
となる。
(d) Next 1:, CV D Method 1: T i O2I
T! 6 was epitaxially grown on the underlying S n O2 film to a thickness of one layer, and both ends were removed by dry etching as shown in the figure (d) to form a TiO2 film. is directly bonded to the TiO2 film (2) and has a shape that covers one end of the double electrode film (2).

(e)さらにTiO2膜(りに前述のようなSnO2/
Cr2重電極膜(各膜厚0.5nm) 7を形成し、片
側端部をウェットエツチングにより除去して2重電極膜
■とした。
(e) Furthermore, a TiO2 film (SnO2/
A Cr double electrode film (each film thickness: 0.5 nm) 7 was formed, and one end portion was removed by wet etching to obtain a double electrode film (2).

(f)さらにCVD法によりTiO2膜8を下地SnO
2膜に対してエピタキシャル成長により1血の膜厚で形
成し、このTiO2膜の両側をドライエツチングにより
除去して、T io 2膜■とした。このとき、TiO
2膜■はTiO2膜(つと直接に接合して2重電極膜■
の片側端部を覆うような形状となる。
(f) Furthermore, the TiO2 film 8 is coated with SnO as an underlayer by CVD method.
A TiO2 film was formed with a thickness of one layer by epitaxial growth, and both sides of this TiO2 film were removed by dry etching to obtain a TiO2 film. At this time, TiO
The two films ■ are the TiO2 films (which are directly bonded to the double electrode films ■
It has a shape that covers one end of the.

(g)以上の工程から得られた積層膜上に、前述のよう
なSnO2/Cr2重電極膜(各膜厚0.5 &) 9
を形成し、片側端部をウェットエツチングにより除去し
て2重電極膜に)とした。この結果、2重電極膜(わの
片側端部と、2重電極膜に)が直接、接触した構造とな
る。
(g) On the laminated film obtained from the above steps, the SnO2/Cr double electrode film (each film thickness 0.5 &) as described above is applied.
was formed, and one end was removed by wet etching to form a double electrode film). As a result, a structure is obtained in which the double electrode film (one end of the wire and the double electrode film) is in direct contact.

(h)さら+、:、 CV D法ニヨリT i 02膜
10を下地SnO2膜に対してエピタキシャル成長によ
りlumの膜厚で形成し、このT i O2膜の両側を
ドライエツチングにより除去して、TiO2膜に)とし
た。このとき、TiO□膜に)はTiO2膜■と直接に
接合して2重電極膜に)の片側端部を覆うような形状と
なる。
(h) CVD method Niori TiO2 film 10 is formed to a thickness of lum by epitaxial growth on the underlying SnO2 film, and both sides of this TiO2 film are removed by dry etching to form a TiO2 film. (to the membrane). At this time, the TiO □ film) is directly joined to the TiO 2 film ■, forming a shape that covers one end of the dual electrode film).

(i)以上の工程から得られた積層膜上に、前述のよう
なSnO2/Cr2重電極膜(各膜厚0.5 nm) 
IIを形成し、片側端部をウェットエツチングにより除
去して2重電極膜6)とした。この結果、2重電極膜■
の片側端部と、2重電極膜■が直接、接触した構造とな
る。
(i) On the laminated film obtained from the above steps, the SnO2/Cr double electrode film (each film thickness 0.5 nm) as described above is applied.
II was formed, and one end was removed by wet etching to obtain a double electrode film 6). As a result, the double electrode film■
The structure is such that one end of the double electrode film (1) is in direct contact with the double electrode film (2).

(j) さら+Z CV D法ニヨリTiO2膜12を
下地SnO2膜に対してエピタキシャル成長により1如
の膜厚で形成し、このTiO□膜の両側をドライエツチ
ングにより除去して、TiO2膜■とした。このとき、
TiO2膜■はT i 02膜(イ)と直接に接合して
2重電極膜■の片側端部を覆うような形状となる。
(j) Further+Z CVD method Niori TiO2 film 12 was formed on the base SnO2 film by epitaxial growth to a certain thickness, and both sides of this TiO□ film were removed by dry etching to form a TiO2 film ■. At this time,
The TiO2 film (2) is directly bonded to the Ti02 film (A) and has a shape that covers one end of the double electrode film (2).

これに続き必要に応じて、(aSb)、(CSd)、(
e、f)(あるいはgSh)(あるいはL j)の操作
の全部または一部を繰り返すことができるが、ここでは
省略する。
Following this, (aSb), (CSd), (
All or part of the operations e, f) (or gSh) (or L j) can be repeated, but are omitted here.

(k)以上の工程から得られた積層膜上に、前述のよう
なSnO2/Cr2重電極膜(各膜厚0.5 M) 1
3を形成し、両側端部をウェットエツチングにより除去
して2重電極膜(6)とした。この結果、該SnO2/
Cr2重電極膜は、両側の端子電極から独立した第3の
電極となる。
(k) On the laminated film obtained from the above steps, the SnO2/Cr double electrode film (each film thickness 0.5 M) as described above was added 1
3 was formed, and both end portions were removed by wet etching to obtain a double electrode film (6). As a result, the SnO2/
The Cr double electrode film becomes a third electrode independent from the terminal electrodes on both sides.

以上の結果、TiO2膜からなる誘電体層をはさんで、
S n O2/ Cr 2重電極が交互に積層され、か
つ全部または一部のSnO2電極は、その端部が素子の
端部に集められて、互いに接触しない3つ(以上)の電
極となる構造が提供された。
As a result of the above, with a dielectric layer made of TiO2 film in between,
A structure in which SnO2/Cr double electrodes are alternately stacked, and all or some of the SnO2 electrodes have their ends gathered at the ends of the element, resulting in three (or more) electrodes that do not touch each other. was provided.

[実施例3.4] 実施例1の工程、(a)、(c)、(e)、(g)、(
h)においてCr/SnO22重電極膜を、第1表のよ
うに変えた以外はすべて実施例1と同じ方法で行った。
[Example 3.4] Steps of Example 1, (a), (c), (e), (g), (
In h), all the steps were the same as in Example 1 except that the Cr/SnO2 double electrode film was changed as shown in Table 1.

[実施例5.6] 実施例2の(a)、(c)、(e)、(g)、(i)、
(k)l:おいて01750022重電極膜を、第1表
のように変えた以外はすべて実施例1と同じ方法で行っ
た。
[Example 5.6] (a), (c), (e), (g), (i) of Example 2,
(k)l: The same method as in Example 1 was repeated except that the 01750022 double electrode film was changed as shown in Table 1.

第1表 [発明の効果] 以上説明したように、本発明によれば、従来の積層セラ
ミックコンデンサと同様な構造を持ちながら、安価なガ
ラス基板を用いてその上に誘電体薄膜をはさんで内部電
極薄膜が共に10血、好ましくは5111mよりも薄い
厚さで交互に積層された積層薄膜誘電体素子を提供する
ことができる。
Table 1 [Effects of the Invention] As explained above, according to the present invention, although the structure is similar to that of a conventional multilayer ceramic capacitor, an inexpensive glass substrate is used and a dielectric thin film is sandwiched thereon. It is possible to provide a laminated thin film dielectric element in which internal electrode thin films are alternately laminated with a thickness of less than 10 m, preferably less than 5111 m.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の積層型薄膜誘電体素子の一実施例に
おける成膜順序を示す模式断面図である。 第2図は、本発明の別の実施例における成膜順序を示す
模式断面図である。 符号の説明 1・・・・ガラス基板 7・・・・2重電極膜(り 8・・・・TiO2膜(3) 9・・・・2重電極膜に) 10・・・・TiO2膜に) 11・・・・2重電極膜■ 12・・・・TiO2膜■ 13・・・・2重電極膜(6)
FIG. 1 is a schematic cross-sectional view showing the sequence of film formation in an embodiment of the multilayer thin film dielectric element of the present invention. FIG. 2 is a schematic cross-sectional view showing the sequence of film formation in another embodiment of the present invention. Explanation of symbols 1... Glass substrate 7... Double electrode film (ri 8... TiO2 film (3) 9... Double electrode film) 10... TiO2 film ) 11...Double electrode film■ 12...TiO2 film■ 13...Double electrode film (6)

Claims (2)

【特許請求の範囲】[Claims] (1)ガラス基板上に、表面にSnO_2薄膜、裏面に
Cr、NiまたはCu薄膜を有する厚さ10μm以下の
2重電極膜と厚さ10μm以下のTiO_2誘電体膜と
が交互に積層された基本構造を持ち、前記複数のSnO
_2/(Cr、NiまたはCu)2重電極膜の内の一部
または全部は、容量を取得するための内部電極層として
、互いに異なる導出端に接続された少なくとも2群から
なっていることを特徴とする積層型薄膜誘電体素子。
(1) A basic structure in which dual electrode films with a thickness of 10 μm or less and TiO_2 dielectric films with a thickness of 10 μm or less are alternately laminated on a glass substrate, with a SnO_2 thin film on the front surface and a Cr, Ni, or Cu thin film on the back surface. structure, the plurality of SnO
Part or all of the _2/(Cr, Ni or Cu) double electrode film is composed of at least two groups connected to different lead-out ends as internal electrode layers for obtaining capacitance. Characteristic multilayer thin film dielectric elements.
(2)(イ)ガラス基板上にCVD法により所定の形状
と面積をもつ厚さ10μm以下のSnO_2/(Cr、
NiまたはCu)2重電極膜(表面にSnO_2薄膜、
裏面にCr、NiまたはCu薄膜を有する2重電極膜)
を形成し、不要な部分をウェットエッチングにより除去
して第1のSnO_2 /(Cr、NiまたはCu)2
重電極膜(1)とし; (ロ)このSnO_2/(Cr、NiまたはCu)2重
電極膜(1)の上にCVD法により、下地SnO_2膜
に対してエピタキシャル成長させて厚さ10μm以下の
TiO_2誘電体膜を形成し、不要な部分をドライエッ
チング法で除去して第1のTiO_2膜(1)とし; (ハ)上記TiO_2膜(1)の上にCVD法によりエ
ピタキシャル成長させて厚さ10μm以下のSnO_2
 /(Cr、NiまたはCu)2重電極膜を形成し、不
要な部分をウェットエッチングにより除去して第2のS
nO_2/(Cr、NiまたはCu)2重電極膜(2)
とし; (ニ)上記SnO_2 /(Cr、NiまたはCu)2
重電極膜(2)の上に(ロ)と同じ要領で第2のTiO
_2膜(2)を形成し、 上記(イ)〜(ニ)の全部または一部を繰り返すことか
らなる下記の誘電体素子、すなわち、ガラス基板上に、
表面にSnO_2薄膜、裏面にCr、NiまたはCu薄
膜を有する厚さ10μm以下の2重電極膜と厚さ10μ
m以下のTiO_2誘電体膜とが交互に積層された基本
構造を持ち、前記複数のSnO_2/(Cr、Niまた
はCu)2重電極膜の内の一部または全部は、容量を取
得するための内部電極層として、互いに異なる導出端に
接続された少なくとも2群からなっていることを特徴と
する積層型薄膜誘電体素子の製造方法。
(2) (a) SnO_2/(Cr with a thickness of 10 μm or less with a predetermined shape and area by CVD method on a glass substrate,
Ni or Cu) double electrode film (SnO_2 thin film on the surface,
(Double electrode film with Cr, Ni or Cu thin film on the back side)
and remove unnecessary portions by wet etching to form a first SnO_2/(Cr, Ni or Cu)2
As a heavy electrode film (1); (b) TiO_2 with a thickness of 10 μm or less is epitaxially grown on the SnO_2 base film by the CVD method on this SnO_2/(Cr, Ni or Cu) double electrode film (1). A dielectric film is formed and unnecessary portions are removed by dry etching to obtain a first TiO_2 film (1); (c) Epitaxial growth is performed on the TiO_2 film (1) by CVD to a thickness of 10 μm or less. SnO_2
/(Cr, Ni or Cu) double electrode film is formed, unnecessary parts are removed by wet etching, and the second S
nO_2/(Cr, Ni or Cu) double electrode film (2)
(d) The above SnO_2 / (Cr, Ni or Cu)2
A second TiO layer is placed on the heavy electrode film (2) in the same manner as in (b).
_2 Film (2) is formed on the following dielectric element, which consists of repeating all or part of the above (a) to (d), that is, on a glass substrate,
Dual electrode film with a thickness of 10 μm or less and a thin film of SnO_2 on the surface and a thin film of Cr, Ni or Cu on the back surface and a thickness of 10 μm
It has a basic structure in which TiO_2 dielectric films of less than A method for manufacturing a laminated thin film dielectric element, characterized in that the internal electrode layer comprises at least two groups connected to different lead-out ends.
JP33978389A 1989-12-27 1989-12-27 Laminated thin-film dielectric element and manufacture thereof Pending JPH03200309A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33978389A JPH03200309A (en) 1989-12-27 1989-12-27 Laminated thin-film dielectric element and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33978389A JPH03200309A (en) 1989-12-27 1989-12-27 Laminated thin-film dielectric element and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH03200309A true JPH03200309A (en) 1991-09-02

Family

ID=18330769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33978389A Pending JPH03200309A (en) 1989-12-27 1989-12-27 Laminated thin-film dielectric element and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH03200309A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995008831A1 (en) * 1993-09-20 1995-03-30 The Regents Of The University Of California High performance capacitors using nano-structure multilayer materials fabrication
JP2015119184A (en) * 2013-12-16 2015-06-25 コリア・インスティテュート・オブ・サイエンス・アンド・テクノロジー Multilayer ceramic capacitor and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995008831A1 (en) * 1993-09-20 1995-03-30 The Regents Of The University Of California High performance capacitors using nano-structure multilayer materials fabrication
US5414588A (en) * 1993-09-20 1995-05-09 The Regents Of The University Of California High performance capacitors using nano-structure multilayer materials fabrication
JP2015119184A (en) * 2013-12-16 2015-06-25 コリア・インスティテュート・オブ・サイエンス・アンド・テクノロジー Multilayer ceramic capacitor and manufacturing method thereof

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