JPH05335173A - Laminated ceramic electronic component and manufacture thereof - Google Patents
Laminated ceramic electronic component and manufacture thereofInfo
- Publication number
- JPH05335173A JPH05335173A JP16418192A JP16418192A JPH05335173A JP H05335173 A JPH05335173 A JP H05335173A JP 16418192 A JP16418192 A JP 16418192A JP 16418192 A JP16418192 A JP 16418192A JP H05335173 A JPH05335173 A JP H05335173A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- substrate
- electronic component
- conductor
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は積層セラミック電子部品
及びその製造方法に関する。具体的にいうと、ビデオテ
ープレコーダ等の電子部品に広く用いられている積層セ
ラミックコンデンサ、積層バリスタ、積層圧電素子、多
層セラミック基板等の積層セラミック電子部品とその製
造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated ceramic electronic component and a method for manufacturing the same. More specifically, the present invention relates to a monolithic ceramic electronic component such as a monolithic ceramic capacitor, a monolithic varistor, a monolithic piezoelectric element, and a multi-layered ceramic substrate that are widely used in electronic components such as a video tape recorder, and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来の積層セラミックコンデンサの製造
方法を説明する（図示せず）。まず、素子寸法よりも大
きな所定の大きさにカットされたセラミック生シート上
に銀系ペースト等の電極ペースト（内部電極）を印刷
し、乾燥させた後、この電極ペーストが印刷されたセラ
ミック生シートを複数枚重ねて圧着させる。ついで、こ
れを１素子の大きさにカットして焼成する。焼成後、内
部電極と導通させるようにして素子の表面に電極ペース
トを塗布し、これを焼き付けて素子の両端に外部電極を
形成し、チップ状の積層セラミックコンデンサを製作し
ている。2. Description of the Related Art A conventional method for manufacturing a monolithic ceramic capacitor will be described (not shown). First, an electrode paste (internal electrode) such as a silver paste is printed on a ceramic green sheet cut into a predetermined size larger than the element size, dried, and then the electrode green paste-printed ceramic green sheet. Stack multiple sheets and press them together. Then, this is cut into a size of one element and fired. After firing, an electrode paste is applied to the surface of the element so as to be electrically connected to the internal electrodes, and this is fired to form external electrodes at both ends of the element to manufacture a chip-shaped multilayer ceramic capacitor.
【０００３】[0003]
【発明が解決しようとする課題】近年、電子部品の分野
においては、電子回路の高密度化・高集積化に伴って、
積層セラミックコンデンサ等の電子部品の一層の微小化
および高性能化が望まれている。したがって、積層セラ
ミックコンデンサにおいて、容量を小さくすることなく
微小化するためには、セラミック層（誘電体層）の厚み
をできるだけ薄くすることが望まれる。In recent years, in the field of electronic parts, with the increase in density and integration of electronic circuits,
There is a demand for further miniaturization and higher performance of electronic components such as monolithic ceramic capacitors. Therefore, in order to miniaturize the monolithic ceramic capacitor without reducing the capacitance, it is desirable to make the thickness of the ceramic layer (dielectric layer) as thin as possible.
【０００４】しかしながら、従来のような積層セラミッ
クコンデンサにおいてセラミック層の厚みを薄くしよう
とすると、種々の問題があった。まず、セラミック層を
薄くするためには、セラミック原料粉末粒径を小さくす
る必要があるが、セラミック原料粉末の粒径の微小化に
は限度がある。また、セラミック層を薄くすると、内部
電極の厚みも薄くする必要があるため、焼成工程におい
て内部電極に電極切れが生じ易い。さらに、セラミック
層を薄くすると、焼成時における内部電極の異常成長に
よりショートが発生したり、セラミック層に発生した孔
によって耐圧が低下する等の問題が生じる。このため、
従来の積層セラミックコンデンサにあっては、セラミッ
ク層の厚みを数μｍより薄くすることは不可能で、積層
セラミックコンデンサの微小化及び大容量化には限界が
あった。However, when trying to reduce the thickness of the ceramic layer in the conventional monolithic ceramic capacitor, there were various problems. First, in order to make the ceramic layer thin, it is necessary to reduce the particle size of the ceramic raw material powder, but there is a limit to the miniaturization of the particle size of the ceramic raw material powder. Further, when the ceramic layer is made thin, the thickness of the internal electrode also needs to be made thin, and therefore, the internal electrode is likely to be broken during the firing process. Furthermore, if the ceramic layer is made thin, problems such as a short circuit due to abnormal growth of the internal electrodes during firing and a decrease in withstand voltage due to holes generated in the ceramic layer occur. For this reason,
In the conventional monolithic ceramic capacitor, it is impossible to make the thickness of the ceramic layer thinner than several μm, and there is a limit to miniaturization and large capacity of the monolithic ceramic capacitor.
【０００５】本発明は叙上の従来例の欠点に鑑みてなさ
れたものであり、その目的とするところは、積層セラミ
ック電子部品の高性能を実現しながらセラミック層を薄
層化することにある。The present invention has been made in view of the drawbacks of the above conventional examples, and an object thereof is to reduce the thickness of a ceramic layer while realizing high performance of a laminated ceramic electronic component. ..
【０００６】[0006]
【課題を解決するための手段】本発明による積層セラミ
ック電子部品は、複数層の導電体電極と、ＣＶＤ法によ
って形成された複数層のセラミック層とを交互に積層し
たことを特徴としている。A laminated ceramic electronic component according to the present invention is characterized in that a plurality of layers of conductor electrodes and a plurality of layers of ceramic layers formed by a CVD method are alternately laminated.
【０００７】さらに、上記導電体電極はＣＶＤ法、蒸着
法もしくはスパッタ法のうちの少なくとも１種の方法を
用いて形成することができる。Further, the conductor electrode can be formed by using at least one of the CVD method, the vapor deposition method and the sputtering method.
【０００８】また、本発明による積層セラミック電子部
品の製造方法は、基板の上に導電体電極とＣＶＤ法によ
るセラミック層とを交互に複数層積層した後、前記基板
を除去することを特徴としている。Further, the method for manufacturing a monolithic ceramic electronic component according to the present invention is characterized in that a plurality of conductor electrodes and ceramic layers formed by a CVD method are alternately laminated on a substrate, and then the substrate is removed. ..
【０００９】[0009]
【作用】本発明の積層セラミック電子部品にあっては、
セラミック層がＣＶＤ法によって形成され、さらに、導
電体電極がＣＶＤ法、蒸着法、スパッタ法等によって形
成されているので、セラミック層及び導電体電極のいず
れも緻密な膜が形成され、しかも、焼成等の加熱工程を
経ないので、導電体電極の電極切れ、ショート等の欠陥
が生じにくく、電子部品としての高性能化が可能とな
る。In the laminated ceramic electronic component of the present invention,
Since the ceramic layer is formed by the CVD method and the conductor electrode is formed by the CVD method, the vapor deposition method, the sputtering method, etc., a dense film is formed on both the ceramic layer and the conductor electrode, and the firing is performed. Since the heating process such as the above is not performed, defects such as electrode breakage and short circuit of the conductor electrode are unlikely to occur, and high performance as an electronic component can be achieved.
【００１０】さらに、セラミック層がＣＶＤ法によって
形成され、導電体電極がＣＶＤ法、蒸着法、スパッタ法
等によって形成されているので、セラミック層や導電体
電極の１μｍ以下の薄層化が可能となり、超小型の積層
セラミック電子部品が得られる。Further, since the ceramic layer is formed by the CVD method and the conductor electrode is formed by the CVD method, the vapor deposition method, the sputtering method, etc., the ceramic layer and the conductor electrode can be thinned to 1 μm or less. , Ultra-small monolithic ceramic electronic components can be obtained.
【００１１】また、本発明の積層セラミック電子部品の
製造方法にあっては、基板の上にセラミック層及び導電
体電極を形成しているので、基板を支持体として極薄の
セラミック層及び導電体電極を成長させ、交互に積層さ
せることができる。しかも、最終的には基板を除去して
いるので、基板によって積層セラミック電子部品が大き
くなることがなく、上記のような超小型の積層セラミッ
ク電子部品を製作することができる。Further, in the method for manufacturing a monolithic ceramic electronic component of the present invention, since the ceramic layer and the conductor electrode are formed on the substrate, the substrate is used as a support and the ultrathin ceramic layer and the conductor are formed. The electrodes can be grown and stacked alternately. In addition, since the substrate is finally removed, the monolithic ceramic electronic component does not become large due to the substrate, and the above-mentioned ultra-small monolithic ceramic electronic component can be manufactured.
【００１２】[0012]
【実施例】図１（ａ）（ｂ）（ｃ）（ｄ）は、本発明の
一実施例による積層セラミックコンデンサの製造方法を
示している。図１（ａ）に示すものは表面が平滑な基板
１であって、エッチング等によって選択的に除去可能な
材質であればよく、絶縁基板に限定されない。例えば、
アルミナ基板等を用いることができる。この基板１の上
には、図１（ｂ）に示すように、セラミック層３が形成
され、その上に１層目の導電体電極２ａが形成され、そ
の上にセラミック層３が形成され、さらに２層目の導電
体電極２ｂが形成され、さらにセラミック層３が形成さ
れ、その上に３層目の導電体電極２ａが形成される。こ
のような工程を繰り返すことにより、基板１の表面には
導電体電極２ａ，２ｂとセラミック層３とが交互に複数
層ずつ積層され、複数層の導電体電極２ａ，２ｂと複数
層のセラミック層３とからなるセラミック−金属積層体
４が形成される。ここで、各セラミック層３はＣＶＤ法
によって形成され、各導電体電極２ａ，２ｂはＣＶＤ
法、蒸着法もしくはスパッタ法のうちいずれかの方法を
用いて形成されており、各セラミック層３及び各導電体
電極２ａ，２ｂの厚みは１μｍ以下としてある。また、
内部電極となる導電体電極２ａ，２ｂはマスクを用いて
パターン化されており、奇数層目の導電体電極２ａと偶
数層目の導電体電極２ｂとは、交互に反対側の端部へ引
き出されている。この後、基板１をエッチング等によっ
て選択的に除去すると、図１（ｃ）に示すようなセラミ
ック−金属積層体４だけが残る。ついで、ディッピング
やスパッタ等によって両端に外部電極５ａ，５ｂを形成
すると、奇数層目の導電体電極２ａが一方の外部電極５
ａと導通し、偶数層目の導電体電極２ｂが他方の外部電
極５ｂと導通し、図１（ｄ）に示すような超小型の積層
セラミックコンデンサ６が製作される。1 (a), 1 (b), 1 (c) and 1 (d) show a method of manufacturing a monolithic ceramic capacitor according to an embodiment of the present invention. The substrate shown in FIG. 1A is a substrate 1 having a smooth surface, and any material that can be selectively removed by etching or the like may be used, and is not limited to an insulating substrate. For example,
An alumina substrate or the like can be used. As shown in FIG. 1B, a ceramic layer 3 is formed on the substrate 1, a first-layer conductor electrode 2a is formed thereon, and a ceramic layer 3 is formed thereon. Further, the second-layer conductor electrode 2b is formed, the ceramic layer 3 is further formed, and the third-layer conductor electrode 2a is formed thereon. By repeating such steps, a plurality of conductor electrodes 2a and 2b and a plurality of ceramic layers 3 are alternately laminated on the surface of the substrate 1, and a plurality of conductor electrodes 2a and 2b and a plurality of ceramic layers are laminated. A ceramic-metal laminate 4 of 3 is formed. Here, each ceramic layer 3 is formed by a CVD method, and each conductor electrode 2a, 2b is formed by CVD.
Method, vapor deposition method, or sputtering method, and the thickness of each ceramic layer 3 and each conductor electrode 2a, 2b is 1 μm or less. Also,
The conductor electrodes 2a and 2b to be the internal electrodes are patterned using a mask, and the conductor electrodes 2a of the odd-numbered layers and the conductor electrodes 2b of the even-numbered layers are alternately drawn to the opposite ends. Has been. After that, when the substrate 1 is selectively removed by etching or the like, only the ceramic-metal laminate 4 as shown in FIG. 1C remains. Next, when the external electrodes 5a and 5b are formed on both ends by dipping, sputtering, etc., the conductor electrode 2a of the odd-numbered layer becomes one external electrode 5.
The conductive electrode 2b of the even-numbered layer is electrically connected to the outer electrode 5b of the other layer, and the microminiature multilayer ceramic capacitor 6 as shown in FIG. 1D is manufactured.
【００１３】なお、図１では１素子のみの製造工程につ
いて説明しているが、複数素子を同時に製作することに
より効率的に積層セラミックコンデンサを製造すること
ができる。Although the manufacturing process of only one element is described in FIG. 1, a multilayer ceramic capacitor can be efficiently manufactured by simultaneously manufacturing a plurality of elements.
【００１４】つぎに、本発明をより明確に説明するた
め、以下に具体的実施例を掲げて説明する。実施例１ 図２は積層セラミックコンデンサ６の製作に用いた熱Ｃ
ＶＤ装置７の概略構成図であって、８はＣＶＤ用のチャ
ンバー、９は基板１をセットするためのサセプタ、１０
はＯ2ガスの給送路、１１はＡｒキャリアガスの給送
路、１２はＴＩＰ〔チタンイソプロポキシド〕のベッセ
ル、１３はＰｂ（Ｃ2Ｈ5）4のベッセル、１４はＬａ
（ＤＰＭ）3〔ＤＰＭ＝Ｃ11Ｈ19Ｏ2〕のベッセル、１５
は（ＰｔＣｌ2）2（ＣＯ）3のベッセルであって、ＴＩ
Ｐ、Ｐｂ（Ｃ2Ｈ5）4、Ｌａ（ＤＰＭ）3及び（ＰｔＣｌ
2）2（ＣＯ）3の各ベッセル１２，１３，１４，１５は
Ａｒキャリアガスの給送路１１に並列に配置されてい
る。Next, in order to more clearly describe the present invention, specific examples will be described below. Example 1 FIG. 2 shows heat C used for manufacturing the monolithic ceramic capacitor 6.
FIG. 2 is a schematic configuration diagram of the VD device 7, where 8 is a chamber for CVD, 9 is a susceptor for setting the substrate 1 and 10
Is an O 2 gas feed path, 11 is an Ar carrier gas feed path, 12 is a TIP [titanium isopropoxide] vessel, 13 is a Pb (C 2 H 5 ) 4 vessel, and 14 is La.
(DPM) 3 [DPM = C 11 H 19 O 2 ] Vessel, 15
Is a vessel of (PtCl 2 ) 2 (CO) 3 and has a TI
P, Pb (C 2 H 5 ) 4 , La (DPM) 3 and (PtCl
2 ) 2 (CO) 3 vessels 12, 13, 14, and 15 are arranged in parallel to the Ar carrier gas feed path 11.
【００１５】積層セラミックコンデンサ６を製作するた
めの基板１として縦横各５０ｍｍ、厚さ０.２ｍｍのＡ
ｌ2Ｏ3基板を用い、このＡｌ2Ｏ3基板１を熱ＣＶＤ装置
７のサセプタ９上にセットした。As a substrate 1 for manufacturing the monolithic ceramic capacitor 6, an A having a length and width of 50 mm and a thickness of 0.2 mm is used.
This Al 2 O 3 substrate 1 was set on the susceptor 9 of the thermal CVD device 7 using an l 2 O 3 substrate.
【００１６】ついで、サセプタ９を６００℃に加熱した
状態で、ＴＩＰ、Ｐｂ（Ｃ2Ｈ5）4及びＬａ（ＤＰＭ）3
の各ベッセル１２，１３，１４の各バルブ１６，１７，
１８を開き、気化したＴＩＰ、Ｐｂ（Ｃ2Ｈ5）4及びＬ
ａ（ＤＰＭ）3の各原料ガスをＡｒキャリアガスに乗せ
てチャンバー８へ送り、この原料ガスをＯ2ガスと共に
Ａｌ2Ｏ3基板１に吹き付けて反応させ、厚さ約１μｍの
ＰＬＴ薄膜２１（セラミック層３）を形成した（以下、
ＰＬＴ薄膜形成工程という）。Then, with the susceptor 9 heated to 600 ° C., TIP, Pb (C 2 H 5 ) 4 and La (DPM) 3 are added.
The valves 16, 17, of the vessels 12, 13, 14 of
Open 18 and vaporize TIP, Pb (C 2 H 5 ) 4 and L
Each raw material gas of a (DPM) 3 is placed on an Ar carrier gas and sent to the chamber 8. The raw material gas is blown together with the O 2 gas onto the Al 2 O 3 substrate 1 to cause reaction, and the PLT thin film 21 (about 1 μm thick) Ceramic layer 3) was formed (hereinafter,
PLT thin film forming process).
【００１７】次に、ＰＬＴ薄膜２１の上にメタルマスク
をセットし、基板１を６００℃に加熱した状態で（Ｐｔ
Ｃｌ2）2（ＣＯ）3のベッセル１５のバルブ１９を開
き、（ＰｔＣｌ2）2（ＣＯ）3の原料ガスをＡｒキャリ
アガスと共にメタルマスクの窓を通してＡｌ2Ｏ3基板１
に吹き付け、図３（ａ）（ｂ）に示すようにメタルマス
クの窓と同一パターンに厚さ約０.５μｍのＰｔ膜２０
ａ（導電体電極２ａ）を形成した（以下、Ｐｔ膜形成第
１工程という）。図３（ｂ）は図３（ａ）のＸ部拡大図
であって、斜線を施した領域は１素子分に相当する領域
を示し、図３（ｂ）に記入されている数字は各部の寸法
（単位ｍｍ）を示している。Next, a metal mask is set on the PLT thin film 21, and the substrate 1 is heated to 600 ° C. (Pt.
The valve 19 of the vessel 15 of Cl 2 ) 2 (CO) 3 is opened, and the source gas of (PtCl 2 ) 2 (CO) 3 is passed together with the Ar carrier gas through the window of the metal mask Al 2 O 3 substrate 1
3A and 3B, the Pt film 20 having a thickness of about 0.5 μm is formed in the same pattern as the window of the metal mask as shown in FIGS.
a (conductor electrode 2a) was formed (hereinafter referred to as a Pt film formation first step). FIG. 3 (b) is an enlarged view of the X part of FIG. 3 (a), and the shaded area indicates the area corresponding to one element, and the numbers written in FIG. 3 (b) indicate the parts. The dimension (unit: mm) is shown.
【００１８】ついで、再びＰＬＴ薄膜形成工程によりＰ
ＬＴ薄膜２１を約１μｍ生成させた。Then, the PLT thin film forming step is performed again to form P
The LT thin film 21 was formed to have a thickness of about 1 μm.
【００１９】次に、最上層のＰＬＴ薄膜２１の上に別な
メタルマスクをセットし、基板１を６００℃に加熱した
状態で（ＰｔＣｌ2）2（ＣＯ）3のチャンバー１５のバ
ルブ１９を開き、（ＰｔＣｌ2）2（ＣＯ）3の原料ガス
をＡｒキャリアガスと共にメタルマスクの窓を通してＡ
ｌ2Ｏ3基板１に吹き付け、図４（ａ）（ｂ）に示すよう
にメタルマスクの窓と同一パターンに厚さ約０.５μｍ
のＰｔ膜２０ｂ（導電体電極２ｂ）を形成した（以下、
Ｐｔ膜形成第２工程という）。図４（ｂ）は図４（ａ）
のＹ部拡大図であって、斜線を施した領域は１素子分に
相当する領域を示し、図３（ｂ）に記入されている数字
は寸法（単位ｍｍ）を示している。Next, another metal mask is set on the uppermost PLT thin film 21, and the valve 19 of the (PtCl 2 ) 2 (CO) 3 chamber 15 is opened with the substrate 1 heated to 600 ° C. , (PtCl 2 ) 2 (CO) 3 source gas together with Ar carrier gas through the window of the metal mask A
Sprayed onto the l 2 O 3 substrate 1 and having a thickness of about 0.5 μm in the same pattern as the window of the metal mask as shown in FIGS.
Pt film 20b (conductor electrode 2b) was formed (hereinafter,
This is called the Pt film formation second step). 4 (b) is shown in FIG. 4 (a).
3B is an enlarged view of the Y portion of FIG. 3A, in which the shaded area indicates the area corresponding to one element, and the numbers entered in FIG. 3B indicate the dimensions (unit: mm).
【００２０】このように、ＰＬＴ薄膜形成−Ｐｔ膜形成
第１−ＰＬＴ薄膜形成−Ｐｔ膜形成第２の各工程を１５
０回繰り返し、最後にＰＬＴ薄膜形成工程を行なってＡ
ｌ2Ｏ3基板１の上にセラミック−金属積層体４を得た。As described above, each of the PLT thin film formation-Pt film formation first-PLT thin film formation-Pt film formation second steps is performed 15 times.
Repeat 0 times, and finally perform the PLT thin film formation process
A ceramic-metal laminate 4 was obtained on the l 2 O 3 substrate 1.
【００２１】この後、腐食性ガスのイオンビームによる
ドライエッチングでＡｌ2Ｏ3基板１を除去した後、図３
（ｂ）及び図４（ｂ）の破線Ｃに沿ってダイシングソー
によりセラミック−金属積層体４を素子毎にカットし
た。１素子ずつにカットしたセラミック−金属積層体４
の両端にディッピングによりＡｇペーストを付け、６０
０℃で焼き付けて外部電極５ａ，５ｂを形成した。After that, the Al 2 O 3 substrate 1 is removed by dry etching with an ion beam of a corrosive gas, and then, as shown in FIG.
The ceramic-metal laminated body 4 was cut for each element by a dicing saw along the broken line C in (b) and FIG. 4 (b). Ceramic-metal laminate 4 cut into individual elements 4
Attach Ag paste by dipping to both ends of 60
The external electrodes 5a and 5b were formed by baking at 0 ° C.
【００２２】こうして長さ約１ｍｍ、幅約０.５ｍｍ、
厚さ約０.４５ｍｍの積層セラミックコンデンサ６を得
た。この積層セラミックコンデンサ６の容量を測定した
ところ１.１μＦの値であった。Thus, the length is about 1 mm, the width is about 0.5 mm,
A multilayer ceramic capacitor 6 having a thickness of about 0.45 mm was obtained. The capacitance of the monolithic ceramic capacitor 6 was measured and found to be 1.1 μF.
【００２３】実施例２ Ｐｔ層２０ａ，２０ｂ（導電体電極２ａ，２ｂ）の形成
方法として蒸着法を用い、それ以外については実施例１
と同様にして長さ約１ｍｍ、幅約０.５ｍｍ、厚さ約０.
４５ｍｍの積層セラミックコンデンサ６を製作した。こ
の積層セラミックコンデンサ６の容量を測定したところ
１.０μＦの値が得られた。 Example 2 A vapor deposition method was used as a method for forming the Pt layers 20a and 20b (conductor electrodes 2a and 2b), and other than that, Example 1 was used.
Similarly, the length is about 1 mm, the width is about 0.5 mm, and the thickness is about 0.1 mm.
A 45 mm monolithic ceramic capacitor 6 was manufactured. When the capacitance of the monolithic ceramic capacitor 6 was measured, a value of 1.0 μF was obtained.
【００２４】実施例３ Ｐｔ層２０ａ，２０ｂ（導電体電極２ａ，２ｂ）の形成
方法としてスパッタ法を用い、実施例１と同様にして長
さ約１ｍｍ、幅約０.５ｍｍ、厚さ約０.４５ｍｍの積層
セラミックコンデンサ６を得た。この積層セラミックコ
ンデンサ６の容量を測定したところ１.１μＦの値が得
られた。 Example 3 A sputtering method was used as a method for forming the Pt layers 20a and 20b (conductor electrodes 2a and 2b). As in Example 1, a length of about 1 mm, a width of about 0.5 mm, and a thickness of about 0 were set. A .45 mm monolithic ceramic capacitor 6 was obtained. When the capacitance of this monolithic ceramic capacitor 6 was measured, a value of 1.1 μF was obtained.
【００２５】[0025]
【発明の効果】本発明によれば、セラミック層及び導電
体電極のいずれも緻密な膜が得られ、しかも高温に曝さ
れないので、セラミック層や導電体電極を１μｍ以下に
薄層化してもセラミック層や導電体電極に欠陥が生じに
くく、高性能で超小型の積層セラミック電子部品を得ら
れる。According to the present invention, a dense film can be obtained for both the ceramic layer and the conductor electrode, and since it is not exposed to high temperature, even if the ceramic layer or the conductor electrode is thinned to 1 μm or less, the ceramic It is possible to obtain a high-performance and ultra-compact monolithic ceramic electronic component in which defects are unlikely to occur in layers and conductor electrodes.
【００２６】また、本発明にあっては、基板を支持体と
して極薄のセラミック層及び導電体電極を成長させ、交
互に積層させることができるので、安定かつ均一に積層
セラミック電子部品を製作でき、しかも、最終的には基
板を除去することによって超小型もしくは超薄型の積層
セラミック電子部品を製作することができる。Further, according to the present invention, since an extremely thin ceramic layer and a conductor electrode can be grown using the substrate as a support and laminated alternately, a laminated ceramic electronic component can be manufactured stably and uniformly. Moreover, by finally removing the substrate, an ultra-small or ultra-thin monolithic ceramic electronic component can be manufactured.
【図１】（ａ）（ｂ）（ｃ）（ｄ）は本発明の一実施例
による積層セラミックコンデンサの製造方法を示す断面
図である。1A, 1B, 1C and 1D are cross-sectional views showing a method for manufacturing a monolithic ceramic capacitor according to an embodiment of the present invention.
【図２】本発明の具体的実施例において用いたＣＶＤ装
置を示す概略構成図である。FIG. 2 is a schematic configuration diagram showing a CVD apparatus used in a specific example of the present invention.
【図３】（ａ）は基板の上に形成されたＰｔ膜（導電体
電極）を示す平面図、（ｂ）は（ａ）のＸ部拡大図であ
る。FIG. 3A is a plan view showing a Pt film (conductor electrode) formed on a substrate, and FIG. 3B is an enlarged view of an X portion of FIG.
【図４】（ａ）は基板の上に形成された別なＰｔ膜（導
電体電極）を示す平面図、（ｂ）は（ａ）のＹ部拡大図
である。4A is a plan view showing another Pt film (conductor electrode) formed on a substrate, and FIG. 4B is an enlarged view of a Y portion of FIG. 4A.
１ 基板 ２ａ，２ｂ 導電体電極 ３ セラミック層 ５ａ，５ｂ 外部電極 ７ 熱ＣＶＤ装置 DESCRIPTION OF SYMBOLS 1 Substrate 2a, 2b Conductor electrode 3 Ceramic layer 5a, 5b External electrode 7 Thermal CVD apparatus
Claims (3)
て形成された複数層のセラミック層とを交互に積層した
ことを特徴とする積層セラミック電子部品。1. A laminated ceramic electronic component, wherein a plurality of layers of conductor electrodes and a plurality of layers of ceramic layers formed by a CVD method are alternately laminated.
くはスパッタ法のうちの少なくとも１種の方法を用いて
形成した請求項１に記載の積層セラミック電子部品。2. The multilayer ceramic electronic component according to claim 1, wherein the conductor electrode is formed by using at least one of a CVD method, a vapor deposition method, and a sputtering method.
セラミック層とを交互に複数層積層した後、前記基板を
除去することを特徴とする積層セラミック電子部品の製
造方法。3. A method of manufacturing a monolithic ceramic electronic component, comprising: alternately laminating a plurality of conductor electrodes and ceramic layers formed by a CVD method on a substrate, and then removing the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16418192A JPH05335173A (en) | 1992-05-28 | 1992-05-28 | Laminated ceramic electronic component and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16418192A JPH05335173A (en) | 1992-05-28 | 1992-05-28 | Laminated ceramic electronic component and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05335173A true JPH05335173A (en) | 1993-12-17 |
Family
ID=15788253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16418192A Pending JPH05335173A (en) | 1992-05-28 | 1992-05-28 | Laminated ceramic electronic component and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05335173A (en) |
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|---|---|---|---|---|
| US6876536B2 (en) | 2002-12-27 | 2005-04-05 | Tdk Corporation | Thin film capacitor and method for fabricating the same |
| US6930875B2 (en) | 2003-06-12 | 2005-08-16 | Tdk Corporation | Multi-layered unit |
| JPWO2004065668A1 (en) * | 2003-01-21 | 2006-05-18 | Tdk株式会社 | Composition for thin film capacitor, high dielectric constant insulating film, thin film capacitor, thin film multilayer capacitor, and method for manufacturing thin film capacitor |
| US7145198B2 (en) | 2001-08-28 | 2006-12-05 | Tdk Corporation | Compositions for thin-film capacitance device, high-dielectric constant insulating film, thin-film capacitance device, and thin-film multilayer capacitor |
| US7242044B2 (en) | 2001-08-28 | 2007-07-10 | Tdk Corporation | Compositions for thin-film capacitance device, high-dielectric constant insulating film, thin-film capacitance device, and thin-film multilayer capacitor |
| US7312514B2 (en) | 2003-02-27 | 2007-12-25 | Tdk Corporation | High-permittivity insulation film, thin film capacity element, thin film multilayer capacitor, and production method of thin film capacity element |
| US7319081B2 (en) | 2003-02-27 | 2008-01-15 | Tdk Corporation | Thin film capacity element composition, high-permittivity insulation film, thin film capacity element, thin film multilayer capacitor, electronic circuit and electronic apparatus |
| KR100865760B1 (en) * | 2006-03-29 | 2008-10-28 | 박영진 | Multi layer capacitor device and multi layer varistor device and method for manufacturing the same |
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-
1992
- 1992-05-28 JP JP16418192A patent/JPH05335173A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7145198B2 (en) | 2001-08-28 | 2006-12-05 | Tdk Corporation | Compositions for thin-film capacitance device, high-dielectric constant insulating film, thin-film capacitance device, and thin-film multilayer capacitor |
| US7242044B2 (en) | 2001-08-28 | 2007-07-10 | Tdk Corporation | Compositions for thin-film capacitance device, high-dielectric constant insulating film, thin-film capacitance device, and thin-film multilayer capacitor |
| US6876536B2 (en) | 2002-12-27 | 2005-04-05 | Tdk Corporation | Thin film capacitor and method for fabricating the same |
| JPWO2004065668A1 (en) * | 2003-01-21 | 2006-05-18 | Tdk株式会社 | Composition for thin film capacitor, high dielectric constant insulating film, thin film capacitor, thin film multilayer capacitor, and method for manufacturing thin film capacitor |
| US7745869B2 (en) | 2003-01-21 | 2010-06-29 | Tdk Corporation | Thin film capacitance element composition, high permittivity insulation film, thin film capacitance element, thin film multilayer capacitor and production method of thin film capacitance element |
| JP4706479B2 (en) * | 2003-01-21 | 2011-06-22 | Ｔｄｋ株式会社 | Composition for thin film capacitor, high dielectric constant insulating film, thin film capacitor, thin film multilayer capacitor, and method for manufacturing thin film capacitor |
| US7312514B2 (en) | 2003-02-27 | 2007-12-25 | Tdk Corporation | High-permittivity insulation film, thin film capacity element, thin film multilayer capacitor, and production method of thin film capacity element |
| US7319081B2 (en) | 2003-02-27 | 2008-01-15 | Tdk Corporation | Thin film capacity element composition, high-permittivity insulation film, thin film capacity element, thin film multilayer capacitor, electronic circuit and electronic apparatus |
| US6930875B2 (en) | 2003-06-12 | 2005-08-16 | Tdk Corporation | Multi-layered unit |
| US7580241B2 (en) | 2004-04-26 | 2009-08-25 | Tdk Corporation | Thin film capacitor element composition, high permittivity insulation film, thin film capacitor element, thin film multilayer capacitor, and method of production of thin film capacitor element |
| KR100865760B1 (en) * | 2006-03-29 | 2008-10-28 | 박영진 | Multi layer capacitor device and multi layer varistor device and method for manufacturing the same |
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