JPH03198285A - Read circuit for semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain the read circuit which has small power consumption by providing a bias control circuit and controlling a bias application circuit for an amplifying circuit for an input signal passed through a bit line couple. CONSTITUTION:When external signals CESL, SAN, SPA, etc., become active and a read state is entered, the signals of a couple of bit lines BIT and the inverse of BIT are supplied to a main amplifier 22 and when the main amplifier control signal varies from 1 to 0, the N type transistor(TR) 26 of the bias con trol circuit 32 turns to apply a necessary voltage to the node B of the main amplifier bias control circuit 32; and a TR 34 is driven with a constant voltage and a necessary bias voltage is applied to the amplifier 22, which enters the best operation state. Then when the signals of the bit lines become large enough to invert the bias control signal into 0, the N type TR 38 of the circuit 36 turns on to hold the node B at the potential of a power source Vcc, and the bias voltage of the circuit 22 becomes zero. This bias voltage is controlled to prevent the current of the main amplifier from being wasted and the small- power-consumption read circuit is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a read circuit for a semiconductor memory device.

[Prior Art] FIG. 3 shows a conventional readout circuit for DRAM (dynamic random access memory).

In the figure, a bit line pair BIT and BIT are connected to a sense amplifier 10. Bit line pair BIT and BI
T is further a P channel type MOS transistor (hereinafter referred to as P
MO8) Transistor) Connected to one end of MO8) 12 and 14, respectively. A signal C3EL is commonly applied to the gates of the PMOS transistors 12 and 14. PMO8
) transistor 12 and! The other ends of 4 are respectively connected to bit line pair bias applying circuits (hereinafter referred to as bit bias circuits) 20.

The bit bias circuit 20 is composed of, for example, two PMOS transistors 16 and 18, whose sources are supplied with a power supply voltage Vcc.

The gates of PMOS transistors 16 and 18 are both grounded, and their drains are connected to bit line pairs BIT and BIT, respectively. Bit bias circuit 20
is connected to the main amplifier 22.

The main amplifier 22 is composed of, for example, a differential amplifier circuit, and is connected to the output signal line pair Dout and Dout.

On the other hand, the main amplifier control signal is applied to the gate of the PMOS transistor 26 of the bias control circuit 24,
The source of the PMOS transistor 26 is connected to the power supply voltage Vcc.
is supplied. The drain of the PMOS transistor 26 is connected to one end of the resistor 28 (resistance value R1),
One end of a resistor 30 (resistance value R2) is connected to the other end of the resistor 28. The other end of the resistor 30 is grounded, and the output of the bias control circuit 24, that is, the two resistors 23 and 30
The connection point is connected to a main amplifier bias application circuit (hereinafter referred to as main bias circuit) 32.

The main bias circuit 32 is, for example, an N-channel MOS
It is composed of a transistor (hereinafter referred to as an NMO3h transistor) 34, and the source and drain of the NMOS transistor 34 are inserted and connected between the main amplifier 22 and the ground.

FIG. 4 is a time chart in a readout circuit of a storage circuit using a conventional bias control circuit 24. Signal RAS from an external circuit not shown.

By activating CAS, C3EL, SAN and SAP (a, b, c, d, e), bit line pair BI
The data of T and BIT are supplied to the main amplifier 22.

After that, the main amplifier control signal changes from "1" level to "0" level.
'' level (f), and the PMOS transistor 26 changes from a cutoff state to a conduction state. The voltage at the connection point between resistors 28 and 30 changes from 0 to Vcc-R2/ (R1+R2),
The voltage is output to point A (g). As a result, the amplitude of the output signal of the main amplifier 22 becomes maximum, and the signals on the bit line pair are amplified and output to the output line pair Dout and Dout (h, i).

The bias control circuit 24 that performs such conventional operation,
It should be noted that it is constantly operating from the time the signal is read until the end of reading.

[Problems to be Solved by the Invention] In other words, the bias voltage required to amplify the minute signal output from the previous stage at the initial stage of signal readout increases as the signal from the previous stage circuit, for example, the sense amplifier 10 becomes large. continues to be applied even after it is no longer needed, resulting in unnecessary current consumption.

Therefore, an object of the present invention is to provide a readout circuit with low current consumption.

[Means for Solving the Problem] According to the present invention, the above-mentioned object includes an amplifier circuit that amplifies a signal inputted manually via a bit line pair, and an amplifier circuit that is connected to the amplifier circuit and that is connected to the amplifier circuit. a bias application circuit that applies a bias voltage; and a bias application circuit that is connected to the bias application circuit;
When the voltage of the signal is below a predetermined voltage, the bias voltage is generated from the bias application circuit so that the amplifier circuit operates at the best operating point, and when the voltage of the signal exceeds the predetermined voltage, the bias voltage is increased. This can be achieved by including a bias control circuit that controls the bias application circuit so that the bias voltage is zero.

[Operation] According to the above configuration, when the amplitude of the signal from the previous stage is small at the beginning of signal readout, the main bias circuit is activated, the power supply voltage of the main amplifier is biased, and the operating point of the main amplifier is in the best condition. . After the amplitude of the signal from the previous stage becomes sufficiently large and the bias voltage becomes unnecessary, the bias voltage of the main bias circuit becomes zero.

[Embodiment] An embodiment of a readout circuit for a semiconductor memory device according to the present invention will be described with reference to the circuit diagram of FIG.

This embodiment is used, for example, as a circuit for controlling bias voltages to a bit line pair used for DRAM.

In the figure, a bit line pair BIT and BIT is connected to a sense amplifier IO. Bit line pair BIT and BI
T is further connected to one end of PMOS transistors 12 and 14, respectively. A signal C3EL is commonly applied to the gates of the PMOS transistors 12 and 14. The other ends of the PMO3) transistors 12 and 14 are connected to the bit bias circuit 20, respectively.

The bit bias circuit 20 is composed of, for example, two PMOS transistors 16 and 18, the sources of which are each supplied with a power supply voltage Vcc. PMOS
A main amplifier control signal is commonly applied to the gates of the transistors 16 and 18, and the drains of the PMOS transistors 16 and 18 are connected to the bit line pair BIT and BIT.
are connected to each other.

The bit bias circuit 20 is connected to a main amplifier 22.

The main amplifier 22 is composed of, for example, a differential amplifier circuit, and is connected to the output signal line pair Dout and Dout.

On the other hand, in the bias control circuit 36, the sources of the two PMOS transistors 26 and 38 are both connected to the power supply voltage Vc.
c is supplied. A main amplifier control signal is applied to the gate of the PMOS transistor 26, and the PMOS transistor 26 has a main amplifier control signal applied to its gate.
A bias control signal is applied to the gate of the S transistor 38. A resistor 28 is connected to the drains of the PMOS transistors 26 and 38. The drain of the PMOS transistor 38 is grounded via a resistor 30, and the drain of the PMOS transistor 38 is further connected to the main bias circuit 32.

The main bias circuit 32 is, for example, an N-channel MOS
It is composed of a transistor (hereinafter referred to as an NMOS transistor) 34, and the source and drain of the NMOS transistor 34 are inserted and connected between the main amplifier 22 and the ground.

The sense amplifier 10 is an amplifier circuit that amplifies the voltage of the minute signal applied to the bit line pair BIT.

The bit bias circuit 20 is configured such that the main amplifier control signal is “
The circuit is configured such that a bias voltage is applied to the bit line pair when the main amplifier control signal is at the "0" level, and becomes zero when the main amplifier control signal is at the "1" level.

The main amplifier 22 is a circuit that amplifies the signal voltage of the bit line pair BIT and BIT.

The bias control circuit 36 is a circuit that generates a voltage according to a main amplifier control signal and a bias control signal supplied from the outside, and supplies this to the main bias circuit 32.

The main bias circuit 32 is a circuit that sets an operating point by changing the voltage applied to the main amplifier 22 according to the voltage generated by the bias control circuit 36.

FIG. 2 is a time chart of the readout circuit of the embodiment.

With C3ELSSAN and SAP active (a, b, c, d, e), bit line pair BIT and B
The IT signal is supplied to the main amplifier 22. after that,
When the main amplifier control signal changes from the "1" level to the "0" level (f), the PMOS transistor 26 changes from the cutoff state to the conduction state, and the voltage vcc-R2/(R1+R2) at the connection point of the resistors 28 and 30 becomes the main bias. It is output to point B of the circuit 32 (h). At this time, the NMO3) transistor 34 is driven with a constant current, the power supply voltage of the main amplifier 22 is biased, and the best operating state is achieved.

Next, when the signal on the bit line pair becomes large enough, the bias control signal is changed from the "1" level to "
0” level (g). The PMOS transistor 38 changes from the cut-off state to the conductive state, and the voltage at the connection point between the resistors 28 and 30 becomes Vcc (h). The voltage at point B is Vcc,
That is, the level becomes "1" and the NMO8) transistor 34 becomes conductive. Therefore, the voltage of the signal on the output line pair Dout and Dout becomes maximum (i, j).

As a result, when reading signals from the memory circuit, an optimum bias voltage is applied to the bit line pair, and the main amplifier 22 operates at maximum amplitude (full swing).

The readout circuit of the semiconductor memory device described above is a DRAM.
It can be used not only for SRAM (Static Random Access Memory), EFROM (Erasable Programmable Read Only Memory), MROM (Mask Read Only Memory), etc.

[Effects of the Invention] As explained in detail above, according to the present invention, when the voltage of the signal is below a predetermined voltage, the bias voltage that causes the amplifier circuit to operate at the best operating point is generated from the bias application circuit;
When the voltage of the signal exceeds a predetermined voltage, the bias application circuit is controlled to make the bias voltage zero. In this way, by using a simple circuit configured such that a bias voltage is applied to the power supply voltage of the main amplifier at the beginning of signal readout, and the bias voltage becomes zero when the signal voltage becomes large enough, the main Signals can be read out efficiently without wasting current in the amplifier.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a read circuit of a semiconductor memory device of the present invention, FIG. 2 is a time chart in the embodiment of FIG. 1, FIG. 3 is a circuit diagram showing a conventional example, and FIG. 4 1 is a diagram showing a time chart in a conventional example. ID...Sense amplifier, 16. +8.26.
38...PMOS transistor, 20...
...Bit line pair bias application circuit, 28.30...
...Resistor, 32...Main amplifier bias circuit, 34...NMOS transistor, 36...
...Bias control circuit. f Figure 2 Figure 4

Claims (1)

[Claims] an amplifier circuit that amplifies a signal input through the bit line pair; a bias application circuit that is connected to the amplifier circuit and applies a bias voltage to the amplifier circuit; and a bias application circuit that is connected to the bias application circuit; When the voltage of the signal is below a predetermined voltage, the bias voltage that causes the amplifier circuit to operate at the best operating point is generated from the bias application circuit, and when the voltage of the signal exceeds the predetermined voltage, the bias voltage is reduced to zero. A readout circuit for a semiconductor memory device, comprising: a bias control circuit that controls the bias application circuit so as to perform the following steps.