JPH03196639A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPH03196639A JPH03196639A JP33694989A JP33694989A JPH03196639A JP H03196639 A JPH03196639 A JP H03196639A JP 33694989 A JP33694989 A JP 33694989A JP 33694989 A JP33694989 A JP 33694989A JP H03196639 A JPH03196639 A JP H03196639A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- substrate
- reduced
- film
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 3
- 239000010453 quartz Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005336 cracking Methods 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 15
- 239000002184 metal Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、絶縁基板上に形成された簿膜トランジスタに
関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a film transistor formed on an insulating substrate.
薄膜トランジスタを用いて、液晶デイスプレィを構成し
た場合には、薄膜トランジスタのチャンネル部、ソース
部、ドレイン部及びゲート電極などが表面に突出する。When a liquid crystal display is constructed using thin film transistors, the channel portion, source portion, drain portion, gate electrode, etc. of the thin film transistor protrude from the surface.
ところが液晶の配向処理は高い部分が優先的に行われ、
低い部分の配向処理が充分行われず、液晶に配向不良を
生じるという問題点があり、特開昭５９−１０４１７０
号公報の技術においては、前記問題点解決のため、チャ
ンネル部、ソース部、ドレイン部およびゲート電極を絶
縁基板内に埋めこむことを提案している。しかしながら
、配線部分についての問題意識は全く開示されていない
。However, the alignment process of liquid crystal is performed preferentially on the high part.
There is a problem that the alignment treatment of the lower part is not performed sufficiently, resulting in poor alignment of the liquid crystal.
In order to solve the above-mentioned problem, the technique disclosed in the publication proposes embedding the channel section, source section, drain section, and gate electrode in an insulating substrate. However, no awareness of the problem regarding the wiring portion is disclosed at all.
ところが、従来の薄膜トランジスタでは、基板もしくは
基板上に形成された絶縁膜の上に直接ＡＱ等のメタルで
配線部が形成されていた。However, in conventional thin film transistors, wiring portions are formed directly on the substrate or an insulating film formed on the substrate using a metal such as AQ.
このため、配線部の抵抗値を下げるためには、配線の断
面積を広くする必要があった。そこで配線部の断面積を
大きくするためのメタル層を厚くすると表面段差が大き
くなりこの上に形成される保護膜にクラックが生じやす
くなるためメタル層は１．２μｍ程度までしか厚くでき
ないという問題が生じた。Therefore, in order to lower the resistance value of the wiring portion, it was necessary to increase the cross-sectional area of the wiring. Therefore, if the metal layer is made thicker in order to increase the cross-sectional area of the wiring part, the surface step will become larger and the protective film formed on top of this will be more likely to crack, so there is a problem that the metal layer can only be thickened to about 1.2 μm. occured.
本発明の目的は、配線部の段差および表面積を大きくす
ることなく配線部の断面積を大きくして、抵抗値の小さ
い配線部を有する薄膜トランジスタを提供することにあ
る。An object of the present invention is to provide a thin film transistor having a wiring portion with a low resistance value by increasing the cross-sectional area of the wiring portion without increasing the steps and surface area of the wiring portion.
本発明は、絶縁基板上に形成された薄膜トランジスタに
おいて、配線部の少くとも１部分が基板内に埋めこまれ
ていることを特徴とする薄膜トランジスタに関する。The present invention relates to a thin film transistor formed on an insulating substrate, in which at least a portion of a wiring portion is embedded in the substrate.
本発明を図面を参照しながら説明する。The present invention will be described with reference to the drawings.
配線部の少くとも１部分を基板１内に埋めこむための溝
は、第１図ではＡ、第２図ではＡ′で示されている。溝
の深さは、配線部を完全に埋め込むほど深いものであっ
てもよいが、必要に応じてもっと薄い溝にすることもで
きる。A groove for burying at least a portion of the wiring portion into the substrate 1 is designated by A in FIG. 1 and by A' in FIG. 2. The depth of the groove may be deep enough to completely bury the wiring portion, but the groove may be made thinner if necessary.
実施例１
石英基板１に溝Ａを深さ１μｍで形成しくフォトリソ技
術による）、次に活性層２となる多結晶シリコン膜を島
状に形成し、さらに熱酸化膜３を形成する。ゲートとな
る多結晶シリコン膜４を形成しイオン打込にてソース・
ドレイン領域５．５を形成する。Example 1 Grooves A are formed in a quartz substrate 1 to a depth of 1 μm (by photolithography), then a polycrystalline silicon film that will become an active layer 2 is formed in the form of an island, and a thermal oxide film 3 is further formed. A polycrystalline silicon film 4 that will become the gate is formed, and the source and
A drain region 5.5 is formed.
次に溝Ａの部分にＡＱの配線７を１μｍ形成し、層間絶
縁膜６を形成後、コンタクトホールを開口して再びＡＱ
の配線を行う。Next, an AQ wiring 7 of 1 μm thickness is formed in the groove A, and after forming an interlayer insulating film 6, a contact hole is opened and the AQ wiring 7 is again formed.
Perform the wiring.
なお、溝の部分の配線は、Ｗなどの高融点金属を用いて
活性層の多結晶シリコン膜形成より前に形成しておいて
もよい。Note that the wiring in the groove portion may be formed using a high melting point metal such as W before forming the polycrystalline silicon film of the active layer.
実施例２
パイレックス基板８に溝Ａ′を深さ３０００人で形成し
、次にＣｒをゲート９と溝Ａ′の部分に充填する。次に
プラズマＣＶＤ法によりシリコン窒化膜１０、アモルフ
ァスシリコン膜１１、ｎ１アモルファスシリコン膜１２
を形成して所望のパターンにエツチングする６次に眉間
絶縁膜１３を形成し、コンタクトホールを開口し、ＡＱ
配線を行う。Example 2 A groove A' was formed in a Pyrex substrate 8 to a depth of 3,000 mm, and then the gate 9 and the groove A' were filled with Cr. Next, a silicon nitride film 10, an amorphous silicon film 11, an n1 amorphous silicon film 12 are formed by plasma CVD.
Next, a glabellar insulating film 13 is formed, contact holes are opened, and AQ is etched into a desired pattern.
Perform wiring.
配線部の表面積が小さくなることによりデバイスとして
の必要面積がｔＪｓさくなる。また、配線の段差が小さ
くなり、保護膜のクラック等も少なくなった。As the surface area of the wiring portion becomes smaller, the area required for the device becomes smaller by tJs. In addition, the level difference in the wiring has become smaller, and the number of cracks in the protective film has also been reduced.
第１図および第２図は、本発明の薄膜トランジスタの１
例をそれぞれ示す断面図である。
１．８・・・基板
２．１１・・・活性層
３．１０・・・ゲート絶縁膜
４．９・・・ゲート電極
５．１２・・・拡散層
６．１３・・・層間絶縁膜
７．１４・・・配線
Ａ、Ａ’・・・溝および配線1 and 2 show one of the thin film transistors of the present invention.
FIG. 3 is a cross-sectional view showing examples. 1.8... Substrate 2.11... Active layer 3.10... Gate insulating film 4.9... Gate electrode 5.12... Diffusion layer 6.13... Interlayer insulating film 7 .14... Wiring A, A'... Groove and wiring
Claims (1)
、配線部の少くとも１部分が基板内に埋めこまれている
ことを特徴とする薄膜トランジスタ。1. A thin film transistor formed on an insulating substrate, characterized in that at least a portion of the wiring portion is embedded within the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33694989A JPH03196639A (en) | 1989-12-26 | 1989-12-26 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33694989A JPH03196639A (en) | 1989-12-26 | 1989-12-26 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03196639A true JPH03196639A (en) | 1991-08-28 |
Family
ID=18304112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33694989A Pending JPH03196639A (en) | 1989-12-26 | 1989-12-26 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03196639A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006090445A1 (en) * | 2005-02-23 | 2006-08-31 | Fujitsu Limited | Semiconductor circuit device, and method for manufacturing the semiconductor circuit device |
| JP2019050394A (en) * | 2018-10-31 | 2019-03-28 | 株式会社半導体エネルギー研究所 | Semiconductor device and electronic apparatus |
| US10665610B2 (en) | 2000-12-11 | 2020-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
-
1989
- 1989-12-26 JP JP33694989A patent/JPH03196639A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10665610B2 (en) | 2000-12-11 | 2020-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
| WO2006090445A1 (en) * | 2005-02-23 | 2006-08-31 | Fujitsu Limited | Semiconductor circuit device, and method for manufacturing the semiconductor circuit device |
| JP5018475B2 (en) * | 2005-02-23 | 2012-09-05 | 富士通セミコンダクター株式会社 | Semiconductor circuit device and method of manufacturing the semiconductor circuit device |
| JP2019050394A (en) * | 2018-10-31 | 2019-03-28 | 株式会社半導体エネルギー研究所 | Semiconductor device and electronic apparatus |
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