JPH03196021A - Matrix type display device - Google Patents

Matrix type display device

Info

Publication number
JPH03196021A
JPH03196021A JP1337895A JP33789589A JPH03196021A JP H03196021 A JPH03196021 A JP H03196021A JP 1337895 A JP1337895 A JP 1337895A JP 33789589 A JP33789589 A JP 33789589A JP H03196021 A JPH03196021 A JP H03196021A
Authority
JP
Japan
Prior art keywords
source
etching stopper
electrode
contact layer
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1337895A
Other languages
Japanese (ja)
Other versions
JP2711003B2 (en
Inventor
Hirokazu Sakamoto
阪本 弘和
Akira Kawamoto
川元 暁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP33789589A priority Critical patent/JP2711003B2/en
Publication of JPH03196021A publication Critical patent/JPH03196021A/en
Application granted granted Critical
Publication of JP2711003B2 publication Critical patent/JP2711003B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To simplify optimization of pretreatment conditions and to enhance product yield in a process by forming a second etching stopper made of a material substantially same as that of a semiconductor layer between a first etching stopper and a source-drain contact layer. CONSTITUTION:The second etching stopper 10 is formed between the first etching stopper 6 and the source-drain contact layer 7. The stopper 10 is made of a material substantially same as that of the semiconductor layer 5. In a buffered hydrofluoric acid (BHF) treatment to be executed after patterning the stoppers 6, 10 and before forming the source-drain contact layer 7, the surface of the semiconductor substrate 5 to be exposed the BHF solution is made of the same one material, thus permitting the optimization of the BHF treatment to be made easy, and the source-drain ohmic contact layer 7 to be formed with close adhesiveness improved.

Description

【発明の詳細な説明】 〔庁業上の利用分野〕 この発明は、マトリックス型表示装置に関し、特に薄膜
トランジスタC以下、TPT上記す)アレイ基板及びそ
れを用いた表示装置の歩留向上に関するものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to matrix display devices, and particularly to improvement in yield of thin film transistor (hereinafter referred to as thin film transistor C), TPT (hereinafter referred to as above) array substrates, and display devices using the same. be.

〔従来の技術〕[Conventional technology]

マトリックス型表示装置は通常2枚の対向した基板の間
に液晶等の表示材料が挾持され、この表示材料に電圧を
印加する方法で構成される。この際、少くとも一方の基
板にマトリックス状に配列した画素電極を設け、これら
の画素を選択的に動作するために各画素毎にTPT等の
非線形特性を有する能動素子を設けている。
A matrix type display device is usually constructed by a method in which a display material such as a liquid crystal is sandwiched between two opposing substrates, and a voltage is applied to the display material. At this time, pixel electrodes arranged in a matrix are provided on at least one substrate, and an active element having nonlinear characteristics such as TPT is provided for each pixel in order to selectively operate these pixels.

従来のこの種の装置として特開昭63−221678号
公報に掲載されているものを第4図〜第6図に示す。第
4図は従来のマトリックス型表示装置を示す部分平面図
、第5図は第4図のv−v線断面図、第6図は製造途中
のものの断面図である。
A conventional device of this type, disclosed in Japanese Patent Application Laid-Open No. 63-221678, is shown in FIGS. 4 to 6. FIG. 4 is a partial plan view showing a conventional matrix type display device, FIG. 5 is a sectional view taken along the line v--v in FIG. 4, and FIG. 6 is a sectional view of a device in the process of being manufactured.

図において、(1)は透明絶縁性基板、(2)は画素電
極、(3)はゲート電極・配線、(4)はゲート絶縁膜
、(IIは半導体層、(6)はエツチングストッパー、
(7)ハソース・ドレインのオーミックコンタクト層、
(8)はソース1Ics・配線、(9)はドレイン電極
である。
In the figure, (1) is a transparent insulating substrate, (2) is a pixel electrode, (3) is a gate electrode/wiring, (4) is a gate insulating film, (II is a semiconductor layer, (6) is an etching stopper,
(7) Hasource/drain ohmic contact layer,
(8) is the source 1Ics/wiring, and (9) is the drain electrode.

この液晶表示装置を製造工程に基いて説明する。This liquid crystal display device will be explained based on the manufacturing process.

まず洗浄された透明絶縁性基板(1)上に、EB蒸着法
もしくはスパッタリング法により、ITO(Indiu
mTin 0xide)  等の透明導w1膵を成膜す
る。これをフォトエツチング法等の方法で所望のパター
ンに加工し、画素′R1極121及び電極端子等を形成
する。
First, on the cleaned transparent insulating substrate (1), ITO (Indiu
A transparent conducting w1 pancreas film such as mTin Oxide is deposited. This is processed into a desired pattern by a method such as photoetching to form the pixel 'R1 pole 121, electrode terminal, etc.

2番目にCr等の高融点金属をスパッタリング法等で成
膜し、同様の方法でゲート電極及び配線(3)等を形成
する。3番目にゲート絶縁膜+41として810!やS
iN、半導体層(5)として1−a−8iやpoli−
8!。
Second, a film of a high-melting point metal such as Cr is formed by sputtering or the like, and a gate electrode, wiring (3), etc. are formed by the same method. Thirdly, 810 as gate insulating film +41! YaS
iN, 1-a-8i or poli- as the semiconductor layer (5)
8! .

そしてエツチングストッパー(6)としての5s02や
SiNを連続的にプラズマC司法等で成膜する。4番目
にエツチングストッパー(6)にソース・ドレインコン
タクト用のコンタクトホールを形成し、バッフアートフ
ッ酸(BHF)溶液等で前処理後ソースドレインのオー
ミ゛ツクコンタクト層(7)としてのn”−a−8i 
 を成膜する。5番目に画素電極(2)と後に形成する
ドレイン電極(9)をつなぐためのコンタクトホールを
形成する。6番目にAI、 Ajt/Cr 。
Then, a film of 5S02 or SiN as an etching stopper (6) is continuously formed using a plasma C method or the like. Fourth, contact holes for source/drain contacts are formed in the etching stopper (6), and after pretreatment with buffered hydrofluoric acid (BHF) solution, etc., an n"- a-8i
Deposit a film. Fifth, a contact hole is formed to connect the pixel electrode (2) and the drain electrode (9), which will be formed later. 6th AI, Ajt/Cr.

Al /MoあるいはAt?合金等をスパッタリング法
等で成膜し、パターン加工してソース電極・配線(8)
及びドレイン電極(9)を形成する。以上の様にしてT
FTアレイ基板は形成される。このTFTアレイ基板に
対向して、透明導電膜及びカラーフィルタ等を設けた対
向電極基板を設け、この両者の間に液晶等を挾持して液
晶平面デイスプレィが構成される。
Al/Mo or At? A film of alloy etc. is formed by sputtering method etc. and patterned to form the source electrode/wiring (8)
and a drain electrode (9) is formed. As above, T
An FT array substrate is formed. A counter electrode substrate provided with a transparent conductive film, a color filter, etc. is provided opposite to this TFT array substrate, and a liquid crystal flat display is constructed by sandwiching a liquid crystal or the like between the two.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のマトリックス型表示装置は、上記の様にTFTア
レイ基板を形成する際、第6図に示されている状部のも
のに4番目の一−a−8!(7)を成膜する前に、その
表面を清浄化するためにBHF溶液等で前処理する。こ
の時この溶液にさらされる基板表面の膜はエツチングス
トッパー(6)である5iN(又はSin、)と半導体
層(5)である1−a−8i(又はPo1i−St )
の両方があり、この様な基板をBHF溶液等で前処理す
る際の条件の最適化が困難で、うまくオーεツクコンタ
クトがとれなかったり、n −a −s 1(7)がは
がれるといった問題点があった。
In the conventional matrix type display device, when forming the TFT array substrate as described above, the fourth 1-a-8! Before forming (7) into a film, the surface is pretreated with a BHF solution or the like in order to clean it. At this time, the films on the substrate surface exposed to this solution are 5iN (or Sin), which is an etching stopper (6), and 1-a-8i (or Po1i-St), which is a semiconductor layer (5).
Therefore, it is difficult to optimize the conditions when pre-treating such a substrate with a BHF solution, etc., resulting in problems such as not being able to make a good open contact or peeling off of n-a-s 1(7). There was a point.

この発明は上記のような問題点を解消するためになされ
たもので、ソース・ドレインコンタクト層(7)を形成
する前の、前処理する基板表面をできる限り単一の材質
になる様に構成し、前処理条件の最適化を簡単にし、こ
の工程の歩留を向上させることを目的とする。
This invention was made in order to solve the above-mentioned problems, and the surface of the substrate to be pretreated before forming the source/drain contact layer (7) is configured to be made of a single material as much as possible. The purpose is to simplify the optimization of pretreatment conditions and improve the yield of this process.

〔課題を解決するための手段〕[Means to solve the problem]

この発明ニ係るマトリックス型表示装置は、従来の第1
エツチングストッパーとソース−FL、インコンタクト
層の間に、半導体層の材料と実質的に[1−の材料によ
る第2エツチングストソバ−を有する構造としたもので
ある。
The matrix type display device according to the present invention is different from the conventional first one.
This structure has a second etching stopper made of a material substantially equal to the material of the semiconductor layer and the material of [1-] between the etching stopper, the source FL, and the in-contact layer.

〔作用〕[Effect]

この発明における第2エツチングストッパー1九半導体
層の材料と実質的に同一の材料で形成されており、エツ
チングストッパーのパターン加工後テソース・ドレイン
コンタクト層を形成スる前に施すBHF処理において、
BHF溶液にさらされる基板表面は単一の材料のものと
なり、B町処理の最適化が容易となり、さらにその後成
膜するソースドレインのオーミ゛ツクコンタクト層の密
着性を良好にする。
The second etching stopper in this invention is made of substantially the same material as the semiconductor layer 19, and in the BHF treatment performed after patterning the etching stopper and before forming the source/drain contact layer.
The substrate surface exposed to the BHF solution is made of a single material, which facilitates optimization of the B-layer process and improves the adhesion of the source-drain ohmic contact layer that is subsequently deposited.

〔実施例〕〔Example〕

第1図〜第3図はこの発明の一実施例によるマトリ゛ソ
クス型表示装置を示すもので、第1図はマトリ゛ソクス
型表示装置の部分平面図、第2図は第1図の璽−1線断
面図、第3図は製造途中の断面図である。第1図〜第3
図において、第4図〜第6図と同一符号は同一、又は相
当部分を示す。さらに、Q13 ハffi 2工ゝソチ
ングストツパーであり、以下その製造工程に基いて説明
する。
1 to 3 show a matrix type display device according to an embodiment of the present invention, FIG. 1 is a partial plan view of the matrix type display device, and FIG. -1 line sectional view and FIG. 3 are sectional views in the middle of manufacturing. Figures 1 to 3
In the figures, the same reference numerals as in FIGS. 4 to 6 indicate the same or corresponding parts. Furthermore, it is a Q13 Haffi 2-work soching stopper, and the manufacturing process thereof will be explained below.

まず透明絶縁性基板0にITOを臼蒸着法もしくはスパ
ッタリング法等で成膜し、これをフォトエツチング法等
でパターン加工し、画素電極(2)及び電極端子等を形
成する。2番目にCr等の高融点金属をスパッタ法等で
成膜し、パターン加工してゲート電極・配線(3)等を
形成する。3番目にゲート絶縁膜(4)としてのSiN
あるいは810!、半導体層(5)となるi−*−8i
もしくはpoli−8i、そして第1エツチングストッ
パー(6)となるSiNあるいは8*Ot。
First, an ITO film is formed on a transparent insulating substrate 0 by a mortar evaporation method, a sputtering method, or the like, and then patterned by a photoetching method or the like to form a pixel electrode (2), an electrode terminal, and the like. Second, a film of high-melting point metal such as Cr is formed by sputtering or the like, and patterned to form gate electrodes, wiring (3), and the like. Third, SiN as the gate insulating film (4)
Or 810! , i-*-8i which becomes the semiconductor layer (5)
or poli-8i, and SiN or 8*Ot which becomes the first etching stopper (6).

さらに第2エツチングストソバ−GOとしての1−1−
8iもしくはpoli−8iをプラズvCVD法等で連
続成膜する。4番目にソース・ドレインコンタクトホー
ルをml、第2エッチングヌトツパ−+61.GOにあ
ける。この後、BHF溶液等で前処理しソースドレイン
のオーミックコンタクト層(7)としてのn+−a−8
i  を成膜する。5番目に画素電極(1)とドレイン
電極(9)を接続するためのコンタクトホールを形成す
る。6番目にAI%AI/Cr、 Al1No あるい
はA1合金をスパッタリング法等で成膜し、フォトエツ
チング法等でパターン加工し、ソース電極・配線(8)
及びドレイン電極(9)を形成する。
Furthermore, 1-1- as a second etching soba-GO
8i or poli-8i is continuously formed into a film by plasma vCVD method or the like. Fourth, source/drain contact holes were formed by etching the second etching hole +61. Open it to GO. After this, the n+-a-8 is pretreated with a BHF solution etc. to form the source/drain ohmic contact layer (7).
Deposit i. Fifth, a contact hole is formed to connect the pixel electrode (1) and the drain electrode (9). Sixth, a film of AI%AI/Cr, Al1No or A1 alloy is formed by a sputtering method, etc., and patterned by a photoetching method, etc. to form a source electrode/wiring (8).
and a drain electrode (9) is formed.

以上の様にしてTFTアレイ基板は形成される。The TFT array substrate is formed in the manner described above.

このTFTアレイ基板に対向して、透明導電膜及びカラ
ーフィルタ等を設けtこ対向電極基板を設け、この両者
の開に液晶等の表示材料を挾持して液晶平面デイスプレ
ィが構成される。
Opposed to this TFT array substrate, a transparent conductive film, a color filter, etc. are provided, and a counter electrode substrate is provided, and a display material such as liquid crystal is sandwiched between the two to form a liquid crystal flat display.

以上の様な構成にした場合、4番目のソース・ドレイン
のオーミックコンタクト層(7)としてのn”−a−8
i  を成膜直前の前処理時において基板表面は第3図
に示されている様にほとんど第2工゛ソチングストツパ
ー〇〇と半導体層(5)の1−a−81(あるいはpo
li−8i )でおおわれているため、前処理の制御が
容易になりそのマージンが広がる。その結果n−a−8
i  と1−a−8iのオーミツクコンククトが良好に
均一になt) 、 ts”−a−8iがはがれるといっ
たこともないので、高歩留で高品質のTFTアレイが提
供できる。
In the case of the above structure, the n"-a-8 as the fourth source/drain ohmic contact layer (7)
During the pretreatment immediately before film formation, the substrate surface is almost completely covered with the second process sowing stopper 〇〇 and semiconductor layer (5) 1-a-81 (or po
li-8i), the preprocessing can be easily controlled and its margin widened. As a result na-8
Since the ohmic contact between i and 1-a-8i is well uniform and there is no possibility that ts''-a-8i is peeled off, a high-quality TFT array can be provided with a high yield.

なお、各材料は上記実施例に限るものではない。In addition, each material is not limited to the above-mentioned example.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、透明絶縁性基板に1
画素電極、ゲート電極、ゲート絶縁膜、半導体71.第
1工1ソ手ングストッパー ソース・ドレインコンタク
ト層、ソース電極・配線及びドレイン電極を順に載置す
る薄膜トランジスタ(TF’I’ )アレイ基板、並び
に透明電極及びカラーフィルターを有する対向電極基板
を備え、TFTアレイ基板と対向電極基板との間に表示
材料を挾持してなるマトリックス型表示装置において、
第1エツチングスト・ソバ−とソース・ドレインコンタ
クト層の間に、半導体層の材料と実質的に同一の材料に
よる第2エツチングストソバ−を有する構造としたこと
により、ソース・ドレインコンタクト層の密着力が向上
でキ、亮歩留で高品質のマトリックス型表示装置が提供
できる効果がある。
As described above, according to the present invention, the transparent insulating substrate has one
Pixel electrode, gate electrode, gate insulating film, semiconductor 71. 1st process 1st hand stopper comprising a source/drain contact layer, a thin film transistor (TF'I') array substrate on which a source electrode/wiring, and a drain electrode are placed in order, and a counter electrode substrate having a transparent electrode and a color filter; In a matrix display device in which a display material is sandwiched between a TFT array substrate and a counter electrode substrate,
By adopting a structure in which a second etching stopper made of substantially the same material as the semiconductor layer is provided between the first etching stopper and the source/drain contact layer, the source/drain contact layer can be tightly bonded. This has the effect of providing a high quality matrix type display device with improved power and improved yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例によるマド11ツクス型表
示装置に用いられるTFTアレイ基板の要部を示す平面
図、第2図は第1図の11線断面図、第3図は製造途中
の断面図、第4図は従来のマトリックス型表示装置に用
いられるTFTアレイ基板の要部を示す平面図、第5図
は第4図のV−マ線断面図、第6図は製造途中の断面図
である。 (1)は透明絶縁性基板、121は画素電極、(3)は
ゲート電極・配線、(4)はゲート絶縁膜、(5)は半
導体層。 (6)は第1エツチングストソバ−1(7)はソース・
ドレインコンタクト層、(8)はソース電極・配線、(
9)ハトレイン1t8i、O・は第2工゛ソチングスト
ツパーである。 なお、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a plan view showing the main parts of a TFT array substrate used in a multilayer display device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line 11 in FIG. 1, and FIG. 4 is a plan view showing the main parts of a TFT array substrate used in a conventional matrix type display device, FIG. 5 is a sectional view taken along the line V in FIG. 4, and FIG. FIG. (1) is a transparent insulating substrate, 121 is a pixel electrode, (3) is a gate electrode/wiring, (4) is a gate insulating film, and (5) is a semiconductor layer. (6) is the first etching saucer and (7) is the sauce.
Drain contact layer, (8) source electrode/wiring, (
9) Hat train 1t8i, O. is the second process sawing stopper. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 透明絶縁性基板に、画素電極、ゲート電極、ゲート絶縁
膜、半導体層、第1エッチングストッパー、ソース・ド
レインコンタクト層、ソース電極・配線及びドレイン電
極を順に載置する薄膜トランジスタ(TFT)アレイ基
板、並びに透明電極及びカラーフィルターを有する対向
電極基板を備え、上記TFTアレイ基板と上記対向電極
基板との間に表示材料を挾持してなるマトリックス型表
示装置において、第1エッチングストッパーと上記ソー
ス・ドレインコンタクト層の間に、上記半導体層の材料
と実質的に同一の材料による第2エッチングストッパー
を有する構造としたことを特徴とするマトリックス型表
示装置。
A thin film transistor (TFT) array substrate, in which a pixel electrode, a gate electrode, a gate insulating film, a semiconductor layer, a first etching stopper, a source/drain contact layer, a source electrode/wiring, and a drain electrode are sequentially placed on a transparent insulating substrate; A matrix type display device comprising a counter electrode substrate having a transparent electrode and a color filter, and a display material sandwiched between the TFT array substrate and the counter electrode substrate, the first etching stopper and the source/drain contact layer. A matrix type display device characterized in that it has a structure in which a second etching stopper made of substantially the same material as the material of the semiconductor layer is provided between the layers.
JP33789589A 1989-12-25 1989-12-25 Matrix type display device Expired - Fee Related JP2711003B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33789589A JP2711003B2 (en) 1989-12-25 1989-12-25 Matrix type display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33789589A JP2711003B2 (en) 1989-12-25 1989-12-25 Matrix type display device

Publications (2)

Publication Number Publication Date
JPH03196021A true JPH03196021A (en) 1991-08-27
JP2711003B2 JP2711003B2 (en) 1998-02-10

Family

ID=18313011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33789589A Expired - Fee Related JP2711003B2 (en) 1989-12-25 1989-12-25 Matrix type display device

Country Status (1)

Country Link
JP (1) JP2711003B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0836192A (en) * 1994-07-21 1996-02-06 Nec Corp Active matrix substrate and its production
JP2010147303A (en) * 2008-12-19 2010-07-01 Mitsubishi Electric Corp Thin-film transistor, method of manufacturing the same, thin-film transistor array substrate, and display device
JP2011205105A (en) * 2011-04-22 2011-10-13 Casio Computer Co Ltd Thin film transistor and method of manufacturing the same
JP2012093707A (en) * 2010-10-22 2012-05-17 Samsung Mobile Display Co Ltd Display device and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
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JPH0836192A (en) * 1994-07-21 1996-02-06 Nec Corp Active matrix substrate and its production
JP2010147303A (en) * 2008-12-19 2010-07-01 Mitsubishi Electric Corp Thin-film transistor, method of manufacturing the same, thin-film transistor array substrate, and display device
JP2012093707A (en) * 2010-10-22 2012-05-17 Samsung Mobile Display Co Ltd Display device and method for manufacturing the same
JP2011205105A (en) * 2011-04-22 2011-10-13 Casio Computer Co Ltd Thin film transistor and method of manufacturing the same

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