JPH03194516A - Liquid crystal display element - Google Patents

Liquid crystal display element

Info

Publication number
JPH03194516A
JPH03194516A JP1335537A JP33553789A JPH03194516A JP H03194516 A JPH03194516 A JP H03194516A JP 1335537 A JP1335537 A JP 1335537A JP 33553789 A JP33553789 A JP 33553789A JP H03194516 A JPH03194516 A JP H03194516A
Authority
JP
Japan
Prior art keywords
electrode
pixel electrode
gate
electrodes
gap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1335537A
Other languages
Japanese (ja)
Other versions
JP2714650B2 (en
Inventor
Yasuhiro Ukai
育弘 鵜飼
Tomihisa Sunada
富久 砂田
Masaru Yasui
勝 安居
Teizo Yugawa
湯川 禎三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hosiden Corp
Original Assignee
Hosiden Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hosiden Corp filed Critical Hosiden Corp
Priority to JP33553789A priority Critical patent/JP2714650B2/en
Priority to KR1019900015632A priority patent/KR940005124B1/en
Priority to US07/592,272 priority patent/US5042916A/en
Priority to EP90118978A priority patent/EP0421386B1/en
Priority to DE69020288T priority patent/DE69020288T2/en
Priority to EP94111000A priority patent/EP0621503A3/en
Publication of JPH03194516A publication Critical patent/JPH03194516A/en
Application granted granted Critical
Publication of JP2714650B2 publication Critical patent/JP2714650B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To remedy a defective picture element without changing the brightness of picture element when the insulation of the additive capacitance part is deteriorated by forming the first and second electrodes and third electrode to be laser- welded on the upper surface opposed with a gap formed in any of comb-shaped electrodes in between. CONSTITUTION:The extension 15b of a picture element electrode 15 is formed with plural comb-shaped electrodes 15b1, 15b2 and 15b3, and a part of the electrode 15b1 in contact with the picture element electrode is cut off to form a gap 40. A capacitance is formed with capacitors C1, C2 and C3 between the comb-shaped electrode and a gate bus 18. Even if the insulation of any of the divided additive capacitances, i.e., C2 or C3, is deteriorated, the bridging part 32 of the defective capacitor is laser-cut, the first electrode 41 and the third electrode 43 and the second electrode 42 and the third electrode 43 are electrically connected by laser welding, an additive capacitance C1a is formed between the electrode 15b1 and the gate bus 18, and the additive capacitance after repairing is adjusted approximately to the normal value.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は液晶表示素子に関し、特にその画素電極と接
続される付加容量部の構成に関する。
DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a liquid crystal display element, and more particularly to the configuration of an additional capacitance section connected to a pixel electrode thereof.

「従来の技術」 従来の液晶表示素子を第4図を参照して説明する。ガラ
スのような透明基4Ii、ll及び12が近接対向して
設けられ、その周縁部にはスペーサ13が介在され、こ
れら透明基板11.12間に液晶14が封入されている
。一方の透明基板11の内面に画素電極I5が複数形成
され、これら各画素電極15に接してそれぞれスイッチ
ング素子としてT F T″(薄11タトランジスタ)
16が形成され、そのTPT I 6のトレインは画素
電極15に接続されている。これら複数の1iTii素
電極15と対向して他方の透明基板12の内面に透明な
共通電極17が形成されている。
"Prior Art" A conventional liquid crystal display element will be explained with reference to FIG. Transparent substrates 4Ii, 11 and 12 such as glass are provided in close opposition to each other, a spacer 13 is interposed at the peripheral edge thereof, and a liquid crystal 14 is sealed between these transparent substrates 11 and 12. A plurality of pixel electrodes I5 are formed on the inner surface of one transparent substrate 11, and in contact with each pixel electrode 15, a T F T'' (thin 11 transistor) is connected as a switching element.
16 is formed, and its TPT I 6 train is connected to the pixel electrode 15. A transparent common electrode 17 is formed on the inner surface of the other transparent substrate 12, facing the plurality of 1iTii elementary electrodes 15.

画素電極15は第5図に示すように、透明基板ll上に
ほぼ正方形の画素電極I5が行及び列に近接配列されて
おり、画素電極I5の各行配列と近接し、かつこれに沿
ってそれぞれゲートバス】8が形成され、また画素電極
15の各列配列と近接してそれに沿ってソースハス19
がそれぞれ形成されている。これら各ゲートバス18及
びソースバス19の交差点においてTFT16が設けら
れ、各T F T 16のゲートは両バスの交差点位置
においてゲートバス18に接続され、各ソースはソース
バス19にそれぞれ接続され、更に各ドレインは画素電
極15に接続されている。
As shown in FIG. 5, the pixel electrode 15 has substantially square pixel electrodes I5 arranged in close proximity to each other in rows and columns on a transparent substrate 11, and is arranged in close proximity to each row arrangement of pixel electrodes I5 and along this. A gate bus 8 is formed, and a source bus 19 is formed adjacent to and along each column arrangement of pixel electrodes 15.
are formed respectively. A TFT 16 is provided at the intersection of each gate bus 18 and source bus 19, the gate of each TFT 16 is connected to the gate bus 18 at the intersection of both buses, each source is connected to the source bus 19, and Each drain is connected to a pixel electrode 15.

これらゲートバス18とソースバス19との各−つを選
択してそれら間に電圧を印加し、その電圧が印加された
TFT I 6のみが導通し、その導通したTFT16
のドレインに接続された画素型Fi15に電荷を蓄積し
て画素電極15と共通電極17との間の液晶14の部分
においてのみ電圧を印加し、これによって画素電極15
の部分のみを光透明或は光遮断とすることによって選択
的な表示を行う。この画素電極■5に蓄積した電荷を放
電させることによって表示を消去させることができる。
By selecting each of these gate buses 18 and source buses 19 and applying a voltage between them, only the TFT I 6 to which the voltage has been applied becomes conductive, and the TFT 16 that has become conductive becomes conductive.
Charge is accumulated in the pixel-type Fi 15 connected to the drain of the pixel electrode 15, and a voltage is applied only to the portion of the liquid crystal 14 between the pixel electrode 15 and the common electrode 17.
Selective display is performed by making only the portion transparent or blocked. The display can be erased by discharging the charges accumulated in the pixel electrode 5.

第6図乃至第8図は既に提案されている液晶表示素子で
ある。透明基板11上に画素電極15とソースバス19
とがITOのような透明導電膜によって形成され、画素
電極15及びソースバスI9の互に平行近接した部分間
にまたがってアモルファスシリコンのような半導体層2
1が形成され、更にその上に窒化シリコンなどのゲート
絶縁膜22が形成される。このゲート絶縁膜22上にお
いて半導体層21を介して画素電極15及びソースバス
19とそれぞそれ一部重なってゲート電極23が形成さ
れる。ゲート電極23の一端はゲートバス18に接続さ
れる。このようにしてゲート電極23とそれぞれ対向し
た画素電極I5、ソースハスL9はそれぞれトルレイン
電Fil 5 a、ソース電極19aを構成し、これら
電極15a、19a、半導体層21、ゲート絶縁膜22
、ゲート電極23によってTFT16が構成される。ゲ
ート電極23及びゲートハス18は同時に形成され、例
えばアルミニウムによって構成される。液晶に対する保
護のためにゲート電極23上に全体を覆って保護層29
が形成されている。
6 to 8 show liquid crystal display elements that have already been proposed. A pixel electrode 15 and a source bus 19 are arranged on a transparent substrate 11.
are formed of a transparent conductive film such as ITO, and a semiconductor layer 2 such as amorphous silicon is formed between parallel and adjacent portions of the pixel electrode 15 and the source bus I9.
1 is formed, and a gate insulating film 22 made of silicon nitride or the like is further formed thereon. A gate electrode 23 is formed on the gate insulating film 22 so as to partially overlap the pixel electrode 15 and the source bus 19 with the semiconductor layer 21 interposed therebetween. One end of the gate electrode 23 is connected to the gate bus 18. In this way, the pixel electrode I5 and the source layer L9, which respectively face the gate electrode 23, constitute a torlein electrode Fil 5a and a source electrode 19a, respectively, and these electrodes 15a, 19a, the semiconductor layer 21, and the gate insulating film 22
, the gate electrode 23 constitutes the TFT 16. The gate electrode 23 and the gate lotus 18 are formed at the same time and are made of aluminum, for example. A protective layer 29 is provided to completely cover the gate electrode 23 for protection against the liquid crystal.
is formed.

第8図に示すように、画素電極】5の一端部は、隣接す
るゲートバス18の下側において、ゲートバス18のほ
ぼ中間位置まで延長されてそのゲートバス18との間に
付加容量部30が形成される。
As shown in FIG. 8, one end of the pixel electrode 5 is extended below the adjacent gate bus 18 to approximately the middle position of the gate bus 18, and an additional capacitance portion 30 is formed between the pixel electrode 5 and the gate bus 18. is formed.

この付加容量は画素電極部の静電容量を補ってTFT1
6のチャンネル部の抵抗値とで作る時定数を大きくする
ために必要とされる。
This additional capacitance supplements the capacitance of the pixel electrode section and
This is necessary in order to increase the time constant created by the resistance value of the channel section No. 6.

付加容量部は複数分割される。@素電極の延長部15b
は、ゲートバスの幅方向の中間位置に重ねられて島状に
形成され、橋絡片32により画素電極15に連結されて
成る樽の歯状電極15b115b2,15b3で構成さ
れる。これらの櫛の歯状電極とゲートバス18との間に
形成される静電容量が第5図に示すコンデンサC,,C
,、C。
The additional capacitor section is divided into multiple parts. @Extension part 15b of elementary electrode
is formed of barrel tooth-shaped electrodes 15b115b2 and 15b3, which are stacked in an island shape at an intermediate position in the width direction of the gate bus and connected to the pixel electrode 15 by a bridging piece 32. The capacitance formed between these comb-like electrodes and the gate bus 18 is the capacitor C, , C shown in FIG.
,,C.

である、この分割されたいずれがの付加容量部3゜にお
いて、ゲートバス18と櫛の歯状電極との間のゲート絶
縁膜22にピンホールが発止したり、製造プロセスの途
中で塵埃が混入すると、両電極間に絶縁低下や短絡が発
止することがある。このような付加容量部の不良によっ
て、表示素子内のいくつかの画素は表示すべき映像信号
とは無関係に、常にオン(点灯)の状態となり、表示品
位を低下させる。そこでこの不良となった付加容量部(
分割部)を削除することが行われる。即ち、第4図の透
明基板12側からレーザー光線を照射し、不良付加容量
部30における橋絡片32の画素電極の近傍に2〜lO
μmの焦点を結ばせ、カッティングして画素電極15か
ら切り離す。
In either of the divided additional capacitance parts 3°, pinholes may occur in the gate insulating film 22 between the gate bus 18 and the comb tooth-shaped electrodes, or dust may form during the manufacturing process. If mixed, insulation may deteriorate or a short circuit may occur between both electrodes. Due to such a defect in the additional capacitance section, some pixels in the display element are always turned on (lit) regardless of the video signal to be displayed, degrading the display quality. Therefore, this defective additional capacitance section (
The division part) is deleted. That is, a laser beam is irradiated from the side of the transparent substrate 12 in FIG.
It is focused in μm and separated from the pixel electrode 15 by cutting.

「発明が解決しようとする課題」 従来提案されている液晶表示素子では、不良となった付
加容量部30の1つの分割部をレーザカントすると、付
加容量部の容量値が設定値の273に減少してしまう。
"Problem to be Solved by the Invention" In conventionally proposed liquid crystal display elements, when one divided part of the defective additional capacitor section 30 is laser canted, the capacitance value of the additional capacitor section decreases to the set value of 273. Resulting in.

このため画素電極の共通電極に対する電位が設定値より
ずれることになり、画素の輝度が変化を受ける。単純な
白黒表示を行う場合にはあまり問題にならないが、高品
位な多階調表示を行う場合には、画素の階調がずれてし
まい、表示品位を劣化させる。
Therefore, the potential of the pixel electrode relative to the common electrode deviates from the set value, and the brightness of the pixel changes. This is not much of a problem when performing a simple monochrome display, but when performing a high-quality multi-gradation display, the gradations of pixels are shifted, deteriorating the display quality.

この発明の目的は、付加容量部が絶縁不良となった場合
に、画素の輝度に変化を与えない方法で不良画素を救済
できるようにしようとするものである。
An object of the present invention is to make it possible to repair a defective pixel by a method that does not cause a change in the brightness of the pixel when an insulation failure occurs in the additional capacitance section.

「課題を解決するための手段」 透明基板上に複数のソースバスと複数のゲートバスとが
互いに直交する方向に、それぞれ等間隔に形成され、そ
れら各交叉点位置と対応してその交叉するソースバス及
びゲートバスに接続された薄膜トランジスタが上記ソー
スバスとゲートバスとで囲まれた網目内の一角に形成さ
れ、そのトランジスタのドレイン電極と接続される画素
電極が上記綱目内に広く形成され、その画素電極の端部
が隣接する薄膜トランジスタの接続されるゲートバスの
下側に重なるように延長され、上記ゲートバスの下面と
接して、上記画素電極及びその延長部を覆うようにゲー
ト絶縁膜が一様に形成され、上記延長部とその延長部と
対向する上記ゲートバスとの間に付加容量部が形成され
ている液晶表示素子において、この発明では、 上記画素電極の延長部が複数の櫛の歯状電極で構成され
、 それらの櫛の歯状電極のいずれか一つにおいて、上記画
素電極と接する電極の一部が欠如されて、ギャップ部が
形成され、 そのギャップ部を挟んで対向する上記櫛の歯状電極及び
画素電極のギャップ部側の上面にレーザウェルド用の第
1.第2電極がそれぞれ形成され、それら第1.第2電
極を覆うと共に上記ギャップ部を埋めるように上記ゲー
ト絶縁膜が形成され、そのゲート絶縁膜上に、上記第1
.第2電極及び上記ギャップ部の一部と重なって、レー
ザウェルド用の第3電極が形成される。
"Means for Solving the Problem" A plurality of source buses and a plurality of gate buses are formed on a transparent substrate at equal intervals in directions perpendicular to each other, and the sources that intersect are arranged in correspondence with the positions of their respective intersection points. A thin film transistor connected to the bus and the gate bus is formed in one corner of the mesh surrounded by the source bus and the gate bus, and a pixel electrode connected to the drain electrode of the transistor is formed widely within the mesh. An end of the pixel electrode is extended so as to overlap the lower side of a gate bus to which an adjacent thin film transistor is connected, and a gate insulating film is provided so as to be in contact with the lower surface of the gate bus and cover the pixel electrode and its extension. In the liquid crystal display element in which an additional capacitance portion is formed between the extension portion and the gate bus facing the extension portion, in the present invention, the extension portion of the pixel electrode is formed by a plurality of combs. In one of the comb tooth-like electrodes, a part of the electrode in contact with the pixel electrode is missing to form a gap, and the above-mentioned electrodes facing each other across the gap are The first comb electrode for laser welding is attached to the upper surface of the gap side of the comb tooth electrode and the pixel electrode. Second electrodes are formed respectively, and the first and second electrodes are formed respectively. The gate insulating film is formed to cover the second electrode and fill the gap, and the first electrode is formed on the gate insulating film.
.. A third electrode for laser welding is formed overlapping the second electrode and a portion of the gap portion.

「実施例」 この発明の実施例を第1図乃至第3図を参照して説明す
る。これらの図には第4図乃至第8図と対応する部分に
は同じ符号を付し、重複説明を省略する。この実施例で
は櫛の歯状電極15blにおいて、橋絡片32の画素電
極15と接する電極の一部が欠如されて、ギャップ部4
0が形成される。そのギャップ部40が形成された橋絡
片32と画素電極15とのギャップ部40を挟んで対向
する側の各上面に、レーザウェルド用の高融点金属(例
えばクロム、モリブデン等)より成る第1゜第2電極4
1.42がそれぞれ形成される。この高融点金属は、よ
く知られているところの、ソースバスの抵抗値を下げる
ためにその上に積層される高融点材料と同じものでよく
、それと同じ工程でパターニングされる。それら第1.
第2電極41.42を覆うと共にギャップ部40を埋め
るようにゲート絶縁膜22が堆積される。そのゲート絶
縁膜22上に、第1.第2電極41.42及びギャップ
部40の一部と重なって、レーザウェルド用の第3電極
43が形成される。この第3電極43はゲートバス18
と同じ材料(例えばアルミ)を用いて、ゲートバス18
と同時にパターニングされる。
"Embodiment" An embodiment of the present invention will be described with reference to FIGS. 1 to 3. In these figures, parts corresponding to those in FIGS. 4 to 8 are designated by the same reference numerals, and redundant explanation will be omitted. In this embodiment, in the comb tooth-shaped electrode 15bl, a part of the bridging piece 32 that is in contact with the pixel electrode 15 is missing, and the gap portion 4
0 is formed. A first plate made of a high melting point metal (for example, chromium, molybdenum, etc.) for laser welding is provided on each upper surface of the bridging piece 32 where the gap portion 40 is formed and the pixel electrode 15 on opposite sides across the gap portion 40.゜Second electrode 4
1.42 are formed respectively. This high melting point metal may be the same as the well-known high melting point material that is laminated on top of the source bus in order to lower its resistance value, and is patterned in the same process. The first of them.
A gate insulating film 22 is deposited to cover the second electrodes 41 and 42 and to fill the gap portion 40. On the gate insulating film 22, the first. A third electrode 43 for laser welding is formed overlapping the second electrodes 41 and 42 and a portion of the gap portion 40. This third electrode 43 is connected to the gate bus 18
using the same material (e.g. aluminum) as the gate bus 18.
patterned at the same time.

櫛の歯状電極15b1とゲートバス18との間にはコン
デンサCImが形成される。また、第1゜第2電極41
.42と第3電極43との間にそれぞれコンデンサC1
k及びC+Cが形成される。これら3個のコンデンサは
第2図に示すように、直列に接続される。各コンデンサ
の容量値を表わすのにコンデンサの符号をそのまま流用
すればC1C1,C,h  C1c 簡単化のため C1,夕CIc (2) とすれば、 C,C,、C,、/2 櫛の歯状電極15 b 2,15 b 3とゲートバス
18との間には従来と同様に、コンデンサCz。
A capacitor CIm is formed between the comb tooth-shaped electrode 15b1 and the gate bus 18. In addition, the first and second electrodes 41
.. 42 and the third electrode 43, each capacitor C1
k and C+C are formed. These three capacitors are connected in series as shown in FIG. If we use the symbols of the capacitors as they are to express the capacitance value of each capacitor, we will get C1C1,C,h C1c For simplicity, we will use C1, and CIc (2) If we use C1, C1, C1c (2), then C, C,, C,, /2 Comb's A capacitor Cz is provided between the toothed electrodes 15b2, 15b3 and the gate bus 18, as in the conventional case.

C3がそれぞれ形成される。第2図へには1つの画素と
その周囲の等価回路を示しである。
C3 is formed respectively. FIG. 2 shows one pixel and its surrounding equivalent circuit.

コンデンサC2及びそC1についても簡単化のため静電
容量値を共にCに設定する。
The capacitance values of both capacitors C2 and C1 are set to C for simplicity.

C,=C,=C (4) 付加容量値を01で表わせば、 C,=C,+2C(5) となる。C,=C,=C (4) If the additional capacitance value is expressed as 01, C,=C,+2C(5) becomes.

コンデンサC3がショートした場合には、櫛の歯状電極
15b3の橋絡片32の画素電極15の近傍を、第3図
へに切断部44で示すようにレーザカットする。また、
第3図の透明基Fi12又は!■側から、第3電極43
及びそれと対向する第1電極41及び第2電極42の各
中央部(第1図AにX印で示す位置)にレーザウエルグ
(レーザビームを利用した溶接機)によってレーザビー
ムを照射することにより、第3図Bに示すように対向す
る両電極間を溶融した金属45又は46によって電気的
に接続する。この結果コンデンサC1m及びC1(はシ
ョートされ、合成容量C,−C,、となり、付加容量は
c、′=c+c、、となる。この修理後の付加容IC↑
’=C十〇、、を正常時の(5)式の付加容量値CT=
C+ +2Cにほぼ等しく設定する必要がある。従って (C,′=)C+C,、−C,+2C(=C,)  (
6)一方、コンデンサC1mがショートした場合にも、
その時の付加容量値Cy”=C+b/2+2Cが正常時
の付加容量値C7にほぼ等しくなるように設定する必要
がある。従って (Ct”=)Ctb/2+2 C=C,+2C(=CT
)(7)(7)式より、 c + = c +bi2(8) (8)式と(3)式とから C111−ω (9) となる。実用的には cl、 >> C+b/2        (9’ )
であればよい。(6)弐より、 C,1l−C,l−C(6’ ) (6′)式に(8)式を代入すれば、 C、、+= C+b/2+ CQω となる。
If the capacitor C3 is short-circuited, the bridging piece 32 of the comb tooth-shaped electrode 15b3 near the pixel electrode 15 is laser-cut as shown by the cut portion 44 in FIG. Also,
The transparent group Fi12 in FIG. 3 or! ■From the side, the third electrode 43
By irradiating a laser beam with a laser weld (a welding machine that uses a laser beam) to the center portions of the first electrode 41 and the second electrode 42 (positions indicated by X marks in FIG. 1A) facing the first electrode 41 and the second electrode 42, As shown in FIG. 3B, the two opposing electrodes are electrically connected by molten metal 45 or 46. As a result, capacitors C1m and C1 (are short-circuited, resulting in a combined capacitance C, -C, , and the additional capacitance becomes c,'=c+c, .) After this repair, the additional capacitor IC ↑
'=C10, , is the additional capacitance value CT of equation (5) at normal time=
It should be set approximately equal to C+ +2C. Therefore (C,'=)C+C,, -C,+2C(=C,) (
6) On the other hand, if capacitor C1m is short-circuited,
It is necessary to set the additional capacitance value Cy"=C+b/2+2C at that time to be approximately equal to the additional capacitance value C7 during normal operation. Therefore, (Ct"=)Ctb/2+2 C=C, +2C(=CT
)(7) From equation (7), c + = c + bi2 (8) From equation (8) and equation (3), it becomes C111-ω (9). Practically speaking, cl, >> C+b/2 (9')
That's fine. (6) From 2, C, 1l-C, l-C(6') If we substitute equation (8) into equation (6'), we get C,,+=C+b/2+CQω.

分り易いように数値例をあげて説明しよう、いま、C+
b=0.5ppとすれば、(9′)式よりC,、>>0
.25pFでなければならない、そこで00式を考慮し
て、C= 1. OpFとすれば、C,、=0.25+
1.0 =1.25pFさ1.29Fとなり、(9′)
式を粗い近値で満足できる。よって、C+−=0.5、
C= 1.0、C+a”’1.2pFに設定する8合成
容量 c +は(8)式よりC+ = C+b/2= 
0.25ρFとなるが、上記各コンデンサの容量値は近
位的なものであるので、Cは(3)式より正確に求た方
がよく、 となる、またcf、Cr’、Cr”をそれぞれ(5)。
Let me explain by giving a numerical example to make it easier to understand.
If b=0.5pp, then from equation (9'), C, >>0
.. Must be 25pF, so considering equation 00, C=1. If it is OpF, C,,=0.25+
1.0 = 1.25pF becomes 1.29F, (9')
The equation can be satisfied with a rough approximation. Therefore, C+-=0.5,
The 8 combined capacitance c + is set to C= 1.0, C+a'''1.2 pF as follows from formula (8): C+ = C+b/2=
0.25ρF, but since the capacitance values of each of the above capacitors are proximal, it is better to find C more accurately than equation (3), and cf, Cr', Cr'' (5) respectively.

(6)及び(7)式より求めれば Ct −C++2C=0.21+ 2 X 1 =2.
21pF   Q21CT ’ =C+C1,= 1 
+1.20=2.20pF   O■Ct ” =C+
b/2+2C=0.25+2 =2.25pF   0
41となり、修理後の付加容I CT ’及びC1,シ
ョート後の付加容量Cア゛共正常な付加容Icyにほぼ
等しいことが分る。
If calculated from equations (6) and (7), Ct −C++2C=0.21+ 2 X 1 =2.
21pF Q21CT' =C+C1,=1
+1.20=2.20pF O■Ct ” =C+
b/2+2C=0.25+2 =2.25pF 0
41, and it can be seen that the additional capacitances ICT' and C1 after the repair, and the additional capacitance C after the short circuit are almost equal to the normal additional capacitance Icy.

これ迄の説明では、付加容量部30の櫛の歯状電極15
bl、15b2.15b3にはそれぞれ画素電極15側
に幅の狭い橋絡片32を持ち、くびれた形状であるとし
たが、この発明はこの形状に限るものではなく、任意の
形状でよい0例えば、最も簡単な形状としてくびれのな
い矩形杖の櫛の歯状電極としてもよい。上述と同様に第
1乃至第3 @極の形状も任意でよい、また櫛の歯状電
極も3個に限らず、複数個であればよい。
In the explanation up to this point, the comb tooth-shaped electrode 15 of the additional capacitance section 30 has been described.
bl, 15b2, and 15b3 each have a narrow bridging piece 32 on the pixel electrode 15 side and have a constricted shape, but the present invention is not limited to this shape, and any shape may be used.For example, The simplest shape may be a rectangular cane comb-like electrode without constriction. Similarly to the above, the shapes of the first to third @poles may be arbitrary, and the number of comb tooth-shaped electrodes is not limited to three, but may be a plurality.

「発明の効果J この発明によれば、分割された付加容量のIっCt又は
C1のいずれかが絶縁不良になったとしても、その不良
コンデンサの橋絡部32をレーザカットして切断し、そ
の代りに、第1電極と第3電極間及び第2電極と第3電
極間をレーザウエルグにより導通させ、櫛の歯状電極1
5blとゲートバス18との間で作られる付加容1c、
、を加えることによって修理後の付加容1ffiftl
!を正常時の値にほぼ等しくすることができる。
"Effect of the Invention J According to this invention, even if either of the divided additional capacitors ICt or C1 has an insulation defect, the bridging portion 32 of the defective capacitor is cut by laser cutting, Instead, conduction is made between the first electrode and the third electrode and between the second electrode and the third electrode by laser welding, and the comb tooth-shaped electrode 1
Additional capacity 1c created between 5bl and gate bus 18,
, the additional capacity after repair is 1ffiftl by adding
! can be made almost equal to the normal value.

また、付加容IC,,がショートしたとしても、全付加
容量値は特別の修理を行うことなく正常時の値にほぼ等
しくできる。
Further, even if the additional capacitance IC, .

従って上記いずれの場合にも、対応する画素の輝度は正
常な画素とほとんど変化はなく、優れた多段調表示が可
能である。
Therefore, in any of the above cases, the brightness of the corresponding pixel is almost the same as that of a normal pixel, and excellent multi-level tone display is possible.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A及びBはそれぞれこの発明の実施例の要部を示
す平面図及びB−B断面図、第2図は第1図の画素電極
15を囲む要部の電気的等価回路図、第3図Aは第1図
の櫛の歯状電極15b3とゲートバス18との間に絶縁
不良があった場合に、櫛の歯状電極15b3をレーザカ
ットにより画素電極15より分離させた状態を示す平面
図、第3図Bは、レーザウエルグにより第3図Aの第1
電極41と第3電極43との間及び第2電極42と第3
電極43との間を電気的に接続した状態を示すための第
3図AのB−B断面図、第4図は液晶表示素子の一部の
断面図、第5図は液晶表示素子の等価回路図、第6図は
既に提案されている液晶表示素子の要部の平面図、第7
図は第6図のAA断面図、第8図は第6図のB−B断面
図である。
1A and 1B are a plan view and a sectional view taken along the line B-B showing the main parts of an embodiment of the present invention, respectively. FIG. 2 is an electrical equivalent circuit diagram of the main parts surrounding the pixel electrode 15 in FIG. 3A shows a state in which the comb tooth electrode 15b3 is separated from the pixel electrode 15 by laser cutting when there is an insulation failure between the comb tooth electrode 15b3 and the gate bus 18 in FIG. The plan view, FIG. 3B, is the same as the first one in FIG.
Between the electrode 41 and the third electrode 43 and between the second electrode 42 and the third electrode 43
3A is a sectional view taken along line B-B of FIG. 3A to show the electrical connection between the electrode 43, FIG. 4 is a sectional view of a part of the liquid crystal display element, and FIG. 5 is an equivalent view of the liquid crystal display element. The circuit diagram, Figure 6 is a plan view of the main part of the liquid crystal display element that has already been proposed, and Figure 7 is
The figure is a sectional view along line AA in FIG. 6, and FIG. 8 is a sectional view taken along line BB in FIG.

Claims (1)

【特許請求の範囲】[Claims] (1)透明基板上に複数のソースバスと複数のゲートバ
スとが互いに直交する方向に、それぞれ等間隔に形成さ
れ、それら各交叉点位置と対応してその交叉するソース
バス及びゲートバスに接続された薄膜トランジスタが上
記ソースバスとゲートバスとで囲まれた網目内の一角に
形成され、そのトランジスタのドレイン電極と接続され
る画素電極が上記網目内に広く形成され、その画素電極
の端部が隣接する薄膜トランジスタの接続されるゲート
バスの下側に重なるように延長され、上記ゲートバスの
下面と接して、上記画素電極及びその延長部を覆うよう
にゲート絶縁膜が一様に形成され、上記延長部とその延
長部と対向する上記ゲートバスとの間に付加容量部が形
成されている液晶表示素子において、 上記画素電極の延長部が複数の櫛の歯状電極で構成され
、 それらの櫛の歯状電極のいずれか一つにおいて、上記画
素電極と接する電極の一部が欠如されて、ギャップ部が
形成され、 そのギャップ部を挟んで対向する上記櫛の歯状電極及び
画素電極のギャップ部側の上面にレーザウェルド用の第
1、第2電極がそれぞれ形成され、それら第1、第2電
極を覆うと共に上記ギャップ部を埋めるように上記ゲー
ト絶縁膜が形成され、そのゲート絶縁膜上に、上記第1
、第2電極及び上記ギャップ部の一部と重なって、レー
ザウェルド用の第3電極が形成されていることを特徴と
する、 液晶表示素子。
(1) A plurality of source buses and a plurality of gate buses are formed on a transparent substrate at equal intervals in directions orthogonal to each other, and are connected to the intersecting source buses and gate buses in correspondence with each intersection point position. A thin film transistor is formed in one corner of the mesh surrounded by the source bus and the gate bus, and a pixel electrode connected to the drain electrode of the transistor is formed widely within the mesh, and the edge of the pixel electrode is A gate insulating film is uniformly formed so as to overlap with the lower side of the gate bus to which adjacent thin film transistors are connected, and in contact with the lower surface of the gate bus, covering the pixel electrode and the extension thereof; In a liquid crystal display element in which an additional capacitance section is formed between an extension part and the gate bus facing the extension part, the extension part of the pixel electrode is constituted by a plurality of comb tooth-shaped electrodes, In any one of the tooth-like electrodes, a part of the electrode in contact with the pixel electrode is missing to form a gap, and the gap between the tooth-like electrode of the comb and the pixel electrode facing each other across the gap. First and second electrodes for laser welding are respectively formed on the upper surface of the part side, and the gate insulating film is formed to cover the first and second electrodes and fill the gap part. In the above 1st
A liquid crystal display element, characterized in that a third electrode for laser welding is formed overlapping the second electrode and a part of the gap portion.
JP33553789A 1989-10-04 1989-12-25 Liquid crystal display device Expired - Fee Related JP2714650B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP33553789A JP2714650B2 (en) 1989-12-25 1989-12-25 Liquid crystal display device
KR1019900015632A KR940005124B1 (en) 1989-10-04 1990-09-29 Liquid crytal display device
US07/592,272 US5042916A (en) 1989-10-04 1990-10-03 Active matrix display device having divided additional capacitors
EP90118978A EP0421386B1 (en) 1989-10-04 1990-10-04 Liquid crystal display element
DE69020288T DE69020288T2 (en) 1989-10-04 1990-10-04 Liquid crystal display element.
EP94111000A EP0621503A3 (en) 1989-10-04 1990-10-04 Liquid crystal display element.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33553789A JP2714650B2 (en) 1989-12-25 1989-12-25 Liquid crystal display device

Publications (2)

Publication Number Publication Date
JPH03194516A true JPH03194516A (en) 1991-08-26
JP2714650B2 JP2714650B2 (en) 1998-02-16

Family

ID=18289684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33553789A Expired - Fee Related JP2714650B2 (en) 1989-10-04 1989-12-25 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JP2714650B2 (en)

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Publication number Priority date Publication date Assignee Title
JPH06273803A (en) * 1993-01-20 1994-09-30 Hitachi Ltd Active matrix liquid crystal display device
JP2001305586A (en) * 2000-02-15 2001-10-31 Matsushita Electric Ind Co Ltd Liquid crystal display device, pixel correction method thereof and driving method thereof
JP2002318390A (en) * 1993-01-20 2002-10-31 Hitachi Ltd Active matrix liquid crystal display device
US7209193B2 (en) 1993-03-04 2007-04-24 Samsung Electronics Co., Ltd. Matrix-type display device capable of being repaired in pixel unit
US7430024B2 (en) 2004-01-28 2008-09-30 Sharp Kabushiki Kaisha Active matrix substrate and display device
WO2013001564A1 (en) * 2011-06-27 2013-01-03 パナソニック株式会社 Display device and production method therefor
WO2013001566A1 (en) * 2011-06-27 2013-01-03 パナソニック株式会社 Display device and production method for same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06273803A (en) * 1993-01-20 1994-09-30 Hitachi Ltd Active matrix liquid crystal display device
JP2002318390A (en) * 1993-01-20 2002-10-31 Hitachi Ltd Active matrix liquid crystal display device
US7209193B2 (en) 1993-03-04 2007-04-24 Samsung Electronics Co., Ltd. Matrix-type display device capable of being repaired in pixel unit
JP2001305586A (en) * 2000-02-15 2001-10-31 Matsushita Electric Ind Co Ltd Liquid crystal display device, pixel correction method thereof and driving method thereof
US7430024B2 (en) 2004-01-28 2008-09-30 Sharp Kabushiki Kaisha Active matrix substrate and display device
US7830467B2 (en) 2004-01-28 2010-11-09 Sharp Kabushiki Kaisha Electrodes located at storage capacitor wiring in active matrix substrate
WO2013001564A1 (en) * 2011-06-27 2013-01-03 パナソニック株式会社 Display device and production method therefor
WO2013001566A1 (en) * 2011-06-27 2013-01-03 パナソニック株式会社 Display device and production method for same
US8563993B2 (en) 2011-06-27 2013-10-22 Panasonic Corporation Display device and fabrication method for display device
US8664671B2 (en) 2011-06-27 2014-03-04 Panasonic Corporation Display device and fabrication method for display device
JP5667992B2 (en) * 2011-06-27 2015-02-12 パナソニック株式会社 Display device and manufacturing method thereof
JPWO2013001566A1 (en) * 2011-06-27 2015-02-23 パナソニック株式会社 Display device and manufacturing method thereof

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