JPH0319348A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the intermediate trap of sidewalls and to stabilize the threshold voltage of a MOSFET by a method wherein a protective film to stop the permeation of ions, which are implanted in a semiconductor substrate, is formed on an intermediate film and after the protective film and a protective film are removed with an etching liquid which does not etch the intermediate film, the intermediate film is etched. CONSTITUTION:Sidewalls 12 consisting of a silicon oxide are respectively formed on the side parts of a gate electrode 6 formed on a semiconductor substrate 1, an intermediate film 14 having a large etching rate to a silicon oxide is formed on the sidewalls 12 and a protective film (a WSix layer) 18 to stop the permeation of ions which are implanted in the substrate 1 is formed on the film 14. Ions which bring the surface layer of the substrate 1 into an amorphous state, are implanted and impurity ions which are used for the formation of drain and source layers are implanted in the substrate 1. After a protective film 16 and the film 18 are removed with an etching liquid which does not etch the film 14, the film 14 is etched.

Description

[Detailed Description of the Invention] [Summary] Regarding a method of manufacturing a semiconductor device having a MOSFET, the present invention aims to improve the hot carrier resistance of the MOSFET, prevent the effective channel length from shortening, and suppress fluctuations in the dark voltage. A step of forming a sidewall made of silicon oxide on the side of a gate electrode formed on a semiconductor substrate, and a step of forming an intermediate film having a higher etching rate than silicon oxide on the sidewall. a step of forming a protective film on the intermediate film to prevent the transmission of ions implanted into the semiconductor substrate; a step of implanting ions that deteriorate the quality of the surface layer of the semiconductor substrate; and a step of forming a drain layer and a source layer. The method includes a step of implanting impurity ions used for layer formation into the semiconductor substrate, and a step of etching the intermediate film after removing the protective film using an etching solution that does not etch the intermediate film. [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a MOSFET. [Prior art] With the increasing integration of semiconductor devices, P-channel MOSFET
However, in order to reduce the effects of short channel effects such as deterioration of subthreshold characteristics and dependence of threshold voltage on channel length, the source and drain are formed shallowly and the depletion layer from the drain electrode is reduced. The aim is to suppress the spread of the problem and ensure stable operation. By the way, when forming the source and drain of a P-channel MOSFET by adding P-type impurity ions to an N-type silicon substrate, boron (Ba), which has a high solid solubility in silicon, is used.
However, since boron has a large diffusion coefficient in silicon, it easily diffuses within the silicon substrate, making it difficult to form shallow sources and drains. In this case, there is a method of reducing the ion implantation energy to make it shallower, but in reality there is a limit to reducing the implantation energy, so as shown in Figure 2(c), two Boron fluoride ion is converted to silicon base Fi2
2, so that boron enters shallowly. [Problem to be solved by the invention] However, many boron difluoride ions dissociate from the acceleration tube of the ion implantation device until they reach the silicon base Fi22, and fluorine ions and boron ions or boron fluoride ions As a result, the boron ions, which have a lighter mass, are accelerated and enter the silicon substrate 22 at a higher speed than the fluorine ions.Moreover, since boron atoms are smaller than silicon atoms, channeling occurs and the boron ions enter the silicon substrate 22. It will be deeply injected. Therefore,
As shown in FIGS. 2(a) and 2(b), before implanting boron difluoride ions, silicon ions or germanium ions are implanted into the silicon substrate 22 in advance to form the portions where the source and drain are to be formed. It is made amorphous to suppress the occurrence of channeling. However, since silicon ions or germanium ions are implanted over the entire surface of the silicon substrate 22, they are also implanted into the side walls 21 provided on the side walls of the gate electrode 20, and as a result, there are dangling bonds within the side walls 21. There will be more silicon atoms and a large number of intermediate traps will be formed.

When we investigate the generation of interface states in this state using the charge bombing method, we find that the charge bombing current is two orders of magnitude larger than in the state before silicon ion implantation, and many localized units are formed in the band gap. It is confirmed that it will. In addition, the lifespan is two orders of magnitude shorter in normal hot carrier resistance tests (the lifespan here is
FET to increase conductance by 10% of initial value
). Note that the sidewalls 21 of the sidewalls of the gate electrode 20 are made of other MOSFETs.
It is formed as a secondary product in the sidewall forming process used in the manufacture of ET. In this way, silicon ions and germanium ions excessively implanted into the sidewall 21 often exist as neutral traps in the sidewall 21.
Drain avalanche hot electrons generated due to impact ionization at the drain end reach the sidewall 2.
When the electrons are injected into L, electrons are captured therein, and the sidewall 21 becomes negatively charged. As a result, positive charges are induced at the end of the drain d to form a positive charge layer 24, as shown in FIG. As the impurity concentration becomes higher, the impurity concentration gradient becomes larger, hot carriers are more likely to be generated, and the dark value voltage becomes more likely to fluctuate. The present invention has been made in view of these problems, and it reduces the intermediate traps of the sidewall and improves the MOS
The purpose of this paper is to provide a method for manufacturing a semiconductor device that can stabilize the threshold voltage of an FET. [Means for solving the problem] The above-mentioned IJ problem includes a step of forming a sidewall l2 made of silicon oxide on the side of a gate electrode 6 formed on a semiconductor substrate 1, as illustrated in the first vlJ. , forming an intermediate film l4 having a higher etching rate than silicon oxide on the sidewall 12;
A step of forming a protection M18 on the intermediate film 14 to prevent the transmission of ions implanted into the semiconductor substrate 1; a step of implanting ions to amorphize the surface layer of the semiconductor substrate I; a step of implanting impurity ions used for forming the drain layer and the source layer into the semiconductor substrate temporary I;
After removing the protective film 16.18 with an etching solution that does not etch the intermediate WI14, the intermediate film 14 is removed.
The problem is solved by a method for manufacturing a semiconductor device, which is characterized by having a step of etching. [Function] According to the present invention, since the retention RL films 16 and 18 prevent the transmission of ions intended to be implanted into the semiconductor substrate 1, ions are prevented from entering the sidewall 12 below. In this case, the semiconductor group vi. The ions implanted into the semiconductor substrate 1 include, for example, silicon ions and germanium ions for making the surface layer of the semiconductor substrate Fif amorphous, or ions used for forming a source layer and a drain layer on the semiconductor substrate 1. There are boron fluoride ions, and the protective films 16 and 18 include, for example, a polycrystalline silicon film and a tungsten silicide film. For this reason, Gate i! In the process of implanting silicon or germanium ions into the semiconductor substrate 1 on both sides of the pole 6 to degrade the surface layer, these ions are no longer implanted into the sidewall I2, and neutral traps in the sidewall 12 are This can be prevented from occurring. Therefore, even if drain avalanche hot carriers are generated, they are less likely to be trapped by the sidewall l2, and charging of the sidewall 12 can be avoided. Therefore, charges are not induced in the drain or source by the sidewall 12, and the effective channel It is possible to prevent the length from decreasing or from increasing the impurity concentration gradient at the ends of the drain and source regions, and it is possible to suppress fluctuations in the threshold voltage. Further, in the present invention, after ions are implanted into the semiconductor substrate 1, the i-holding films 16, 18 and the intermediate film 14 are removed to leave the sidewall 12 for the following reason. That is, when the gate electrode 6 is made of polycrystalline silicon, if the sidewall l2 made of silicon oxide is etched with an etching solution such as hydronic acid, the gate electrode 6 will also be etched.
This is because it would be difficult to selectively etch only the sidewall 12, and furthermore, it is preferable to leave the sidewall 12 as a protective film for the gate electrode 6 to avoid damage to the gate electrode 6.

Further, the reason why the intermediate film 14 is formed between the i-holding film 16.18 and the sidewall 12 is to prevent the sidewall 12 from being etched at the same time when the protective film 16.18 is etched.

For example, the intermediate film 14 is formed of a silicon nitride film,
When polycrystalline silicon 111117 and tungsten silicide 11118 are sequentially formed as a protective film, a hydrofluoric acid-containing solution that etches the polycrystalline silicon film 17 and NH40H that etches the tungsten silicide film 18 are used.
, that depending on the etching solution, the intermediate film 1
4 remains without being etched, and the sidewall 12 made of silicon oxide remains as it is. Further, the intermediate film 14 in the present invention is a film having a higher etching rate than the sidewall l2 made of silicon oxide. That is, when etching the intermediate film 14 made of silicon nitride, o.
An etching solution containing POA will be used, but with this etching solution, silicon oxide is difficult to etch, and the selectivity of the silicon nitride film is about 30, making it possible to leave the sidewall l2 as it is. This is because it becomes. As a result of the influence of these films, the protective films l6, l8
It becomes possible to reliably protect the gate electrode 6 when removing it. [Example] Therefore, an example of the present invention will be described below based on the drawings. FIG. 1 is a cross-sectional process diagram showing an embodiment of the present invention, and the process of forming a P-channel M○S transistor on an N-type silicon substrate will be described below. First, as shown in FIG. 1(a), the surface of the silicon substrate in areas where no field oxide film is to be formed is covered with a silicon nitride film (hereinafter referred to as SiQM) 2, and in this state an N-type element for channel cut is applied. ,for example? (P) Ions are implanted at an energy of 60 keV and a dose of 2 x 101''/ej, and then the surface of the silicon substrate 1 is selectively oxidized to form a field oxide film 3 with a thickness of 300 to 400 nm in the region exposed from the SiJ4M2. In this case, a channel cuff region N4 is formed at the bottom of the field oxide film 3 (see FIG.
b)). After that, after removing SIJaM2, the transistor forming elmA is thermally oxidized to form a 15 nm thick silicon dioxide film (hereinafter referred to as SiO film) 5, and boron ions for threshold voltage adjustment are energized from above. 20keV,
It is implanted into the silicon substrate 1 at a dose of 9×10”/cd (FIG. 1(c)). Next, a first polycrystalline silicon film 6 is deposited to a thickness of 200 nm on the SiO film 5 by vapor phase epitaxy. The first SisN
n)! ! 7, second polycrystalline silicon film 8, second S+
The Ja film 9 is sequentially formed to have a thickness of 50 nm, 100 nm*, and 50 mm (FIG. 1(e)). Then, a second SL3NmlgI located above a certain region B of the gate electrode shape
A resist mask IO is formed on 9, and a second SLN is etched by reactive ion etching (hereinafter referred to as RIE).
A plurality of films from aW4'' to the first polycrystalline silicon film 6 are anisotropically etched (FIG. 1(f)).After this,
Peel off the resist mask 10. Next, SiQ. After depositing the SiOt film 11 to a thickness of 2000 mm, the SiOt film 11 is anisotropically etched by RIE to form the sidewall l2.
(Fig. 1 (g) and (h)), and then a third SiJa film 13 with a film thickness of 1000 is laminated thereon, and this film is anisotropically etched to form the sidewall 12. Middle consisting of SrsHa on the side! 1I14 (lth
Figures (i), (j)). After this, the exposed surface of the silicon substrate 1 is thermally oxidized to a film thickness of 200 to 310! A film 15 is formed. The second 542Ha film 9 is provided to prevent oxidation of the second polycrystalline silicon. Furthermore, a third polycrystalline silicon film 16 is formed to a thickness of about 2,000 layers, anisotropically etched by RIH, and the intermediate layer 16 is etched. Thin polycrystalline silicon film l6 on the side of 14
(Fig. 1(k)). The reason for providing the SiJ4 film 7.13 between the two polycrystalline silicon films 6.8 and between the sidewall 12 and the polycrystalline silicon film 16 in this way is that the polycrystalline silicon 118 .1
6, the polycrystalline silicon film 6 which becomes the gate electrode and the sidewall 1 made of silicon oxide are etched.
This is to protect 2. Next, the top layer Si. N. removing the membrane 9 with phosphoric acid;
The polycrystalline silicon 1198.16 around the first polycrystalline silicon film 6, which will become the gate electrode, is exposed. Then, tungsten hexafluoride (wp*) and monosilane (Si84
) When tungsten silicide (hereinafter referred to as WSil) is formed by the vapor phase method using a gas containing W
Because Six has the property of selectively adhering to polycrystalline silicon, the second polycrystalline silicon l! ! 8 and the third polycrystalline silicon film 16, WSil is selectively extended to form a layer 151 on the gate electrode formation region B. A film 18 is formed (FIG. 1 (1)). Ko-Six l! 1 B is 10
Make it about 00 people thick. In this state, using the WS+ film 18 as a mask, silicon ions (Si'' in the figure) or germanium ions (Go'' in the figure) are implanted into the silicon base layer 1 to make the surface layer non-quality. Figure l (+e)). Then, using boron difluoride ions (BF!'' in the figure) as a dopant,
This is implanted with an energy of 10 to 20 keel and a dose of 1×
1OIS~3×10'5/C4 and inject into non-quality 1119 (Figure 1(n)). Next, NH. OR and Ht
WSIx M 1 by an etching solution containing O*
8 is removed, and the polycrystalline silicon 16 on the side of the sidewall 12 is etched using an etching solution containing HNOs and HF. Furthermore, the middle portion 1!14 made of 513Na is removed using an etchant of HzPO4 ( Figure 1 (0)). In this case, S for S108
The etching selectivity of iJa is H! P.O.
．． When using sidewall 12, it will be as high as about 30. It is hardly etched. Also, M
The intermediate film 14 is etched using an etching solution for Si, 1H and 1B.
is not etched. The reason why the sidewalls 12 are left in this way is that when the sidewalls 12 made of silicon oxide are etched with an etching solution such as hydrofluoric acid, the polycrystalline silicon M6 constituting the gate electrode is also etched with the same etching solution. This is because there is a risk of damage. In addition, in these etching steps, the second polycrystalline silicon M8 and the first s+xNsH'r
You can also remove them at the same time. After this, the impurities implanted into the surface layer of the silicon substrate 1 are activated by heating to form conductivity type regions N30 to be used for drains and sources, and oxidized M3 is formed on the surface of the substrate 1.
Add 1 (Figure 1 (p)). Note that in the above embodiment, WSi. is attached to polycrystalline silicon 8.16,
Although silicon ions and germanium ions are prevented from entering the sidewall 12 made of SiO2, it is also possible to prevent ion implantation by forming thick polycrystalline silicon without forming WSh. Furthermore, although a silicon-based substrate 1 was used in the above embodiment, germanium or other semiconductor substrates may also be used. [Effects of the Invention] As described above, according to the present invention, the protective film prevents ions intended to be implanted into the semiconductor substrate from implanting into the sidewalls. It disappears. Therefore, in the process of implanting silicon ions or germanium ions into a semiconductor substrate to make the surface layer amorphous, these ions are not implanted into the sidewalls, which prevents the generation of neutral traps in the sidewalls. It can be prevented. Therefore, drain avalanche hot carriers are less likely to be trapped in the sidewalls, and charging of the sidewalls can be avoided, so charges are not induced in the drain or source by the sidewalls, reducing the effective channel length, or , it is possible to prevent the impurity concentration gradient from increasing at the ends of the drain M region and the source region, and it is possible to suppress fluctuations in the dark value voltage. In addition, an intermediate film that is not etched by the protective film etching solution is provided on the sidewall to protect the sidewall when the protective film is etched, and an intermediate layer is formed with a film that has a higher etching rate than the sidewall. By leaving the sidewalls intact when etching the intermediate film, the sidewalls can protect the gate electrode from the etching solution.

[Brief explanation of the drawing]

FIGS. 1(a) to (p) are process diagrams showing an example of the present invention in cross section, and FIGS. 2(a) to (d) are process diagrams showing an example of a conventional method in cross section. (Explanation of symbols) 1... Silicon substrate (semiconductor substrate) 5, 15... Si (h film, 6, 8... Polycrystalline silicon film, 7, 9, 13... SiJa film, 1l... ...Sing film, 12...Side wall, 14...Intermediate film, l6...Polycrystalline silicon film, l8...wsi.M (protective film), 19...Non-quality layer. Requester Fujitsu Limited

Claims (1)

[Claims] A step of forming a sidewall made of silicon oxide on the side of a gate electrode formed on a semiconductor substrate, and an intermediate film having a higher etching rate than silicon oxide on the sidewall. a step of forming a protective film on the intermediate film to prevent transmission of ions implanted into the semiconductor substrate; and a step of implanting ions to make the surface layer of the semiconductor substrate amorphous. , a step of implanting impurity ions used for forming a drain layer and a source layer into the semiconductor substrate, and a step of etching the intermediate film after removing the protective film with an etching solution that does not etch the intermediate film. A method for manufacturing a semiconductor device, characterized in that: