JPH03187259A - Cmos semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance latch-up resistance by forming a latch-up countermeasure well around a diffusion layer directly connected with I/O pad on a substrate having low impurity concentration without contacting with other wells. CONSTITUTION:A p-well 3 is formed on the surface region of a p<->-type semiconductor substrate 1 and an n-channel transistor Qn1 is formed on the surface thereof. An n-well 2a is formed on the surface region of the p<->-type semiconductor substrate 1, and a p-channel transistor Qp1 is formed on the surface thereof. n<+>-type diffusion layers 4a-4f are connected directly with I/O pads 10a-10d. An n-well 2b is formed around the n<+>-type diffusion layers 4a-4f in the surface region of the p<->-type semiconductor substrate 1 without contacting with other wells. At this time, no p-well is formed around the n-well 2b. Consequently, a depletion layer extends farther into the substrate 1 from the n-well 2b thus enhancing electron absorbing capability of the substrate 1. By such arrangement, latch-up resistance is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS type semiconductor integrated circuit device, and in particular, to a CMOS type semiconductor integrated circuit device, in which a p-well and an n-well are formed in a surface region of a p-type semiconductor substrate. CM with so-called twin well structure
The present invention relates to an OS type semiconductor integrated circuit device.

[Prior Art] As semiconductor integrated circuit devices become more densely packed, channel lengths are becoming shorter. (
CMOS having a so-called twin-well structure, in which a p-well and an n-well are formed on a semiconductor substrate (or n-type), has come into widespread use.

FIG. 4 is a plan view of this type of conventional CMO3 type O3 circuit and device near the input pad, and FIG. 5 is a sectional view taken along the line V-V.

In FIGS. 4 and 5, 1 is a p-type semiconductor substrate, 2a
, 2b is an n-well, 3 is a p-well doped with p-type impurities and has a higher impurity concentration than the substrate l, 4a to 4f
is an n 4-type diffusion layer, 5a and 5b are p11 type diffusion layers, 6 is a field oxide film, 7 is a gate oxide film, 8 is a gate electrode made of polysilicon, 9 is an insulating film between the eyebrows, 10a to 10
d is a wiring layer made of aluminum film, 10a is a VCO wiring layer, 10b is a GND wiring layer, 10c is a signal wiring layer, 10d is an input pad, 11 is an aluminum wiring layer (10a to 10d) and n+ type or p+ 12 are aluminum wiring layers (10b, 10c)
) and the gate electrode 8.

The n-well 2a is connected to the VC6 wiring layer 10a via the n+ type scattered layer 4a contact 11, and its potential is set to the power supply potential. In the n-well 2a, p11 type diffusions 5a and 5b are formed, and these diffusion layers and the gate electrode 8 form a p-channel MOS transistor Qpl.
is configured.

In the p-well 3, an n+ type scattering layer 4b4c is formed, and an n-channel MOS transistor Qnl is formed by these diffusion layers and the gate electrode ti8. The drains of the transistor Qnl and the transistor Qpl are connected to each other to form an inverter. In other parts of p-well 3, n1 type diffusion layers 4e and 4f are formed, and these diffusion layers and gate electrode 8 constitute an n-channel MOS transistor Qn2. n
The + type scattering layer 4f is a diffused resistance layer constituting a protection resistor, and one end of this diffused resistance layer is connected to the input pad 10d via a contact 11. Transistor Q n
Numeral 2 is a bunch-through transistor for preventing electrostatic discharge damage, and together with a diffused resistor (4f), constitutes an input protection circuit.

The n-well 2b is connected to the vcc wiring layer 10a via an n1 type expansion layer 4d and a contact 11. This well is provided to absorb minority carriers that are injected into the board from the input protection circuit when excessive voltage is applied to the input bin, and to prevent latch-up from occurring. .

[Problems to be Solved by the Invention] Latch-up due to the input bin is caused by the number of electrons injected into the n+ type scattered layer 4F substrate that constitutes the input protection resistor when a negative voltage is applied to the input bin. increases, and this is the inner M
! It is induced by reaching the n-well 2a for forming the i7 path. That is, when the number of electrons absorbed in the n-well 2a increases, the potential of this well decreases, and the p+
A forward bias is applied between the type scattering layer 5an well 2a,
As a result, a parasitic vertical pnp transistor constituted by the p-type diffusion layer 5a, the n-well 2a, and the p-type semiconductor substrate 1 is turned on. At this time, the holes injected into the substrate 1 from the n-well 2a cause The potential of the substrate around the n-well 2a rises, and the n+ type scattered layer 4Cp- type semiconductor substrate (p-well 3
)1, a forward bias is applied. Therefore, the parasitic lateral npn) transistor formed by the n+ type diffusion layer 4cmp- type semiconductor substrate 1-n well 2a is turned on, and a positive feedback loop is formed by both parasitic transistors, leading to latch-up.

In the conventional CMO8 type O8 circuit device described above, the n-well 2b is used to absorb electrons injected into the semiconductor substrate 1.
However, since this well is surrounded by the p-well 3, which has a higher impurity concentration than the substrate, the p-well 2b is
The depletion layer extending toward the − type semiconductor substrate 1 is narrowed, and its ability to absorb electrons is weakened.

In addition, in the conventional integrated circuit device, since the n+ type scattered layer 4f is in contact with the p well 3 with high impurity concentration, the withstand voltage between the n+ type scattered layer 4f and the p well 3 decreases, and the impurity is implanted into the substrate. The number of electrons increases.

From the above, the latch-up resistance of the conventional CMO9 type O9 circuit device is low, and latch-up is easily caused by an abnormal input voltage to the input bin.

[Means for Solving the Problems] The CMO8 type semiconductor integrated circuit device of the present invention is provided with: (1) an n-channel MO3)-transistor formed in the surface region of a p-type semiconductor substrate, on the surface of which an n-channel MO3)-transistor is formed; (1) an n-well formed in the surface region of the p-type semiconductor substrate on which a p-channel MOS transistor is formed; and (2) n+-type diffusion waste directly connected to the input/output pad. , (2) an n-well formed in the surface region of the p--type semiconductor substrate so as to surround the n+-type diffusion layer and not in contact with other wells.

[Example] Next, an example of the present invention will be described with reference to one drawing.

FIG. 1 is a plan view of the vicinity of an input pad showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line ■-■. In FIGS. 1 and 2, parts common to those in the conventional example shown in FIGS. 4 and 5 are denoted by the same reference numerals, and thus redundant explanation will be omitted.

In this example, the diffused resistor (4
f〉 and the punch-through transistor Qn2 are formed directly on the p-type semiconductor substrate 1 having an extremely low impurity concentration of about 1015/-, and are formed so as to surround this input protection circuit. The n-well 2b for preventing latch-up is also arranged within the surface area of this substrate without contacting other wells. On the other hand, transistor Qpl and transistor Qn that constitute the internal circuit
1 is a higher impurity concentration (1016 to 10
17 pieces/crA) are formed in the n-well 3.

In this embodiment configured as described above, since an n-well is not formed adjacent to the n-well 2b for latch-up prevention, a depletion layer largely extends from the n-well 2b into the substrate, and electrons in the substrate are absorption capacity has been improved and latch-up resistance has been significantly improved. Further, the transistor Qp1. By forming Qn1 in a well and forming bunch-through transistors directly on the substrate, the withstand voltage of the input protection circuit against the substrate can be increased while maintaining the conventional threshold voltage of the transistors that make up the internal circuit. Since the injection of electrons from the n4 type diffusion layer 4f into the substrate can be made more difficult to occur, the latch-up resistance can be further improved.

FIG. 3 is a plan view of the vicinity of an n-channel output transistor showing another embodiment of the present invention. In this embodiment, the output transistor has a threshold voltage equivalent to that of the internal circuit transistor. It is configured in the p-well 3a in order to make it a value. An n+ type scattered layer 4h constituting the source region of the output transistor, an n+ type scattered layer 4g connected to the Vcc wiring layer 10a through the contact 11, and constituting the drain region of the output transistor;
connected to the signal wiring layer 10c via the contact 11;
And it is connected to the output pad via this wiring layer. Furthermore, the gate electrode 8 is connected via a contact 12 to a signal wiring layer 10c that receives internal signals. An n-well 3 is provided outside the n-well 3a, and a transistor forming an internal circuit is formed on the well. Further, an n-well 2c for preventing latch-up is formed between these two n-wells and does not contact any of the n-wells. The n-well 2C is connected to the VCC wiring layer 10a via the n+ type scattering layer 41 contact 11.

In this embodiment as well, the depletion layer from the n-well 2C extends largely into the substrate, so a negative voltage is applied to the output bin and the n+
Even if electrons are injected into the substrate from the type scattering layer 4g, they are
It can be absorbed into the well 2C, and latch-up can be effectively prevented.

[Effects of the Invention j As explained above, the present invention has the advantage that the latch-up countermeasure well formed to surround the diffusion layer directly connected to the input/output pad can be formed at a low temperature without coming into contact with other wells. Since the depletion layer is formed in the substrate having an impurity concentration, according to the present invention, the depletion layer from the well for preventing latch-up can be largely extended into the substrate. Therefore, according to the present invention, even if minority carriers are injected into the substrate from the diffusion layer connected to the input/output bin, most of these carriers can be absorbed into the latch-up prevention well, thereby preventing latch-up. can be significantly suppressed.

In addition, since the input/output protection circuit is formed directly on the substrate with low impurity concentration, the withstand voltage of the diffusion layer connected to the input/output pins with respect to the substrate is improved, and the minority carriers from this diffusion layer to the substrate are injection is reduced and latch-up is further suppressed.

[Brief explanation of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a plan view showing an embodiment of the present invention.
3 is a plan view showing another embodiment of the present invention, FIG. 4 is a plan view of the conventional example, and FIG. 5 is a sectional view taken along the line ■-■.
It is a sectional view taken along the line V-V. 1...p-type semiconductor substrate, 2a-2C...n-type well, 3.3a...p-well, 4a-41...
n" type diffusion layer, 5a, 5b...p+ type diffusion layer 6.
...Field oxide film, 7...Gate oxide film, 8.
...Gate electrode, 9...Interlayer insulating film, 10a...
・VCC wiring layer, 10b-GND wiring layer, 10c・
...Signal wiring layer, 10d...Input pad, 11.
12...Contact.

Claims (2)

[Claims] (1) a first conductivity type well formed in a surface region of a first conductivity type semiconductor substrate with a higher impurity concentration than the semiconductor substrate, and on whose surface a second conductivity type channel MOS transistor is formed; 1 formed within a surface region of a conductivity type semiconductor substrate,
a second conductivity type well on whose surface a first conductivity type channel MOS transistor is formed; a second conductivity type diffusion layer directly connected to the input/output pad; and the second conductivity type diffusion layer and the first conductivity type well. A CMOS type semiconductor comprising a conductivity type well and a second conductivity type well formed in a surface region of the first conductivity type semiconductor substrate without contacting these wells. Integrated circuit device. (2) The CMOS type semiconductor integrated circuit device according to item 1, wherein the second conductivity type diffusion layer directly connected to the input/output pad is formed directly on the first conductivity type semiconductor substrate.