JPH03183973A - Semiconductor testing device - Google Patents

Abstract

PURPOSE:To shorten the test time by storing a dedicated cache memory with decoded data of a next test program while a device main body conducts a test. CONSTITUTION:A CPU 1 reads a test program out of a memory 2 and decodes it, and sends it to a cache memory 4 (4-1 - 4-n) dedicated to test conditions of respective test items. Then when one test item is all completed, its condition is transferred from the memory 4 directly to the testing device main body 3, which starts a test. During this period, the CPU 1 decodes the test condition instructions of the test program and transfers them to the memory 4. When the test by the main body is completed during the period, the CPU 1 stops next test condition setting temporarily and restarts the interrupted test condition setting after the processing for the test end is completed; when the test is completed, a test condition is sent from the memory 4 to the main body 3 and a next test is conducted. Thus, all tests as to the test items are conducted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor testing device that tests a semiconductor using a test program.

[Conventional technology]

FIG. 2 is a configuration diagram of a conventional semiconductor testing device. In the figure, 1 is a CPtJ, 2 is a memory, and 3 is a main body of a semiconductor testing device. The CPU controls the test device main body 3, the memory 2 stores the test program, and the test device main body 3
generates test voltage etc. to perform IC tests.

Next, the operation will be explained. Tables 1 to 3 are examples of test programs. In this way, an IC test program consists of a condition setting instruction section for testing and an instruction section for actually conducting the test. Stored in memory 2. Tables 1 to 3 are test items 1 to 3.
From Table 1 (7) DRV (3V, OV), PAT
up to START, and DRV in Table 2 (2,5V, O
V) to PATSTART is a condition setting command part, and TEST in Tables 1 and 2 is a test command part.

The CPUI reads the test program from memory 2,
The command is decoded, converted into appropriate data, and sent to the test device main body 3. The test device main body 3 is set in a state for testing (for example, a voltage setting state of a voltage determination section (not shown), etc.) in accordance with data from the CPUI.

The CPU repeatedly executes the plurality of test condition commands written in the memory 2 as described above, and when all the test conditions have been set, sends a test execution command to the test device main body 3 to perform the next test.

The test device main body 3 performs the test and notifies the CPUI of completion. Meanwhile, the CPUI waits until the test device main body 3 completes the test.

The above operations are repeated for the number of test items written in the test program stored in the memory 2 to determine whether the IC is good or defective.

FIG. 3 is a flowchart showing the general operation of the CPU, and shows one test item. In the figure, first, initial processing of the test apparatus main body 3 is performed (step knob 11), a test program is decoded (step 12), and test condition data is transferred to the test apparatus main body 3 (step 13). Then, wait until the test condition setting of the test device main body 3 is completed (step 14).Next, send a test execution command to the test device main body 3 (step 15), and wait until the test of the test device main body 3 is completed (step 16). . Finally, perform processing such as display (
Step 17).

[Problem to be solved by the invention]

Since the conventional semiconductor test equipment is configured as described above, there is a waiting time for the CPU while the test equipment main body 3 performs the test after setting the test conditions.
There were problems such as an increase in the test time for C.

The present invention has been made in view of these points, and an object of the present invention is to obtain a semiconductor testing device that can shorten IC testing time.

[Means to solve the problem]

In order to achieve such an object, the present invention is equipped with a dedicated cache memory that allows the CPU to decode the next test program and store the data while the test equipment is executing a test. The data is transferred to the test equipment body independently from the test equipment.

[Effect]

In the semiconductor test device according to the present invention, while the test device main body is conducting a test, the CPU can store test conditions for the next test item of the test program in a cache memory dedicated to test conditions for each test item. .

〔Example〕

FIG. 1 shows the configuration of an embodiment of a semiconductor testing apparatus according to the present invention. In the figure, 1 is a CPU, 2 is a memory in which a test program is stored, 3 is a main body of a test device that generates a test voltage, etc., and 41.4-2. ..., 4
-n is a cache memory dedicated to multiple test conditions for each test item, cache memory 4-L 4-2.
. . , 4n have a common name as cache memory 4.

From memory 2 where the test program is stored, the CPU
I reads the test program, decodes it, and sends it to the cache memory 4 dedicated to test conditions for each test item. 1
When all the test conditions for the test items are completed, the test equipment main body 3
The navel conditions are directly transferred from the cache memory 4, and the test device main body 3 starts the test. During the test, the CPUI
The next test condition command of the test program is decoded and transferred to the cache memory 4. If the test of the test device main body 3 is completed during that time, the CPUI temporarily suspends setting of the next test conditions, performs a process to end the test, and when that is completed, resumes the suspended test condition settings. After all test condition settings are completed, the cache memory 4 is transferred to the test equipment main body 3.
Send the test conditions to , and perform the next test.

The above operations are performed for all test items.

Note that the test completion notification to the CPU 1 of the test device main body 3 is performed by an interrupt.

In the above embodiment, the CPUI processing does not use real-time O3, but it may be implemented by assigning test condition setting processing for each test item to a plurality of real-time O3 tasks.

〔Effect of the invention〕

As explained above, the present invention is equipped with a dedicated cache memory that allows the CPU to decode the next test program and store the data while the test equipment itself is running a test. By transferring data to the test equipment, the CPU no longer needs to wait for the test equipment to finish setting the test conditions or for the test to complete, reducing the time required to set the test conditions and reducing test time. This has the effect of significantly shortening the time.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a semiconductor testing device according to the present invention, FIG. 2 is a configuration diagram showing a conventional semiconductor testing device,
FIG. 3 is a flowchart for explaining the operation of the apparatus shown in FIG. 1...CPU, 2...Memory, 3...Test device main body, 4-1.4-2. ..., 4-n...Kyasoshumesori. Agent Masuo Oishi Figure 2 Figure 3

Claims (1)

[Claims] When performing an IC test, the CPU decodes the test programs in the order in which they are written and directly controls the hardware of the test equipment itself. The CPU is equipped with a dedicated cache memory that can decode the next test program and store the data, and this cache memory is
A semiconductor test device characterized in that data is transferred to a test device main body independently of a PU.