WO2007023730A1

WO2007023730A1 - Testing apparatus and program

Info

Publication number: WO2007023730A1
Application number: PCT/JP2006/316184
Authority: WO
Inventors: Mitsuru Sakai
Original assignee: Advantest Corporation
Priority date: 2005-08-23
Filing date: 2006-08-17
Publication date: 2007-03-01
Also published as: JP2007057333A; TW200710417A

Abstract

A testing apparatus is provided for testing devices to be tested. The testing apparatus is provided with a hardware section, which is connected to the device to be tested and tests the device based on given control information; and a control section which previously stores the control information and controls the hardware section. The control section is provided with a first register and a second register for storing the control information; the control circuit for controlling the hardware section based on first control information stored in the first register; and a write section for writing second control information to be successively performed after the first control information, while the hardware section is operating based on the first control information.

Description

Specification

Test apparatus and program

Technical field

The present invention relates to a test apparatus that tests a device under test, and a program that causes the test apparatus to function. This application is related to the following Japanese application. For designated countries where incorporation by reference is permitted, the contents described in the following application are incorporated into this application by reference and made a part of this application.

Japanese Patent Application 2005— 241710 Filing August 2005 23

Background art

Conventionally, a test apparatus for testing a device under test such as a semiconductor circuit includes hardware for testing the device under test and a control circuit for controlling the hardware. The hardware is, for example, a circuit included in a pattern generator that generates a test pattern, a driver comparator connected to the IZO pin of the device under test, a comparator that compares the output signal of the device under test with an expected value, etc. .

[0003] A control circuit is provided for each piece of hardware, and controls the corresponding hardware based on control information stored in advance. The test apparatus performs a plurality of tests on the device under test according to, for example, a plurality of test items for testing the device under test. In this case, the control information stored in the control circuit is rewritten for each test. Currently, the related patent documents are not recognized and will be omitted.

Disclosure of the invention

Problems to be solved by the invention

[0004] However, when the control information stored in the control circuit is rewritten, the hardware control is changed, and therefore cannot be rewritten while the hardware is operating. For this reason, conventional test equipment stores control information for the next test in each control circuit after the test of the device under test is completed, and rewrites the control information for all control circuits. After that, the next test has started.

[0005] Control information to be stored in each control circuit differs depending on the corresponding hardware. Therefore, the test equipment needs to rewrite the control information sequentially for each control circuit. For this reason, it takes time to rewrite the control information of all the control circuits.

Therefore, an object of the present invention is to provide a test apparatus and a program that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

Means for solving the problem

[0007] In order to solve the above-described problem, in a first embodiment of the present invention, a test apparatus for testing a device under test, which is connected to the device under test and is based on control information provided A hardware unit for testing the device and a control unit for storing the control information in advance and controlling the hardware unit are provided. The control unit includes a first register and a second register for storing the control information. A control circuit that is connected to the hardware unit and controls the hardware unit based on the first control information stored in the first register, and the hardware unit operates based on the first control information. And a writing unit for writing second control information to be executed next to the first control information into the second register

[0008] The first register is connected to the control circuit and supplies the stored first control information to the control circuit. The control unit adds the first control information stored in the first register to the control circuit. And further comprising a transfer unit for transferring the second control information stored in the second register to the first register when the test based on the test is completed.

[0009] The control unit switches whether the first register or the second register is connected to the control circuit, and controls the control information stored in the connected first register or the second register. Also have a switch to supply the circuit.

[0010] While the test apparatus is operating based on the plurality of hardware units, the plurality of control units corresponding to the plurality of hardware units, and the first control information corresponding to the plurality of hardware unit forces. A control information supply unit that sequentially supplies the second control information to each writing unit, and when the test based on the first control information is completed, the second control information is sent to each transfer unit. A transfer control unit that transfers information at substantially the same time may be further included.

[0011] The test apparatus operates based on the plurality of hardware units, the plurality of control units corresponding to the plurality of hardware units, and the first control information corresponding to the plurality of hardware unit forces. In addition, when the test based on the first control information is completed, the control information supply unit that sequentially supplies the second control information to each writing unit, and the first register or the second And a switch control unit that switches which of the registers to be connected to the control circuit substantially simultaneously.

[0012] The second register is a flip-flop that takes in the second control information output from the writing unit in response to a given control clock. The hardware unit converts the writing unit into the first control information. Have a second register controller that supplies a control clock to the second register while operating on the basis.

[0013] The first register is a flip-flop that takes in the second control information transferred by the transfer unit according to a given control clock, and the transfer unit includes the control information output from the writing unit, the second control information, Select the shift of control information stored in the register and transfer it to the first register, and supply the control clock to the first register when the test based on the first control information is completed And a first register control unit.

[0014] The first register control unit includes a logical product circuit that outputs a logical product of a control clock output from the second register control unit and an enable signal that prohibits the first register from capturing control information. A logical sum circuit that outputs the logical sum of the transfer command signal indicating the H logic as the control clock of the first register when the test based on the first control information is completed. Have it!

[0015] In the test based on the first control information, the control unit prohibits the first register from taking in the second control information when a failure of the device under test is detected. Also have a Jister Control.

[0016] In the second embodiment of the present invention, there is provided a program for causing a test apparatus for testing a device under test to function. The test apparatus is connected to the device under test and is based on control information provided! / The hardware unit for testing the device under test and the control information are stored in advance and function as a control unit for controlling the hardware unit. The control unit stores the control information. The control circuit for controlling the hardware unit based on the first control information stored in the first register and the hardware unit are connected to the first register and the second register, and the hardware unit. A program is provided that functions as a writing unit that writes second control information to be executed next to the first control information to the second register while operating based on the control information.

[0017] It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. A sub-combination of these feature groups can also be an invention.

The invention's effect

[0018] According to the present invention, control information for controlling hardware can be updated in a short time. In particular, in a test apparatus including a large number of hardware units, the control information in each control unit that controls the hardware units can be updated in a short time. In addition, when multiple tests are performed continuously, such as in a semiconductor circuit test apparatus, it is necessary to update the control information multiple times, so that the time required for updating the control information for each test can be shortened. The invention is effective.

Brief Description of Drawings

FIG. 1 is a diagram showing an example of the configuration of a test apparatus 100 according to an embodiment of the present invention.

2 is a diagram showing an example of the configuration of a control unit 30. FIG.

3 is a diagram showing an example of a detailed configuration of the control unit 30 shown in FIG. 2 (a).

FIG. 4 is a timing chart showing an example of the operation of the control unit 30 shown in FIG.

FIG. 5 is a diagram showing an example of a program that causes the test apparatus 100 to function.

FIG. 6 shows an example of the configuration of a computer 500 that causes the test apparatus 100 to function.

Explanation of symbols

[0020] 10 ··· 'Main body, 20 ·' No, 1ware portion, 30 · · · Control portion, 32 · · · Write portion, 34 · · · First register, 36 · · 'Second Register, 38 ... 'Transfer section, 40 ...' Control circuit, 42 ... 'First switch section, 44 ...' Second switch section, 46 ... 50 '' OR circuit, 52 '' Second register controller, 100 '' Test equipment, 200 '' Device under test, 500 '' Computer, 702 '-ROM, 704 · -RAM, 706 · · 'Communication interface, 710 ·' Node disk drive, 712 · 'FD drive, 714 · · CD-ROM drive Eve, 720 · 'Flexible disc, 722 · -CD-ROM

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention within the scope of the claims, and combinations of features described in the embodiments. All of these are not necessarily essential to the solution of the invention.

FIG. 1 is a diagram showing an example of the configuration of a test apparatus 100 according to an embodiment of the present invention. The test apparatus 100 is an apparatus for testing a device under test 200 such as a semiconductor circuit, and includes a main body unit 10, a plurality of hardware units 20, and a plurality of control units 30.

[0023] Each hardware unit 20 is connected to the device under test 200, and tests the device under test 200 based on the given control information. For example, each hardware unit 20 includes, for example, a pattern generator that generates a test pattern, a driver comparator connected to the I / O pin of the device under test, and a comparison that compares the output signal of the device under test with an expected value. It is a circuit included in a container.

The plurality of control units 30 are provided corresponding to the plurality of hardware units 20. Each control unit 30 stores control information in advance, and controls the corresponding hardware unit 20 based on the control information. For example, the control information is information indicating data to be output by the hardware unit 20, information indicating the output timing of the data, and the like. Each control unit 30 has two registers for storing two control information. While controlling the hardware unit 20 based on the control information stored in one register, the control information to be used next is stored. Include in the other register in advance.

[0025] The main body unit 10 exchanges data with the hardware unit 20 and the control unit 30 to determine whether the device under test 200 is good or bad. For example, the main unit 10 can determine whether the device under test 200 is good or bad based on the output signal that the hardware unit 20 also received the device power under test. Also, the test result of the device under test 200 in the nodeware unit 20 is stored. Even so. Further, the main body unit 10 generates control information to be stored in each control unit 30 and sequentially supplies the control information to each control unit 30.

As described above, since the control unit 30 has a register for storing two pieces of control information, the control information to be used next is preliminarily stored in each control unit 30 during the operation of the hardware unit 20. Can be stored. Therefore, when a plurality of tests are performed on the device under test 200, it is possible to eliminate the time for supplying the next control information from the main body unit 10 to the control unit 30 each time the test is completed.

[0027] For example, since it is necessary to sequentially supply control information from the main body unit 10 to the respective control units 30, when the test apparatus 100 includes a large number of hardware units 20, If the control information of the control unit 30 is updated at the end of each test, the test time loss becomes very large. On the other hand, the test apparatus 100 in this example can store the control information to be used next during the test of the device under test 200 in each control unit 30, thereby greatly reducing the test time loss. be able to.

FIG. 2 (a) is a diagram illustrating an example of the configuration of the control unit 30. The control unit 30 shown in FIG. 2A includes a writing unit 32, a first register 34, a second register 36, a transfer unit 38, and a control circuit 40.

The first register 34 and the second register 36 store control information given from the main body 10. The first register is connected to the control circuit 40 and supplies the stored first control information to the control circuit 40. The first control information stored in each first register 34 may be different control information for each control unit 30. That is, the first control information stored in each control unit 30 may be different for controlling different hardware units 20. The control circuit 40 is connected to the hardware unit 20 and controls the hardware unit 20 based on the first control information stored in the first register.

[0030] The writing unit 32 transmits the second control information to be executed next to the first control information to the second register while the hardware unit 20 operates based on the first control information. Write to 36. Each writing unit 32 receives the second control information from the main body unit 10. The main unit 10 includes a control information supply unit that sequentially supplies the second control information to each writing unit 32 while the plurality of hardware units 20 operate based on the corresponding first control information. May be included.

[0031] The second control information given to each writing unit 32 may be different control information for each control unit 30. With such a configuration, the second control information to be executed next in each control unit 30 is stored in advance while the first control information is being executed. It can be done.

[0032] When the test based on the first control information stored in the first register 34 is completed, the transfer unit 38 receives the second control information stored in the second register 36, Transfer to first register 34. Each transfer unit 38 is given a transfer command from the main unit 10 and transfers the second control information stored in the second register to the first register 34 in response to the transfer command. The main body unit 10 may include a transfer control unit that transfers the second control information to the respective transfer units 38 substantially simultaneously when the test based on the first control information is completed.

Since the transfer command given to each control unit 30 may be the same signal, the main body unit 10 can give the transfer command to each control unit 30 almost simultaneously. Therefore, when the test based on the first control information is completed, the second control information can be stored in each of the first registers 34 in a short time.

[0034] According to the control unit 30 in this example, the control information for controlling the hardware unit 20 can be updated in a short time. For example, if the test apparatus 100 includes 100 control units 30 and the time required to update the control information of one control unit 30 is t [s], in the conventional method, after the test is completed, Since the control information is updated sequentially for each control unit 30, it takes 100 X t [s] to update the control information. On the other hand, according to the control unit 30 in this example, the control information can be updated simultaneously for all the control units 30 after the test is completed. Can do.

[0035] Further, the control unit 30 prohibits the first register 34 from taking in the second control information when a failure of the device under test 200 is detected in the test based on the first control information. You may stop. By such control, the same test can be repeatedly performed on the device under test 200 in which a defect is detected.

FIG. 2 (b) is a diagram showing another example of the configuration of the control unit 30. The control unit 30 shown in FIG. 2B includes a writing unit 32, a first register 34, a second register 36, a control circuit 40, a first switch unit 42, and a second switch unit 44.

[0037] The first register 34 and the second register 36 have the same functions as those of the first register 34 and the second register 36 described with reference to FIG. The second switch 44 is connected to the first Switch between register 34 or second register 36 to be connected to control circuit 40, and supply control information stored in connected first register 34 or second register 36 to control circuit 40 .

The control circuit 40 is connected to the hardware unit 20 and controls the hardware unit 20 based on the first control information stored in either the first register 34 or the second register 36. I will do it. That is, the control circuit 40 controls the hardware unit 20 based on the control information stored in the register to which the second switch unit 44 is connected.

[0039] The first switch unit 42 switches whether the writing unit 32 is connected to the first register 34 or the second register 36. In this example, the first switch unit 42 selects a register opposite to the second switch unit 44 and connects it to the writing unit 32. That is, when the control circuit 40 is connected to the first register 34, the first switch unit 42 connects the writing unit 32 and the second register 36. When the control circuit 40 is connected to the second register, the first switch unit 42 connects the writing unit 32 and the first register 34.

[0040] The writing unit 32 operates while the hardware unit 20 is operating based on the first control information stored in either the first register 34 or the second register 36. The second control information to be executed next to the control information is written to the other one of the first register 34 and the second register 36. In this example, the writing unit 32 writes the second control information to the register to which the first switch unit 42 is connected. In addition, the main body unit 10 controls the control information for sequentially supplying the second control information to the respective writing units 32 while the plurality of hard- er units 20 operate based on the corresponding first control information. You may have a supply part. With this configuration, the second control information to be executed next in each control unit 30 can be stored in advance while the first control information is being executed.

The first switch part 42 and the second switch part 44 are controlled by the main body part 10. When the test based on the first control information is completed, the main body 10 sends the first register 34 or the second switch 44 to the first switch 42 and the second switch 44 in each control unit 30. It has a switch controller that switches which register 36 is connected to the writing unit 32 or the control circuit 40 almost simultaneously.

[0042] For each control unit 30, the first switch unit 42 and the second switch unit 44 are controlled. Since the control signals to be controlled may be the same signal, the main body unit 10 can provide the control signals to the respective control units 30 substantially simultaneously. For this reason, when the test based on the first control information is completed, the control information for controlling the hardware unit 20 can be switched in a short time.

FIG. 3 is a diagram showing an example of a detailed configuration of the control unit 30 shown in FIG. 2 (a). In this example, the first register 34 is a flip-flop that takes in the second control information transferred by the transfer unit 38 in accordance with a given control clock. The second register 36 is a flip-flop that takes in the second control information output from the writing unit 32 in accordance with a given control clock.

The writing unit 32 includes a second register control unit 52. The transfer unit 38 includes a multiplexer 46, an AND circuit 48, and an OR circuit 50. The logical product circuit 48 and the logical sum circuit 50 function as a first register control unit that supplies a control clock to the first register 34 when the test based on the first control information is completed.

The write unit 32 receives data of control information, a register SEL signal, and a write enable signal from the main unit 10. The writing unit 32 supplies control information data to the data input terminal of the first register 34 and the data input terminal of the multiplexer 46. The second register controller 52 supplies the logical product of the register SEL signal and the write enable signal to the second register 36 as a control clock. Here, the register SEL signal is a signal for the main body unit 10 to sequentially select the control unit 30 to store the second control signal, and the write enable signal is sent to the second control unit 30 for the second control signal. This signal permits writing of control signals.

That is, when the main body unit 10 writes a predetermined second control signal to any of the control units 30, the main body unit 10 receives the second control signal and a write enable signal indicating H logic. Supplied to all control units 30. Then, the main unit 10 supplies the register SEL signal indicating the H logic to the control unit 30 to which the second control signal is to be written, and supplies the register SEL signal indicating the L logic to the other control unit 30. To do. By sequentially performing such control for all the control units 30, the second control information to be used next can be stored in the second register 36 for all the control units 30. . The multiplexer 46 receives the control information given from the writing unit 32 and the control information stored in the second register 36, selects one of the control information, and selects the data in the first register 34. Supply to the input terminal. For example, as in the conventional apparatus, when the main unit 10 stores the next control information in the first register 34 after the end of the test, the multiplexer 46 selects the control information given from the writing unit 32 and selects the first control information. To register 34. In addition, when the main unit 10 stores the next control information in the second register 36 in advance during the test, the multiplexer 46 selects the control information stored in the second register 36 and selects the first register. Supply to star 34. Which control information is selected by the multiplexer 46 is controlled by a selection signal supplied from the main unit 10.

[0048] The AND circuit 48 outputs a logical product of the control clock output from the second register control unit 52 and the enable signal W-INH that prohibits the first register 34 from capturing control information. To do. The enable signal is received by the first register 34 from the start of each test to the end of each test or the end of storing the second control information in the second register 36, whichever is later. This is a signal for prohibiting the capture of the next control information. The signal output from the AND circuit 48 indicates L logic in the period. With such control, the second control information can be stored in the second register 36 without being stored in the first register 34 during the operation of the hardware unit 20.

The logical sum circuit 50 outputs the logical sum of the transfer command signal indicating the H logic when the test based on the signal output from the logical product circuit 48 and the first control information is completed. Output as control clock. With this configuration, when the test based on the first control information is completed, the second control information stored in each second register 36 is stored in each first register 34. It can be transferred almost simultaneously.

In this example, the test apparatus 100 sequentially performs testl, test2, and test3 as tests of the device under test 200.

[0051] As described above, the AND circuit 48 has the later of either the end of each test or the end of storing the second control information in the second register 36 from the start of each test. In the period until the first register 34 is prohibited from taking in the next control information Bull signal W—INH is applied.

[0052] During each test, the main unit 10 supplies control information data to be used in the next test to each control unit 30. The control information supplied from the main unit 10 is sequentially stored in the second register of each control unit 30. At this time, since the amount of control information to be used in each test is different, storage of control information may not be completed during the current test, for example, Data3 shown in FIG. In such a case, the main unit 10 generates an enable signal that prohibits the first register 34 from taking in the next control information until the storage of the control information is completed.

[0053] In addition, the main body 10 determines whether the power of the next time period T1 elapses from the later of either the end of each test or the end of storing the second control information in the second register 36. Start the test. The control unit 30 transfers the second control information from the second register 36 to the first register 34 during the period. That is, the main body 10 supplies a transfer command signal to the logical sum circuit 50 in the period T1. The transfer unit 38 transfers the control information stored in the second register 36 to the first register 34 in response to the transfer command signal.

[0054] As described above, according to the test apparatus 100 in this example, the second control information can be transferred from the second register 36 to the first register 34 almost simultaneously in all the control units 30. The control information can be transferred in a short time. The main body 10 may store in advance the time required for the transfer and determine the predetermined period T1 described above based on the time.

FIG. 5 is a diagram showing an example of a program that causes the test apparatus 100 to function. In this program, the command Px in each test testl, test2, and test3 indicates the data of control information to be used in the test. The command MEAS MPAT (9) is a command that causes the main body 10 to prefetch control information to be used in the next test. When the prefetch command is detected, the main unit 10 prefetches the control information data Px to be used in the next test, and supplies the control information data to the control unit 30 during the test.

FIG. 6 shows an exemplary configuration of a computer 500 that causes the test apparatus 100 to function. In this example, the computer 500 uses the test apparatus 100 as described in FIGS. Stores the program to be executed. The computer 500 includes a CPU 700, a ROM 702, a RAM 704, a communication interface 706, a hard disk drive 710, an FD drive 712, and a CD-ROM drive 714. The CPU 700 operates based on programs stored in the ROM 702, RAM 704, node disk drive 710, flexible disk 720, and / or CD-ROM 722.

[0057] For example, a program for causing the test apparatus 100 to function causes the test apparatus 100 to function as the main body unit 10, the plurality of hardware units 20, and the plurality of control units 30 described with reference to FIGS. The communication interface 706 communicates with the test apparatus 100, for example, and controls the test apparatus 100.

A hard disk drive 710 as an example of a storage device stores setting information and a program for operating the CPU 700. The ROM 702, RAM 704, and Z or hard disk drive 710 store programs for causing the test apparatus 100 to function as the test apparatus 100 described with reference to FIGS. The program can also be stored on the flexible disk 720, CD-ROM 722, etc.!

[0059] The FD drive 712 reads a program from the flexible disk 720 and provides it to the CPU 700. The CD-ROM drive 714 reads a program from the CD-ROM 722 and provides it to the CPU 700.

Further, the program may be read and executed directly from the recording medium card to the RAM, or may be read and executed by the RAM after being installed in the node disk drive. Furthermore, the program may be stored in a single recording medium or a plurality of recording media. The program stored in the recording medium may provide each function in cooperation with the operating system. For example, the program may ask the operating system to perform some or all of the functions and provide the functions based on the response of the operating system.

[0061] As a recording medium for storing the program, in addition to a flexible disk and a CD-ROM, an optical recording medium such as DVD and PD, a magneto-optical recording medium such as MD, a tape medium, a magnetic recording medium, and an IC card A semiconductor memory such as a miniature card can be used. In addition, a node provided in a server system connected to a dedicated communication network or the Internet A storage device such as a disk or RAM may be used as the recording medium.

[0062] Although the present invention has been described using the embodiment, the technical scope of the present invention is not limited to the scope described in the above embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiment. It is obvious that the description in the scope of the claims that embodiments with such changes or improvements can also be included in the technical scope of the present invention.

Industrial applicability

As is apparent from the above, according to the present invention, control information for controlling hardware can be updated in a short time. In particular, in a test apparatus including a large number of hardware units, the control information in each control unit that controls the hardware unit can be updated in a short time. In addition, when multiple tests are performed consecutively, such as in a semiconductor circuit test apparatus, it is necessary to update the control information multiple times, so that it is possible to shorten the control information update time for each test. The invention is effective.

Claims

The scope of the claims

[1] A test apparatus for testing a device under test,

A hardware unit connected to the device under test and testing the device under test based on given control information;

A control unit that stores the control information in advance and controls the hardware unit;

The controller is

A first register and a second register for storing the control information;

A control circuit connected to the hardware unit and controlling the hardware unit based on the first control information stored in the first register;

While the hardware unit is operating based on the first control information, the first

A write unit for writing the second control information to be executed next to the control information of 1 into the second register;

Test equipment with

[2] The first register is connected to the control circuit and supplies the stored first control information to the control circuit,

The control unit stores the second control information stored in the second register when the test based on the first control information stored in the first register is completed. Further includes a transfer unit for transferring the data to the first register.

The test apparatus according to claim 1.

[3] The control unit switches which of the first register or the second register is connected to the control circuit, and the connected first register or the second register stores The test apparatus according to claim 1, further comprising a switch unit that supplies the control information to the control circuit.

[4] The test apparatus comprises:

A plurality of the hardware parts;

A plurality of the control units corresponding to the plurality of hardware units;

The plurality of hardware units operate based on the corresponding first control information. A control information supply unit that sequentially supplies the second control information to each of the writing units,

A transfer control unit that causes the respective transfer units to transfer the second control information substantially simultaneously when the test based on the first control information is completed;

The test apparatus according to claim 2, further comprising:

[5] The test apparatus comprises:

A plurality of the hardware parts;

A control information supply unit that sequentially supplies the second control information to each of the writing units while the plurality of hardware units are operating based on the corresponding first control information;

When the test based on the first control information is completed, switch control is performed so that each of the switch units switches the force for connecting either the first register or the second register to the control circuit substantially simultaneously. Department and

The test apparatus according to claim 3, further comprising:

[6] The second register is a flip-flop that takes in the second control information output by the writing unit in response to a given control clock,

The writing unit includes a second register control unit that supplies the control clock to the second register while the hardware unit operates based on the first control information.

The test apparatus according to claim 2.

[7] The first register is a flip-flop that takes in the second control information transferred by the transfer unit according to a given control clock,

The transfer unit

A multiplexer that selects one of the control information output from the writing unit and the control information stored in the second register and transfers the selected information to the first register, and a test based on the first control information And a first register control unit for supplying the control clock to the first register when The test apparatus according to claim 6, comprising:

[8] The first register control unit includes:

An AND circuit for outputting a logical product of the control clock output from the second register control unit and an enable signal for prohibiting the first register from taking in the control information;

When the test based on the signal output from the AND circuit and the first control information is completed, the logical sum of the transfer command signal indicating the H logic is output as the control clock of the first register. OR circuit

The test apparatus according to claim 7, comprising:

[9] In the test based on the first control information, the control unit detects the second control information when a failure of the device under test is detected. 3. The test apparatus according to claim 2, further comprising a second register control unit that prohibits the loading.

[10] A program for operating a test apparatus for testing a device under test,

The test apparatus

A hardware unit that is connected to the device under test and tests the device under test based on given control information;

To function,

The control unit

A first register and a second register for storing the control information;

A control circuit that is connected to the hardware unit and controls the hardware unit based on the first control information stored in the first register;

Program to make it work.