JPH11295387A - Semiconductor integrated circuit tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To serially output test data of a desired pin arrangement of the semiconductor integrated circuit tester from desired pins. SOLUTION: A memory circuit 16 for storing data of a pattern generator is provided at each of driver pins of the semiconductor integrated circuit tester, and constituted as a shift register with desired arrangement of the memory circuit of each driver pin to serially output data in the pin direction from desired driver pins at serial outputting. In the case of testing an IC having both parallel and serial input modes, if test vectors for the parallel mode are formed, the serial mode test is enabled to provide the effect of greatly lessening the vector forming man-hour.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit test apparatus, and more particularly to a technique of a semiconductor integrated circuit test apparatus that serially supplies test data parallel in a pin direction.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit test apparatus, when test data is supplied to an IC under test, data for each pin stored in a pattern generator is read out and supplied to a corresponding pin of the IC under test. Was.

[0003]

However, in such a conventional technique, for example, when the IC under test has both parallel and serial data input modes, and the input mode is different between the final test and the wafer probe test. In addition, it was necessary to create test vectors for both parallel and serial inputs, which required twice as many test vector creation steps.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has been made in consideration of a semiconductor integrated circuit test having a function of supplying parallel test data having an arbitrary pin arrangement from an arbitrary pin to an IC under test serially. It is intended to provide a device.

[0005]

In order to solve this problem, a semiconductor integrated circuit test apparatus according to the present invention comprises: a) a semiconductor integrated circuit test apparatus for supplying test data to an IC under test; The test data can be supplied to the IC under test serially from an arbitrary pin.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, 19 is a driver for supplying a signal to the IC under test, 20 is a driver pin output, 21 is a high-level driver voltage, and 18 is a low-level driver voltage. 12 is output data from the pattern generator,
16 is a memory circuit, 11 is an output of the memory circuit, and 14 is a clock of the memory circuit. 23 is a selection circuit, and 15 is its control signal. In the 0 state, the output data 12 of the pattern generator is selected, and in the 1 state, the shift input 13 to the storage circuit is selected. 22 is a selection circuit, and 17 is its control signal. In the 0 state, the output data 12 of the pattern generator is selected, and in the 1 state, the memory circuit output 11 is selected. FIG. 1 shows a configuration of one pin of a semiconductor integrated circuit test apparatus of the present invention. In a configuration of a plurality of pins, a storage circuit output 11 of a driver pin of its own shifts input to a storage circuit of another driver pin. 1
3 is connected. FIG. 2 shows this connection, 31 '.
Is a memory circuit output of the driver pin [1], 32 'is a memory circuit output of the driver pin [2], and so on. Also,
31 is a shift input to the memory circuit of the driver pin [1],
32 is a shift input to the memory circuit of the driver pin [2],
The same applies hereinafter. ○ indicates connection, and X indicates non-connection. Arbitrary connection is possible by placing a programmable switch at the intersection of the matrix of FIG.

Hereinafter, the operation will be described. Control signal 1
When 5 and 17 are set to the 0 state, the output data 12 from the pattern generator is directly output to the driver pin output 20 through the driver 19. Clock 14 at the same time
To output data 1 from the pattern generator.
2 is stored in the storage circuit 16. When serially outputting pin-direction data, the control signal 15 is set to the 0 state,
The control signal 17 of the driver pin for performing the serial output is set to the 0 state. If the storage circuit 16 of each pin is configured as a shift register in the connection arrangement of FIG.
Driver pin output 20 with control signal 17 set to 0 state
Supplies a serial signal in the pin direction to the IC under test.

[0009]

As described above, according to the present invention,
An arbitrary array of driver signals in the pin direction can be serially output from an arbitrary driver pin. When testing an IC having both parallel and serial input modes, if a parallel mode test vector is created, the serial mode test can be performed, and the number of test vector creation steps can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit test apparatus of the present invention.

FIG. 2 is a shift arrangement diagram.

[Explanation of symbols]

REFERENCE SIGNS LIST 11 storage circuit output 12 output data from pattern generator 13 shift input to storage circuit 14 clock 15, 17 control signal 16 storage circuit 18 low-level driver voltage 19 driver 20 driver pin output 21 high-level driver voltage 22, 23 Select circuit 31-38 Shift input to storage circuit of driver pins [1-8] 31'-38 'Storage circuit output of driver pins [1-8]

Claims (1)

[Claims] A) a semiconductor integrated circuit test apparatus for supplying test data to an IC under test; b) a function of serially supplying test data having an arbitrary pin arrangement from an arbitrary pin to the IC under test; A semiconductor integrated circuit test apparatus, characterized in that: