JPH0989996A - Testing device for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor testing device by which a general static burn-in test can be executed with only one BT terminal, and all internal circuits can be operated. SOLUTION: This device is formed of a multiphase clock generating circuit 4 for generating a scan mode SM, a normal clock CK for operating an internal logic, and a scan clock SCK for operating a boundary scan from a test terminal BT for dynamic BT, respectively, and an input and output buffer circuit formed of F/F A1-A10 and having boundary scan testing function. The scan clock SCK is distributed to the F/F A1-A10, and the normal clock CK to A1-A10 and F/F B1-B10. The scan mode signal SM is distributed to all the F/F A1-A10, B1-B10 to perform the switching of scan mode/normal mode. The output of the F/F A10 in the final stage of boundary scan is connected to the input of the F/F A1 in the initial stage to loop the boundary scan.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit tester, and more particularly to a dynamic burn-in test (hereinafter referred to as "B") using a boundary scan test circuit.
(Referred to as “T”) related to the semiconductor integrated circuit testing device.

[0002]

2. Description of the Related Art A semiconductor integrated circuit is generally subjected to screening in order to obtain high reliability except for an initial failure having a high failure rate. In semiconductor integrated circuits, there are various factors that cause failures, such as design problems, manufacturing problems, and inspection problems. The main failure modes include surface defects such as ion contamination, oxide film defects such as pinholes, metal wiring defects, diffusion defects, and input circuit defects. An effective screening method for these failures is burn-in. The burn-in includes static burn-in that does not operate inside and dynamic burn-in that operates inside. Dynamic burn-in is said to be more effective for oxide film defects, contact defects, and electromigration.

In order to carry out BT, it is necessary to give an input signal, and expensive test equipment is required, so that it may be carried out by the following simple circuit. An example of a conventional example of this type of test apparatus is described in JP-A-61-6837. Referring to FIG. 6 showing a block diagram of the test apparatus described in the publication, a clock generating means for supplying a clock internally shifted (hereinafter, shift and scan are treated as synonymous) by a dynamic BT command and a shift-in by the dynamic BT command. Data generating means for generating data and supplying it to the input of the shift path circuit and NAND circuits 70 and 7
2 is supplied to the NAND circuit 71, and the outputs of the combination circuit CC1 and NAND circuits 73 and 75 are NA.
The combination circuit CC2 is supplied to the ND circuit 74, and the BT terminal 65 has an inverter 68 and a NAND circuit 72.
And 73, shift clock generating circuit 61, shift-in data generating circuit 62, and OR circuit 69.

The output of the shift clock generation circuit 61 is NA.
The output of the shift-in data generating circuit 62 is connected to the other input terminal of the ND circuit 72 and the other input terminal of the NAND circuit 73, respectively. The output of the inverter 68 is connected to one input terminal of each of the NAND circuits 70 and 75. The clock CL is applied to the other input terminal of the NAND circuit 70.
The K terminal 64 is connected. The SIN terminal 67 for shift data is connected to the other input terminal of the NAND circuit 75.
Further, a shift control terminal SFT66 is connected to the other input terminal of the OR circuit 69.

During normal operation, the input of the BT terminal 65 is a logic low level (hereinafter referred to as "0" and high level is referred to as "1").
The shift clock is received from the CLK terminal 64 through the AND gate 70, and the SIN is received through the NAND gate 75.
The shift-in data is received from the terminal 67, and the shift operation is performed when the SFT terminal 66 becomes "1".

When performing dynamic BT, the BT terminal 6
By setting the input of 5 to "1", the operation of the shift clock generating circuit 61 and the shift-in data generating circuit 62 is started, and the output of the shift clock generating circuit 61 is NAN.
Flip-flops 77 through 77 through D gates 72 and 71.
80, the output of the shift-in data generation circuit 62 is supplied to the shift-in input of the flip-flop 77 via the NAND gates 73 and 74, and the OR gate 6
The output of 9 is set to "1" and the flip-flops 77 to 80
The shift operation of is started.

In this example, most of the circuits in the main circuit 63 work together with the flip-flops 77-80. That is, when the flip-flops 77 to 80 start the shift operation, the other circuits in the main circuit 63 also start to operate together. Although the circuit operation at this time has no logical meaning, the purpose of the dynamic BT for performing burn-in while turning on and off the circuit element is fulfilled.

[0008]

In the above-described conventional test apparatus, it is considered that the SFT terminal and the SIN terminal are prepared in advance in the test apparatus. If not, the dynamic test including the BT terminal is performed. Three terminals are required as BT test terminals.

In the dynamic circuit, the main circuit 63 operates, but generally in the case of a synchronous logic circuit, for example, as shown in FIGS. 1 and 4 of the present invention, for example, input buffer → combinational circuit 1 → flip-flop → Combination circuit 2 →
The configuration is flip-flop → combinational circuit 3 → output buffer. In the above-described conventional example, the combinational circuit 2 corresponds to the main circuit 63, and not all circuits are operating in the BT test.

It is an object of the present invention to provide a semiconductor test apparatus capable of executing a normal static burn-in test with only one pin of a BT terminal and operating all internal circuits.

[0011]

The semiconductor integrated circuit testing apparatus of the present invention is characterized in that an internal circuit of the semiconductor integrated circuit is operated in order to eliminate an initial failure such as an oxide film defect and a contact defect of the semiconductor integrated circuit. Meanwhile, in a semiconductor integrated circuit tester for dynamic burn-in that performs screening, when a control signal for shifting to the dynamic burn-in test state is supplied from a test terminal, the storage means is serially connected to set the loop state. A scan mode signal for controlling to alternately repeat a scan state in which the serial output is returned to the serial input and an internal operation state in which the stored contents of the storage means are output in parallel; and an active state in the scan state. Scan clock and the activity during the internal operating state And a normal phase clock generating circuit for generating a normal clock, and in response to the scan clock, a first loop connection circuit formed between the input buffer group and the output buffer group scans predetermined data. A second loop connection circuit formed by the storage means including the first scan means and the first flip-flop group of the internal circuit and the input buffer group, the second flip-flop group of the internal circuit, and the output buffer Any one of the third loop connection circuit formed between the groups and the second scanning means for scanning predetermined data, and the parallel output of the parallel output in response to the normal signal and the first combination circuit and the first combination circuit. Predetermined by the flip-flop group, the second combination circuit group, the second flip-flop group, and the third combination circuit And internal operation means is changed to a value output to the output buffer group are operated alternately in to operate randomly all of the internal circuitry.

The first scanning means stores the signal supplied to the parallel input terminal and the serial input terminal and outputs the signal from the parallel output terminal to the next stage, or the serial input of the output buffer group from the serial output terminal. An input buffer group having a function of outputting serial data to an end, the first combination circuit to which parallel outputs of these input buffer groups are supplied, and the first combination circuit to which outputs of the first combination circuit are supplied. One internal flip-flop group, the second combinational circuit to which the outputs of these first internal flip-flop groups are supplied, and these second combinational circuits.
Second internal flip-flop group to which the output of the combination circuit is supplied, the third combination circuit group to which the output of the second internal flip-flop group is supplied, and these third combination circuit group. From the input buffer group to the output terminal or store the serial data supplied from the input buffer group to the serial input terminal and output the serial data to the serial input terminal of the input buffer group. The output buffer group having a function to perform, the serial data of the input buffer group to the serial input terminal of the output buffer group in response to the serial scan signal, the serial data of the output buffer group is the input buffer group. Of the input buffer group in response to the normal signal. It can be configured to be parallel output from the output buffer group by serial first combination the internal operation means being parallel output to the circuit.

Further, the second scanning means stores the signal supplied to the parallel input terminal and the serial input terminal and outputs the signal from the parallel output terminal to the next stage or from the serial output terminal to the first internal flip-flop. From the input buffer group having a function of outputting serial data to the serial input terminal of the group, the first combination circuit to which parallel data is supplied from these input buffer groups, and the first combination circuit, respectively. The first function having a function of storing the combined output supplied and outputting the parallel output from the parallel output terminal to the next stage or storing the serial data supplied from the input buffer group and outputting the serial data to the serial input terminal of the input buffer group. Internal flip-flops and the parallel outputs of these first internal flip-flops are supplied. The second combinational circuit and the combined output supplied from each of the second combinational circuits are stored and output from the parallel output terminal to the next stage, or serial data supplied from the output buffer group is stored. The second internal flip-flop group having a function of outputting to the serial input terminal of the output buffer group, the third combination circuit group to which the output of the second flip-flop group is supplied, and the third combination circuit group thereof. The combined output supplied from the combination circuit group is stored and output to the output terminal, or the serial data supplied from the second flip-flop group is stored and serially output to the serial input terminal of the second flip-flop group. And the output buffer group having a function of performing the serial buffer of the input buffer group in response to the serial scan signal. The output is first
To the serial input terminal of the internal flip-flop circuit, and the serial output of the second internal flip-flop group is supplied to the serial input terminal of the output buffer group, respectively. Each output of the flip-flop group is supplied to each of the first, second and third combination circuits in response to the normal signal so that each of the first, second and third combination circuits operates randomly. In addition, the internal operation means may be configured to output in parallel from the output buffer group.

Further, the input buffer group may have a predetermined signal set at an input terminal as a parallel input only during an initial setting period, and may have only the serial input as an input signal during the internal operation period by the normal signal. .

Further, either one or both of the front stage and the rear stage of the second combination circuit are serially connected in a loop form in which a parallel output is supplied to a predetermined combination circuit and a parallel output is supplied from this combination circuit. A plurality of sets of the internal flip-flop groups may be provided.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a timing chart of a multi-phase clock generation circuit in the first embodiment, and FIG. 3 is a timing chart of the first embodiment. It is a timing chart for operation explanation.

Referring to FIG. 1, a multi-phase clock generation circuit 4 for generating a scan mode SM, a normal clock CK for operating an internal logic, and a scan clock SCK for operating a boundary scan from a test terminal BT for a dynamic BT, An input having a function of storing signals supplied to the parallel input terminal and the serial input terminal and outputting the signals from the parallel output terminal to the next stage or outputting serial data from the serial output terminal to the serial input terminals of the output buffer groups A6 to A10. Buffer groups A1 to A5, a combination circuit 1 to which parallel outputs of these input buffer groups are supplied, and an internal flip-flop (hereinafter referred to as F / F) group B to which outputs of the combination circuit 1 are supplied.
1 to B5, a combination circuit 2 to which outputs of these internal F / F groups are supplied, an internal F / F group B6 to B10 to which outputs of these combination circuits 2 are supplied, and these internal F / Fs. The combinational circuit group 3 to which the output of the group is supplied and the combined output supplied from the combinational circuit group 3 to the parallel input terminal are stored and output to the output terminal, or the input buffer groups A1 to A5 to the serial input terminal. It is configured to include output buffer groups B1 to B5 having a function of storing the supplied serial data and outputting the serial data to the serial input terminal of the input buffer group.

Generally, when a synchronous logic circuit has a boundary scan function, an input buffer group having F / FA1 to A5 → combination circuit 1 → internal F / FB1 to B5 group → combination circuit 2 → internal F / FB6 to B10 group → Combination circuit 3 → It is composed of an output buffer group having F / Fs of A6 to A10.

The scan clock SCK is distributed to the F / FA1 to A10 in the input / output buffer, and the normal clock is distributed to A1 to A10 and the internal F / FB1 to B10.

The scan mode signal SM is all F / FA1 to
A scan mode / normal mode switching signal is wired to A10 and B1 to B10. The output of the final stage F / FA 10 of the boundary scan is connected to the input of the first stage F / FA 1, and the boundary scan forms a loop.

Next, the operation will be described with reference to FIG.
During normal operation (normal), BT = 0 and the normal clock CK is in the valid state. In the BT mode (BT = 1), the multi-phase clock generation circuit 4 alternately outputs the scan clock SCK and the normal clock CK with non-overlap.

The scan mode signal SM includes SCK, and the SM bar has a waveform including CK.

A more detailed operation will be described with reference to the timing chart of FIG. First, BT mode (BT = 1)
Then, the scan mode and the normal mode alternate. When the scan mode is entered (SM = 1), the scan clock SCK is turned on (SCK = 1), and the F / F of the input / output buffer (hereinafter, referred to as the boundary scan F / F) is A6 = a061 and A7 = a071, respectively , A8 =
a081, A9 = a091, A10 = a101, A1 =
a011, A2 = a021, A3 = a031, A4 = a
041, A5 = a051.

Next, the normal mode is set (SM =
0), the normal clock is input (CK = 1), and the combinational circuits 1, 2, and 3 operate. By operating the combinational circuit 1, for example, B1 = b012, B2 = b
022, by operating the combinational circuit 2, for example, B6 = b062, B7 = b072, combinational circuit 3
Is operated, A6 = a062, A7 = a07
2, A8 = a082, A9 = a092, A10 = a10
It becomes 2. At this time, only the F / FA1 to A5 of the input buffer take in the values of the boundary scan as they are and do not take in the normal values.

That is, in the initial state of BT start, the input terminal is set to have a desired value by pulling up or pulling down to the ground potential by the connected pull-up resistor (not shown). . Therefore, these set values are set in the input buffer groups A1 to A5 at the first timing when the BT mode is set, and the scanned data is input at subsequent timings.

Next, the scan mode is set again (SM =
1), the scan clock SCK is input (SCK =
1), the data is scanned (as agreed with the shift) as indicated by the arrow in the figure, and A051 of A5 is the second SC of A6.
Shift to a position synchronized with K, A6 = A051, similarly A
7 = a062, A8 = a072, A9 = a082, A1
0 = a092 respectively. Similarly, a of A10
102 shifts to a position synchronized with the second SCK of A1, A1 = a102, A2 = a011, A3, respectively.
= A021, A4 = a031, A5 = a041,
Boundary scan F / FA1 to A10 data is 1
Bit scan.

The value of F / FA10 of the output buffer is scanned by F / FA1 of the input buffer, and the output value of A10 is returned to the input. Similarly, the normal mode is entered (SM = 0) and the normal clock is entered (CK =
1), the combinational circuits 1, 2, and 3 operate (internal operation),
In the scan mode (SM = 1, SCK = 1), the I / O scan is repeated alternately, and the inputs of the combinational circuits 1, 2, 3 are changed randomly, and the internal operation is performed randomly.

Referring to FIG. 4 which is a block diagram showing the second embodiment of the present invention and FIG. 5 which is a timing chart for explaining the operation of the second embodiment, reference is made to the first embodiment. The difference is that a circuit for looping a part of boundary scan serial output with a part of internal flip-flop shift registers is used.

That is, the signals supplied to the parallel input terminal and the serial input terminal are stored and output from the parallel output terminal to the next stage, or serial data is transferred from the serial output terminal to the serial input terminal B1 of the internal F / F group 1. The input buffer groups A1 to A5 having a function of outputting, the combination circuit 2 to which parallel data is supplied from these input buffer groups, and the combined output supplied from each of these combination circuits 2 are stored and stored from the parallel output terminal. The serial data output to the next stage or stored from the input buffer groups A1 to A5 is stored, and the input buffer groups A1 to A5 are stored.
Internal F / F with a function to output to serial input terminal A1 of
The groups B1 to B5, the combinational circuit 3 to which the parallel outputs of the internal F / F groups B1 to B5 are supplied, and the combined output supplied from each of the combinational circuits 3 are stored, and the parallel output ends are transferred to the next stage. An internal F / F group B6 to B10 having a function of outputting or storing serial data supplied from the output buffer group and outputting to the serial input terminal A6 of the output buffer group A6 to A10, and these F / F groups
A combination circuit group 3 to which the output of the / F group is supplied, and a combined output supplied from the combination circuit group 3 is stored and output to an output terminal or serial data supplied from the F / F groups B6 to B10. Memorize 3F / F group B6 to B1
The output buffer group A6 to A10 having a function of serially outputting to the serial input terminal B10 of 0.

The scan clock SCK and the normal clock CK are distributed to the boundary scan F / FA1 to A10 and the internal F / FB1 to B10. Output of F / FA5 during boundary scan is internal F / FB5
The output of the internal F / FB1 is the F / FA1 of the input buffer
Are connected to A1 to A5 to B5 to B1 to A1 to form a loop (hereinafter referred to as loop 1). Similarly, the output of the boundary scan F / FA 10 is transferred to the internal F / FB 10.
Output of internal F / FB6 is boundary scan F / FA
A10 to B10 to B6 to A6 to A10 form a loop (hereinafter referred to as loop 2).

Referring to FIG. 5, normal operation (normal)
The time is the same as in the first embodiment. BT mode (B
When T = 1), the scan clock SCK, the normal clock CK, and the scan mode signal SM are generated.
In the BT mode (BT = 1), the scan mode is set (S
M = 1), scan clock SCK is input (SCK =
1), each F / F group of the loop 1 surrounding the combinational circuit 1 has B5 = b051, B4 = b041, and B3 = b03.
1, B2 = b021, B1 = b011, A1 = a01
1, A2 = a021, A3 = a031, A4 = a04
1, A5 = a051.

The respective F / F groups of the loop 2 surrounding the combinational circuit 3 are A6 = a061 and A7 = a0 in B10 to B6 to A6 to A10 to B10 (hereinafter referred to as loop 2).
71, A8 = a081, A9 = a091, A10 = a1
01, B10 = b101, B09 = b091, B08 =
Let b081, B07 = b071, and B06 = b061.

The normal mode is entered (SM = 0), the normal clock is entered (CK = 1), and the combinational circuits 1, 2, and 3 operate. By operating the combinational circuit 1, for example, B2 = b022 and B1 = b012, and by operating the combinational circuit 2, B10 =
= B102, B09 = b092, and by operating the combinational circuit 3, A9 = a092, A10 = a
It becomes 102. At this time, F / FA1 to A5 of the input buffer
Similar to the first embodiment, only the scan value is captured as it is, and the normal value is not captured.

Next, the scan mode is entered again (SM =
1), the scan clock SCK is input (SCK =
1), the data of each F / F is 1 in loop 1 and loop 2
Bit scan, a051 of A5 is the second SCK
Shift to B5 at the position synchronized with, and b052 of B5 is B
4 is sequentially shifted, and b012 of B1 is shifted to A1.

A1 in the input buffer groups A1 to A5
A011 of A2 shifts to A2, and a021 of A2 shifts to A3. That is, each F / F has B5 = b051, B4
= B052, B3 = b042, B2 = b032, B1 =
b022, A1 = b012, A2 = a011, A3 = b
021, A4 = a031, A5 = a041, and A6
Shifts B062 of B6 to a062 of A6 to A7,
Similarly, A6 = b062, A7 = a062, A8 = a
072, A9 = a082, A10 = a092, B10 =
a102, B09 = b102, B8 = b092, B7 =
b082 and B6 = b072.

That is, the value of the internal F / FB1 is scanned and returned to the F / FA1 of the input buffer, and similarly, the value of the F / FA10 of the output buffer is scanned and returned to the internal F / FB10. Normal mode (SM =
0), the normal clock is turned on (CK = 1), the combinational circuits 1, 2 and 3 operate (internal operation), and the scan operation is alternately repeated in the scan mode (SM = 1, SCK = 1). A few inputs change randomly and work internally at random.

Further, the above-mentioned F / F loop can be further formed into a plurality of loops, for example, the combination circuit 2
It is also possible to provide a plurality of sets of internal F / F groups serially connected in a loop, which supplies a parallel output to a predetermined combination circuit and a parallel output is supplied from this combination circuit, in one or both of the preceding stage and the subsequent stage. Similarly, by repeating the scan operation and the normal operation in the same manner, the combinational circuits 1, 2, and 3 can be randomly operated internally.

As described above, the first and second aspects of the present invention
According to the embodiment of the present invention, in any case, all the internal circuits of the semiconductor integrated circuit can be operated randomly by using the 1-pin dynamic BT terminal, which contributes to the improvement of reliability.

[0039]

As described above, the integrated circuit testing method according to the present invention is applied to the B supplied from the dynamic BT terminal.
In response to the T control signal, the memory means is serially connected to form a loop state, and the scan state in which the serial output is returned to the serial input and the internal operation state in which the stored contents of the memory means are output in parallel are alternately repeated. A multi-phase clock generation circuit that generates a scan mode signal that controls the scan clock, a scan clock that becomes active in the scan state, and a normal clock that becomes active in the internal operation state are provided. A storage means and an input buffer group each including a first scanning means for scanning predetermined data by a first loop connection circuit formed between the input buffer group and the output buffer group, and a first F / F group of the internal circuit. Formed between the second loop connection circuit to be formed and the second F / F group and output buffer group of the internal circuit Any one of the second scan means for scanning predetermined data with the loop connection circuit of No. 3, and the parallel output in response to the normal signal, the first combination circuit, the first F / F group, and the second Since the internal operating means for outputting to the output buffer group via the combination circuit group, the second F / F group and the third combination circuit are alternately operated, all the internal circuits are operated at random. By using the 1-pin dynamic BT terminal, all the internal circuits of the semiconductor integrated circuit can be operated at random, which has the effect of contributing to the improvement of reliability.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention,

FIG. 2 is a timing chart of the multi-phase clock generation circuit according to the first embodiment.

FIG. 3 is a timing chart for explaining the operation of the first embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the second embodiment.

FIG. 6 is a block diagram showing an example of a conventional BT test circuit.

[Explanation of symbols]

1, 2 and 3 Combination circuit 4 Multi-phase clock generation circuit A1 to A10 F / F (boundary scan register) of input buffer and output buffer B1 to B10 Internal F / F BT dynamic BT terminal SM scan mode switching signal CK normal Clock SCK Scan clock 61 Shift clock generation circuit 62 Shift-in data generation circuit 63 Main circuit 64 CLK terminal 65 BT terminal 66 SFT terminal 67 SIN terminal 68 Inverter 69 OR gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/822 H01L 27/04 T

Claims (5)

[Claims] 1. A semiconductor integrated circuit testing device for dynamic burn-in, wherein screening is performed while operating an internal circuit of the semiconductor integrated circuit in order to eliminate initial failures such as oxide film defects and contact defects of the semiconductor integrated circuit. When the control signal for shifting to the dynamic burn-in test state is supplied from the test terminal, the memory means is serially connected to form a loop state and the serial output is returned to the serial input and the scan state and the memory means A scan mode signal for controlling so as to alternately repeat the internal operation state in which the stored contents are output in parallel, a scan clock that becomes active in the scan state, and a normal clock that becomes active in the internal operation state. A multi-phase clock generator that generates First scan means for causing the first loop connection circuit formed between the input buffer group and the output buffer group to scan predetermined data in response to the scan clock, and the first flip-flop of the internal circuit. A second loop connection circuit formed by the storage means and the input buffer group, and a third flip connection circuit formed between the second flip-flop group and the output buffer group of the internal circuit, respectively. Any one of the second scanning means for scanning predetermined data, and the parallel output in response to the normal signal to the first combination circuit, the first flip-flop group, the second combination circuit group, and the second combination circuit group. Internal operating means for changing the value to a predetermined value by the flip-flop group and the third combination circuit and outputting the value to the output buffer group. Test apparatus for a semiconductor integrated circuit, characterized in that alternately is operated to operate randomly all of the internal circuitry. 2. The first scanning means stores a signal supplied to a parallel input terminal and a serial input terminal and outputs the signal from a parallel output terminal to a next stage, or a serial input of the output buffer group from a serial output terminal. Input buffer groups having a function of outputting serial data to the end, and the first output to which parallel outputs of these input buffer groups are supplied.
Combination circuit, the first internal flip-flop group to which outputs of the first combination circuit are supplied, and the second combination circuit to which outputs of the first internal flip-flop group are supplied. A second internal flip-flop group to which outputs of the second combinational circuits are supplied, and a third combinational circuit group to which outputs of the second internal flip-flops are supplied,
The composite output supplied from the third combination circuit group to the parallel input terminal is stored and output to the output terminal, or the serial data supplied from the input buffer group to the serial input terminal is stored and stored in the input buffer group. The output buffer group having the function of outputting serial data to a serial input terminal, wherein the serial data of the input buffer group is transferred to the serial input terminal of the output buffer group in response to the serial scan signal. Serial data are output to serial input terminals of the input buffer group, and in response to the normal signal, the data of the input buffer group are output in parallel to the first combination circuit, and the internal operating means outputs the output buffer. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuits are configured to output in parallel from groups. Test methods. 3. The second scanning means stores the signal supplied to the parallel input terminal and the serial input terminal and outputs the signal from the parallel output terminal to the next stage or from the serial output terminal to the first internal flip-flop. From the input buffer group having a function of outputting serial data to the serial input terminals of the group, the first combination circuit to which parallel data is supplied from these input buffer groups, and the first combination circuit, respectively. The first function having a function of storing the supplied combined output and outputting the parallel output from the parallel output terminal to the next stage or storing the serial data supplied from the input buffer group and outputting the serial data to the serial input terminal of the input buffer group Internal flip-flops of
The second combinational circuit to which the parallel output of the first internal flip-flop group is supplied, and the combined output supplied from each of the second combinational circuits are stored and output from the parallel output end to the next stage. Alternatively, the second internal flip-flop group having the function of storing the serial data supplied from the output buffer group and outputting the serial data to the serial input terminal of the output buffer group, and the output of the second flip-flop group are The third combination circuit group supplied and the combined output supplied from these third combination circuit groups are stored and output to an output terminal, or serial data supplied from the second flip-flop group is stored. The output buffer group having a function of storing and serially outputting to a serial input terminal of the second flip-flop group, In response to the serial scan signal, the serial output of the input buffer group is connected to the serial input terminal of the first internal flip-flop circuit, and the serial output of the second internal flip-flop circuit is connected to the serial input terminal of the output buffer group. And the respective outputs of the input buffer group and the first and second internal flip-flop groups are respectively supplied to the first, second and third combination circuits in response to the normal signal. 2. The test of a semiconductor integrated circuit according to claim 1, wherein each of the first, second and third combination circuits operates randomly and is output in parallel from the output buffer group by the internal operating means. Method. 4. The input buffer group uses a predetermined signal set in an input terminal as a parallel input only during an initial setting period,
The semiconductor integrated circuit testing method according to claim 1, wherein only the serial input is used as an input signal during the internal operation period of the normal signal. 5. A serial connection in a loop form in which a parallel output is supplied to a predetermined combination circuit and a parallel output is supplied from this combination circuit to one or both of the front stage and the rear stage of the second combination circuit. 4. The semiconductor integrated circuit testing method according to claim 3, comprising a plurality of sets of the internal flip-flop groups.