JPH03181132A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To improve quality of a substrate and simplify a manufacturing process by adhering semiconductor substrates having a stage to each other to form a uniform island-like semiconductor region so as to reduce roughness of the region surface. CONSTITUTION:An element forming part 2 in a protruding shape is formed on a silicon wafer 1, an SiO2 film 3 and an SiN film 4 different in etching characteristics are laminated thereon and a layer 5 for flattening is adhered. Then the wafer 1 is adhered to another wafer 6, and the wafer 1 is selectively polished from the rear face until an island-like silicon region 2 is exposed. Then by etching the film 2 exposed together with the region 2, the lower film 4 is exposed as well as the upper face of the region 2 protrudes from the upper face of the film 4. Then by grinding a part of the region 2 exposed with the film 4 as a stopper and removing unevenness in thickness caused by the selective polishing, the upper face of the region 2 is flattened. Thus quality of a substrate can be improved and manufacturing is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is directed to a semiconductor substrate having a semiconductor thin layer formed on the substrate through an insulating film, the so-called S○■ (silicon On).
The present invention relates to a method for manufacturing a substrate, particularly to a method for manufacturing an S○■ substrate having a plurality of island-shaped semiconductor regions by bonding semiconductor substrates having steps.

[Summary of the invention]

The present invention provides S
A method for manufacturing an OI substrate includes a step of laminating first and second insulating films having different etching characteristics on a main surface having a step of a semiconductor substrate, a step of bonding the semiconductor substrate with another substrate, and a step of laminating the semiconductor substrate with another substrate; a step of selectively polishing the semiconductor substrate until all of the plurality of island-shaped semiconductor regions partitioned by the first insulating film are exposed; etching away the first insulating film; , a step of exposing a second insulating film around the island-shaped semiconductor region;
polishing the island-shaped semiconductor region using the exposed surface of the insulating film as a stopper, or forming an insulating film on the stepped main surface of the semiconductor substrate;
a step of bonding the semiconductor substrate with another substrate; a step of selectively polishing the semiconductor substrate until all of the plurality of island-shaped semiconductor regions partitioned by the insulating film are exposed; A uniform island shape is formed over the entire surface of the substrate by including the steps of etching the insulating film around the semiconductor region part way and polishing the island-shaped semiconductor region using the etched surface of the insulating film as a stopper. In addition to making it possible to form a semiconductor region, it is also possible to reduce the surface roughness and damage of the island-shaped semiconductor region, thereby realizing high quality SOI substrates.

The present invention also provides the method for manufacturing an SOI substrate, including a step of forming an insulating film on a main surface having a step of a semiconductor substrate;
a step of bonding the semiconductor substrate with another substrate; a step of selectively polishing the semiconductor substrate until all of the plurality of island-shaped semiconductor regions partitioned by the insulating film are exposed; By including the step of polishing the insulating film around the semiconductor region part way along with the island-shaped semiconductor region, it is possible to form a uniform island-shaped semiconductor region over the entire surface of the substrate, and to reduce the roughness of the surface of the island-shaped semiconductor region. The present invention is designed to improve the quality of SOI substrates and to simplify the manufacturing process of SOI substrates.

BACKGROUND OF THE INVENTION [Background Art] Recently, progress has been made in the development of manufacturing VLSIs using so-called SOI substrates in which a thin single-crystal silicon layer is formed on an insulating layer. Among the various SOI substrate manufacturing methods, the bonding method is considered to have the best crystallinity and superior properties (for example, low parasitic capacitance and kink phenomenon).

The bonding method involves creating a step on the main surface of one mirror-surfaced semiconductor wafer, oxidizing it, and then filling the step with a planarizing layer such as a 5102 film or a polycrystalline silicon layer. This is a method of flattening the layer and bonding it to another semiconductor wafer with a mirror surface, and then polishing one semiconductor wafer until it becomes a thin film to form a plurality of island-shaped semiconductor regions (device formation B).

To explain specifically using FIG. 12, first, as shown in FIG. Patterning is done so that there are differences in level.

Next, a 5in2 film (63) is formed on the main surface where the step is formed, and a flattening layer (64) such as an SlO□ layer or a polycrystalline silicon layer is formed on the entire surface in order to fill the step. The surface of this layer (64) is polished flat.

Next, as shown in Figure B, another mirror-finished silicon wafer <65> is bonded to the surface of the planarization layer <64>, and then, as shown in Figure C, the back side of the silicon wafer (61> After grinding to the A side, selective polishing with a hard cloth (a polishing method that only wipes off the product of ethylenediamine and Si in the polishing liquid without adding abrasive grains) was performed to polish the B side, that is, the S1 opening □ film (63 ) until the surface of the element forming part (
62) is exposed and the SiO□ film (
13) a plurality of island-shaped semiconductor regions (i.e.,
An SO engineered substrate (B) having an element forming portion) (62) was obtained.

[Problem to be solved by the invention]

However, the thickness of the island-shaped semiconductor region <62> is approximately 10
When manufacturing an SOI substrate for 000 people, it is impossible to simply bond and polish as in the past. That is, in the case of the conventional method, an island-shaped semiconductor region (6
Even if 2) is exposed, the peripheral area of the wafer is
There is a problem in that Si still remains and the mark for mask alignment is hidden, making subsequent device fabrication, especially mask alignment, difficult. Moreover, even if the Si in the peripheral part is removed, the island-shaped semiconductor region (62
) are all removed, making it impossible to fabricate a device.

In addition, during selective polishing, since the Sl is polished by wiping, as shown in Figure 12, even if it is attempted to leave a desired thickness of Si on the island-shaped semiconductor region 62), the island in the center of the wafer is From the semiconductor region (62) to the island semiconductor region (62) at the periphery of the wafer, the depth is 21~.
A depression (i.e., thickness unevenness) (67) of a degree of z. In addition, the film thickness control, exposure, and development in subsequent device fabrication must be performed while taking the above-mentioned depressions into consideration, resulting in an inconvenience that the process becomes extremely complicated.

In addition, since a hard cloth is used, the island-shaped semiconductor region <12
〉 surface roughness and its damage are a concern.

The present invention has been developed in view of these points, and its purpose is to form a uniform island-shaped semiconductor region over the entire surface of a wafer, and to reduce surface roughness and damage of the island-shaped semiconductor region. The purpose of the present invention is to provide a method for manufacturing a semiconductor substrate that can be made into a semiconductor substrate.

Further, according to the present invention, uniform island-shaped semiconductor regions can be formed over the entire surface of the wafer, and the surface roughness of the island-shaped semiconductor regions can be reduced, and furthermore, the manufacturing process of the SO substrate can be simplified. The purpose of the present invention is to provide a method for manufacturing a semiconductor substrate.

[Means to solve the problem]

The method for manufacturing a semiconductor substrate of the present invention is to stack first and second insulating films (3) and (4) having mutually different etching characteristics on the main surface of a semiconductor substrate (1) having a step, and then to form a semiconductor substrate. (1) and another substrate (6) are bonded together, and then the semiconductor substrate (1) is heated, for example, by a hard film, until all of the plurality of island-shaped semiconductor regions (2) partitioned by the first insulating film (3) are exposed. After selectively polishing using a cloth, the exposed first insulating film (3) is removed by etching to remove the second insulating film (4) around the island-shaped semiconductor region (2). The film (4) is exposed, and then the island-shaped semiconductor region (2) is polished using the exposed surface of the second insulating film (4) as a stopper.

Further, the method for manufacturing a semiconductor substrate of the present invention includes a semiconductor substrate (1)
After forming an insulating film (11) on the main surface having a step,
The semiconductor substrate (1) and another substrate (6) were bonded together, and then the semiconductor substrate (1) was selectively polished until all of the plurality of island-shaped semiconductor regions (2) partitioned by insulating films (11) were exposed. Later, in the insulating film (11), the island-shaped semiconductor region (2)
The exposed insulating film (11) around the periphery of the insulating film (11) is etched halfway, and then the island-shaped semiconductor region (2) is removed using the surface of the etched insulating film (11) as a stopper.
Polish.

Further, the method for manufacturing a semiconductor substrate of the present invention includes a semiconductor substrate (1)
After forming an insulating film (21) on the main surface having a step,
The semiconductor substrate (1) and another substrate (6) were bonded together, and then the semiconductor substrate (1) was selectively polished until all of the plurality of island-shaped semiconductor regions (2) partitioned by insulating films (21) were exposed. Later, in the insulating film (21), the island-shaped semiconductor region (2)
The exposed insulating film (21) around the periphery of the insulating film (21) is partially polished together with the island-shaped semiconductor region (2).

[Effect]

According to the above-mentioned manufacturing method of the present invention, first and second insulating films (3) and (4) having different etching properties are stacked and provided, and at least the first insulating film (3) is formed as a stopper. When selective polishing is performed to expose all of the plurality of island-shaped semiconductor regions (2) partitioned by the first insulating film (3), the state of the island-shaped semiconductor regions (2) after polishing is that of an island-shaped semiconductor. Area (2) Thickness unevenness occurs when looking at a single unit and when looking at the entire wafer, and the thickness is not uniform over the entire wafer, but the thickness unevenness (thickness difference) (
7) is as small as the thickness of the first insulating film (3), so
In the next step, after removing the first insulating film (3) by etching, the island-like semiconductor region (2) is polished using the second insulating film [4] as a stopper.
The thickness can be made uniform over the entire wafer surface, and the surface roughness and damage of the island-shaped semiconductor region (2) caused during selective polishing can be reduced.

Further, according to the manufacturing method of the present invention described above, first, an insulating film (1
1) and using this insulating film (11) as a stopper, a plurality of island-shaped semiconductor regions (2) partitioned by insulating films <11> are formed.
When selective polishing is performed so that all of The thickness unevenness occurs and the thickness is not uniform over the entire wafer, but the thickness unevenness (thickness difference) (7)
Since the film thickness is smaller than that of the insulating film (11), the insulating film (11) is etched halfway in the next step, and then the island-shaped semiconductor region (2) is etched using the etched surface of the insulating film (11) as a stopper. ), the thickness of the island-shaped semiconductor region (2) can be made uniform over the entire wafer surface, and the surface roughness and damage of the island-shaped semiconductor region [2] caused during selective polishing can be reduced. can do.

Further, according to the manufacturing method of the present invention described above, first, the insulating film (2
1), and a plurality of island-shaped semiconductor regions (2) partitioned by insulating films (21) using this insulating film (21> as a stopper).
When selectively polishing is performed so that all of Thickness unevenness occurs and the thickness is not uniform over the entire surface of the wafer, but since the thickness unevenness (thickness difference) (7) is smaller than the thickness of the insulating film (21), the insulating film (21) is ) can be polished halfway along with the island-shaped semiconductor region (2), so that the thickness of the island-shaped semiconductor region (2) can be made uniform over the entire wafer surface, and the island-shaped semiconductor region (2) generated during selective polishing can be made uniform. surface roughness can be reduced. In particular, according to this method, the manufacturing process can be simplified.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to FIGS. 1 to 11.

FIG. 1 is a process diagram showing a method for manufacturing an SOI substrate according to a first embodiment. The steps will be explained step by step below.

First, as shown in Fig. 1, a plurality of element forming portions (2) are uniformly formed on the main surface of a mirror-finished silicon wafer (1) using photolithography to form convex portions over the entire surface. Butter it so that it remains in steps. The thickness of the convex portion d. is approximately 2000 A.

Then, etching characteristics (
The first and second insulating films have different etching rates and serve as polishing stoppers of s1, for example, with a thickness of about 1000
A 5in2 film [3] and SiN with a thickness of 1000 Å or more
The membranes (4) are laminated one after another. Furthermore, a layer (5) for planarization such as a SiO□ layer or a polycrystalline silicon layer is deposited to fill these steps, and then this layer (5) is planarized.

Next, as shown in FIG. 1B, another mirror-finished silicon wafer (6) is bonded to the flattened surface a.

Next, as shown in FIG. 1C, a silicon wafer (1)
After grinding from the back side to side A, polishing is performed to side B by selective polishing with a hard cloth using the 5102 film (3) as a polishing stopper. At this time, as shown in the first diagram, a plurality of island-like silicon regions (2) are exposed, and each island-like silicon region (2) in the central part to the island-like silicon region (2) in the peripheral part has a depth. A depression (7) of 21 to Z is formed. This depression (7) causes thickness unevenness in the island-shaped silicon region (2) alone and thickness unevenness in the entire surface of the wafer (6). It is in a state of dispersion. This is because the pressure of the hard cloth, which is an elastic body, is high at the center of each island-like silicon region (2), and the polishing rate also increases proportionally at the center of the island-like silicon region (2). It can be inferred that. At this time, the depth Z of the depression (7) formed in the island-like silicon region (2) is approximately the thickness of the 5102 film (3) even at its maximum (2+ in the first diagram).

In addition, since this selective polishing uses a hard cloth with a strong wiping action and a selective polishing liquid, the state of the island-shaped silicon region (2) after polishing is such that the surface roughness deteriorates and damage occurs. The situation has occurred.

Next, as shown in FIG. 1, the Sin film (3) is etched with a hydrofluoric acid-based etching solution to remove the exposed 5in2 film (3). At this time, the underlying SiN film (4) is exposed, and the island-like silicon region (
2) The upper surface protrudes from the upper surface of the SiN film (4) by about 1000 mm, and the bottom (peak) of the depression (7) is also at the same level as or above the upper surface of the SiN film (4). In addition, the island-like silicon region (2)
The upper surface of the nearby SiO□ film (3) is slightly depressed than the upper surface of the SiN film (4) due to over-etching caused by the above etching process.

Next, as shown in FIG. The SOI according to this example was polished up to 6 sides with a so-called colloidal silica polishing liquid containing silica.
Obtain a substrate <A1).

When polishing up to six surfaces, the outer periphery of each island-like silicon region (2) protrudes upwardly from the center, so the outer periphery is polished preferentially during polishing.
That is, the top surface of the island-shaped silicon region (2) is flattened by the shape correction effect of polishing.

In particular, since the bottom of the depression (7) is at the same level as or above the top surface of the SiN film (4), this polishing
The depression (7) is completely eliminated and flattened, and the Si
The upper surface of the N film (4) and the upper surface of the island-like silicon region (2) are on the same plane, and the island-like silicon region (2) with a thickness of 1000 layers is uniformly distributed over the entire surface of the wafer (6). It happens. Furthermore, if the polishing rate ratio of Si and Sin is all and the polishing rate ratio of Si and SIN is b:1, the total polishing rate ratio is ab:l.
In order to obtain a polishing rate ratio of 100:1 or more, which is expected to flatten the island-shaped silicon region (2), use Si and Si.

For example, the polishing rate ratio is 10:1. For example, a polishing rate ratio of Si to SiN of 20: A polishing rate ratio with a small process rate is sufficient, and the total polishing rate ratio in this case is 20.
00:1.

As described above, according to this example, after the 3102 film (3) and the SiN film (4) are sequentially laminated on the stepped main surface of the wafer (1), this wafer (1) and another wafer (6) are laminated.
After that, the island-shaped silicon region (2) is exposed by selective polishing with a hard cloth, and the exposed Sin and film (3) are etched away together with the region (2). A part of the region (2) is made to protrude, and then a part of the exposed island-shaped silicon region (2) is polished using a soft cloth using the SIN film (4) as a stopper, so that the problem that occurs during selective polishing is avoided. The thickness unevenness, that is, the depression (7) is removed, and the upper surface of the island-like silicon region (2) can be flattened, and the thickness of the island-like silicon region (2) can be made uniform over the entire surface of the wafer (6). This facilitates subsequent device fabrication. In addition, the required thickness (1000 mm
200 people, considering the thickness to be polished (1000 people)
If the number of workers is set to 0, the thickness of the island-shaped silicon region (2) can be uniformized to the desired thickness (1000 workers) over the entire surface of the wafer 71 in the final step (FIG. 1F). When polishing the island-like silicon region (2) in , polishing was performed using a soft cloth and abrasive-containing polishing liquid, so that the surface of the island-like silicon region (2) that occurred during selective polishing as shown in Figure 1C was removed. Roughness and polishing damage can be reduced.

Next, a method for manufacturing the S○■ substrate according to the second embodiment will be explained based on the process diagram of FIG. 2. Components corresponding to those in FIG. 1 are designated by the same reference numerals.

First, as shown in FIG. 2A, a plurality of element forming portions (2) are uniformly formed on the main surface of a mirror-finished silicon wafer (1) using photolithography to form convex portions over the entire surface. Pattern so that it remains with steps. The thickness do of the convex portion is approximately 4000.

Next, an insulating film, for example, about 4 mm in thickness is applied to the surface on which the step is formed.
000 SiO□ film (11) is formed. Furthermore, a layer (5) for planarization such as a SlO□ layer or a polycrystalline silicon layer is deposited to fill these steps, and then this layer (5) is planarized.

Next, as shown in FIG. 2B, another mirror-finished silicon wafer (6) is bonded to the flattened surface a.

Next, as shown in FIG. 2C, the silicon wafer (1)
After grinding from the underside to the A side, SiQ, film (11)
Using a polishing stopper as a polishing stopper, selectively polish with a hard cloth to the B side. At this time, as shown in the second diagram, a plurality of island-like silicon regions (2) are exposed, and
Recesses (7) with depths Z, ~Z, are formed from the island-like silicon region (2) in the central part to the island-like silicon region (2) in the peripheral part, respectively. As in the case of the first embodiment, this depression (7) causes thickness unevenness in the island-shaped silicon region (2) alone and thickness unevenness in the entire surface of the wafer (6). , island-like silicon region (2)
The thickness of the material varies. However, due to the difference in polishing rate between Si and SiO (polishing rate ratio = 10:1), the depth Z of this depression (7) is less than 1000 Å even at its maximum (2+ in Figure 2 E). , which is smaller than the thickness of the 5102 film (11). Since the selective polishing uses a hard cloth with a strong wiping action and a selective polishing liquid, the state of the island-like silicon region (2) after polishing is as follows as in the first embodiment.
The surface roughness has deteriorated and damage has occurred.

Next, as shown in Figure 2E, the S10° film (11) is
5102 exposed by etching by wet etching using IE (CHF3 gas) or HF solution
The film (11) is removed halfway, that is, about 1,000 layers, and the Sl
A second reference surface is formed by the O□ film (11). At this time, the upper surface of the island-like silicon region (2) protrudes from the second reference surface by about 4,000 people, and a depression (
The lowest point (peak) of 7) is also located at or above the second reference plane.

Next, as shown in FIG. 2F, a second reference surface made of 5i02 film (11) was used as a polishing stopper, and a soft cloth and a polishing liquid containing abrasive grains (for example, a colloidal silica-based polishing liquid) were used to polish the surface.
The surface is polished to obtain an S○■ substrate (A2>) according to this example.

When polishing up to six surfaces, the outer peripheral portion of each island-like silicon region (2) protrudes upwardly than the central portion, as in the first embodiment. is preferentially polished, that is, the top surface of the island-like silicon region (2) is flattened due to the shape correction effect of polishing.

In particular, since the lowest part of the depression (7) is on the same level as or above the second reference surface formed by the 5in2 film (11), this polishing completely eliminates the depression (7) and makes it flat. The island-like silicon region (
2) The upper surface will be on the same plane, and an island-like silicon region (2) with a thickness of 1000 layers will be uniformly formed over the entire surface of the wafer. In addition, by simply setting the polishing rate ratio of Si and SiO□ to about 1O:1, the total polishing rate ratio can be increased to 100:1, which is sufficient for flattening the island-shaped silicon region (2). Become.

As described above, according to this example, after forming the 5I02 film (11) on the stepped main surface of the wafer (1), this wafer (1) and another wafer (6) are bonded together, and then a hard After exposing the island-like silicon region (2) by selective polishing with a cloth, the island-like silicon region (2) is exposed.
), the exposed Si20 film (11) is partially etched away to expose the part of the island-shaped silicon region (2), and then the etched Si20 film (11)
A part of the protruding island-like silicon region (2) was polished using a soft cloth using the film (11>) as a stopper.
Thickness unevenness or depressions caused during selective polishing (7)
is removed, the flatness of the island-like silicon region [2] is improved, and the thickness of the island-like silicon region [2] can be made uniform over the entire surface of the wafer (6), making subsequent device fabrication easier. Become. In addition, the same effect as the two-stage stopper combining the Si and film (4) shown in the first embodiment can be obtained only with the SiO□ film (11).
The process is further simplified, and the island-like silicon region (2) can be highly integrated. In addition, if the step (thickness d of the convex part) of the wafer (1) is set to 2000 people in advance, taking into consideration the thickness required for the element formation area (1000 people) and the thickness to be polished (1000 people), the final step (Figure 2 F)
The thickness of the island-like silicon region (2) can be made uniform to a desired thickness (1000 layers) over the entire surface of the wafer (6). In addition, when polishing the island-shaped silicon region (2) in FIG. 2F, polishing was performed using a soft cloth and a polishing liquid containing abrasive grains, so that the island-shaped silicon region (2) produced during selective polishing as shown in FIG. 2C (2) Surface roughness and polishing damage can be reduced.

Next, a method for manufacturing an SOI substrate according to a third embodiment will be explained based on the process diagram of FIG. 3. Components corresponding to those in FIG. 1 are designated by the same reference numerals.

First, as shown in FIG. 3A, a plurality of element forming portions (2) are uniformly formed on the main surface of a mirror-finished silicon wafer (1) using photolithography to form convex portions over the entire surface. Butter it so that it remains in steps. The thickness of the convex portion d. The number of participants will be approximately 4,000.

Next, an insulating film, for example, about 4 mm in thickness is applied to the surface on which the step is formed.
Form 5102 membranes (21) of 000 people. Furthermore, a layer (5) for planarization such as a 310□ layer or a polycrystalline silicon layer is deposited to fill these steps, and then this layer (5) is planarized.

Next, as shown in FIG. 2B, another mirror-finished silicon wafer (6) is bonded to the flattened surface a.

Next, as shown in FIG. 2C, the silicon wafer (1)
After grinding from the back side to the A side, SiO3 film (21)
Using a polishing stopper as a polishing stopper, selectively polish with a hard cloth to the B side. At this time, as shown in the second diagram, a plurality of island-like silicon regions (2) are exposed, and
Recesses (7) having depths Z1 to Z are formed from the island-like silicon region (2) in the central part to the island-like silicon region (2) in the peripheral part, respectively. As in the case of the first embodiment, this depression (7) causes thickness unevenness in the island-shaped silicon region (2) alone and thickness unevenness in the entire surface of the wafer (6). , island-like silicon region (2)
The thickness of the material varies. However, due to the difference in polishing rate between Sl and 3102 (polishing rate ratio = 10:1), the depth Z of this depression (7) is less than 1000 A even at its maximum (Z, in the third drawing). The thickness of the 5102 film (21) is smaller than that of the 5102 film (21).The selective polishing described above uses a hard cloth with a strong wiping action and a selective polishing liquid. The state of the island-shaped silicon region (2) in is such that its surface roughness has deteriorated and damage has also occurred.

Next, as shown in FIG. 3E, an island-like silicon region (2) is formed.
By polishing the entire surface including the Si film (21) along with the island-like silicon region (2) to the middle (that is, to the 0th surface), about 4000 particles were removed by polishing. An SOI substrate (A3) is obtained. This polishing method mainly involves mechanical polishing, for example, using a hard cloth and a suspension of 5iO7 fine powder with a particle size removal degree of 300 and water (
A polishing method using a polishing liquid (polishing liquid) or a polishing liquid such as HF-H in which Sl and 5i02 are etched at the same etching rate.
A polishing method using an NO3-based polishing liquid is used. This Si
During the simultaneous polishing of the O□ film 21) and the island-like silicon region (2), the depression (7) of the island-like silicon region (2) created during selective polishing has its lowest bottom facing the polishing stop surface (
0 side) or above it,
By this polishing, the depression (7) is completely eliminated and flattened, and the polishing stop surface (plane 0) and the island-like silicon region (plane 2
) are on the same plane as the upper surface of the wafer (6), and an island-like silicon region (2
) will be formed uniformly.

As described above, according to this example, after forming the 310□ film (21) on the main surface of the wafer (1) having a step, this wafer (1) and another wafer (6) are bonded together, and then, After exposing the island-like silicon region (2) by selective polishing with a hard cloth, the SiO□ film <21> was polished halfway along with the island-like silicon region (2), so that the thickness unevenness that occurred during selective polishing was removed. That is, the depression (7) is removed, the flatness of the island-like silicon region (2) is improved, and the thickness of the island-like silicon region (2) can be made uniform over the entire surface of the wafer (6).
Subsequent device fabrication is facilitated, and its yield and reliability are improved. In addition, in advance, the step (thickness do of the convex portion) of the wafer (1) is set to the required thickness (10
00 people〉 and considering the thickness to be polished (1000 people) 2
000 layers, the thickness of the island-shaped silicon region (2) can be made uniform over the entire surface of the wafer (6) to the desired thickness (1000 layers) in the final step (FIG. 3E), and The surface roughness of the island-like silicon region (2) produced during selective polishing shown in C can be reduced.

In particular, in this third embodiment, the 5in2 film (21)
Since the Sol substrate (A, ) can be obtained by simply polishing the island-like silicon region (2) to the middle of the island-like silicon region (2), the first
The process is simplified compared to the example and the second example,
Ili property is improved.

In addition, in the above-mentioned first to third embodiments, each final step (ff
i1 figure F, 2nd r! ! JF and FIG. 3E), the surface of the island-shaped silicon region (2) is thermally oxidized together with its surrounding area, and then the thermal oxide film is removed by etching, thereby reducing the roughness of the surface of the island-shaped silicon region (2). This makes it possible to more efficiently reduce polishing damage and polishing damage.

The planarization polishing process for the planarization layer (5) in the first to third embodiments (Fig. 1 A1, Fig. 2 A, and Fig. 3 A)
(see), usually, first, a polycrystalline silicon layer with a thickness of, for example, 5 μm is formed as a planarizing layer (5) on the pattern convex portion (2) on the wafer (1) by, for example, the CVD method. Polycrystalline silicon layer (
5) Polish and remove only the upper pattern convex part (5a),
Flatten the entire surface. Thereafter, the flattened surface is final polished under the polishing conditions used for regular final polishing of silicon wafers to create a mirror surface that can be bonded (that is, to remove scratches and roughness). In chemical polishing, it was found that when final polishing was performed after pattern convex portions (5a) were removed using a fixed abrasive surface plate, the pattern convex portions that were supposed to have been removed reappeared. As a result of examining the pattern convex portions with a step measuring device, it was found that convex steps and concave steps with a height of about 100 removal degree occurred within one wafer, and the following are thought to be the causes. , the convex step is because the pattern convex part (5a) is not completely removed in the first flattening polishing using the fixed abrasive surface plate (approximately 100 degree of removal remains), so it will not be removed during the next final polishing. , since the abrasive grains are small and a soft cloth is used, it does not have the ability to flatten steps, and on the contrary, it is thought that this makes it easier to see the steps that were difficult to see.In addition, the concave steps are caused by the initial fixed abrasive grains. This is probably because the convex part of the pattern (5a) becomes concave when it becomes completely flat due to flattening polishing using a surface plate. Normally, final polishing is highly selective and the progress of polishing is limited to damaged areas. In other words, during flattening polishing with a fixed abrasive grain surface plate, the pattern convex portions (5a) are preferentially removed, but the portions that come into contact with the fixed abrasive grain surface plate until flattened during this polishing are , only the pattern convex part (5a) supports the load of the fixed abrasive surface plate (the pattern convex part (5a) is in the wa/"i plane. (This accounts for approximately 20% of the pressure, which means that a fairly high pressure is applied per unit area.) Therefore, when the level difference is eliminated by flattening, the pattern convex portion (5a)
There is considerable damage to the part where there was,
It is thought that this damage causes the damaged part to be polished more quickly during the next final polishing, eventually forming a concave step.

Therefore, in this example, after flattening polishing using a fixed abrasive surface plate,
Even if some level difference remains, polishing is added to flatten the level difference, and the final polishing conditions are changed from the usual highly selective to weakly selective to polish the polycrystalline silicon layer (5). I decided to do some polishing.

That is, as shown in FIG. 4A, a flattening layer, for example, a thick After forming a 5 μm thick polycrystalline silicon layer (5) by CVD method or the like, as shown in FIG. 4B, flattening polishing is performed using a fixed abrasive surface plate (25). At this time, the pattern protrusions (5a) formed on the polycrystalline silicon layer (5) are removed and planarized.

Next, as shown in FIG. 1C, the abrasive grain size is 0.05 to 0.0.
Hard cloth (polyester nonwoven fabric impregnated with polyurethane,
Hardness: 60 or higher) Perform the first final polishing at (27) (see table ■ below).

In this first final polishing, a hard cloth (28) is used, so the polishing rate is high and minute differences, for example 100
It is possible to flatten a level difference of about 200A.

However, if this polishing is done as it is, the surface roughness is large and it is unsuitable for bonding. Therefore, in order to improve the surface roughness, the fourth
Perform the second final polishing as shown in the figure. This second final polishing is performed with an abrasive grain size of 0.0 as shown in the table ◎ above.
Polishing is performed with a soft cloth (hardness of 60 or less) (29) while dropping an alkaline polishing agent (26) of PHIO, O or less containing abrasive grains having a diameter of 5 to 0.08 μm.

In other words, while an alkaline abrasive with a PHI of 1.0 is normally used, since an alkaline abrasive (26) with a PHI of 10.0 or less is used, the selectivity is weaker than in normal cases, and the polishing surface (
Even if the polycrystalline silicon layer (5) is partially damaged, that part will not be polished preferentially, and the entire surface will be averagely finished polished.
The upper surface of the polycrystalline silicon layer (5) can be completely flattened. The polishing of the planarization layer (5) according to this example involves two stages of final polishing and an additional step compared to the normal case. Since the purpose of this polishing is to remove rough edges and the polishing rate is high, it is possible to remove minute differences caused by flattening polishing in a short time. Furthermore, since the first final polishing can bring the surface almost to a finished state, the second final polishing can also be completed in a short time. Therefore, compared to normal final polishing, the total polishing time is only 172 seconds, and there is no recurrence of pattern convex portions, resulting in good reproducibility.

In the step of polishing the surface layer of the wafer (6) in the first to third embodiments (see Fig. 1 C and F, Fig. 2 C and F, Fig. 3 C and E), the surface layer is uniformly polished. When polishing, as shown in Figure 5, an elastic material (
32), and this elastic material <32) is used to bond the wafer (
6) The surface (polishing surface) of the wafer (6) is uniformly pressed against the rigid surface plate (33) to uniformly polish the surface layer of the wafer (6) without absorbing the taper and waviness. There is. Note that (34) is a ring-shaped tenbla (31). In the case of forced polishing, the rotation speed of the rigid body surface plate (33) and the rotation speed of the pressure plate (31) are changed, and the rotation directions are set to be the same. For driven polishing, a rigid surface plate (
The rotational speed of 33) and the pressure play (31) are set to be the same, and their rotational directions are also set to be the same. Here, in the normal case, the elastic material (32) is made of silicone rubber (rubber hardness: rubber hardness = 45 ± 5 degrees according to the measurement method based on the hardness measurement of JISK-6301).
In this case, the taper and waviness of the wafer (6) as well as the curvature of the rigid surface plate (33) cannot be absorbed, and polishing of 3 to 4 μm to the surface layer of the wafer (6) results in a polishing of 0.5 to 1 μm.
A relatively large variation (polishing error) in the polishing stock m occurs. Therefore, during selective polishing (see Fig. 1 C1 Fig. 2 C1 Fig. 3 C), the depressions (7) in the island-like silicon region (2)
becomes larger, or during the second polishing (Fig. 1 F).

(See FIGS. 2F and 3E), there is a possibility that the island-like silicon region (2) cannot be flattened. Therefore, in this example, the elastic material (32) is made of a very soft elastic material so that the surface layer of the wafer (6) can be uniformly polished. That is, if a wafer (6) with a diameter of 5 inches and a thickness of 600 to 650 μm is polished using a single-cell elastic material, such as a single-cell sponge (rubber hardness = 30 degrees or less) as the elastic material (32), the wafer 3 for the surface layer of (6)
With polishing of ~4 μm, the variation in polishing stock (polishing error) is 0.1 or less, and polishing can be performed with higher precision than in normal cases.

Therefore, the depression (7) formed in the island-like silicon region (2) during selective polishing becomes smaller, and the planarization of the island-like silicon region (2) during the second polishing can be further improved.

Next, in the process of forming a device in the island-like silicon region (2) after forming the SO substrate in the first to third embodiments, heat treatment is frequently performed. This heat treatment is usually
As shown in Figure 6, wafers (W) are arranged at predetermined intervals on a quartz boat (41) with a total length of about 60 cm, and then the quartz boat (41) is placed in a furnace as shown in Figure 7. (
42〉.

That is, with the quartz bowl (41) placed in the furnace (42), raise the temperature of the furnace (42) to the desired temperature (e.g. 600°C) (heating rate, e.g. 10°C to 20°C/m1n). After a certain period of time (e.g. 30 minutes), the furnace (42
) and take the quartz bowl (41) out of the furnace (42>) to complete the heat treatment.The key to no treatment is to avoid giving thermal shock (thermal distortion) to the wafer (W). This is because severe heat shock may cause metastasis.

Generally, a heat treatment furnace (42) is formed by winding a heater (44) around the outer periphery of a quartz tube (43), as shown in FIG. Therefore, when the wafer (W) is heated up after being put into the furnace (42), the temperature rises from the outer periphery of the wafer (W>), creating a temperature difference from the center of the wafer (W).Similarly, when the temperature is lowered, Since the outer periphery cools down first, there is a temperature difference between the center and the outer periphery.Therefore, there is an inconvenience that a thermal shock inevitably occurs in the wafer (W).This thermal shock causes the wafer (W) to This is said to cause dislocation lines (slip lines) and lead to subsequent device leaks.
It's inconvenient. Therefore, in this example, after preparing a donut-shaped quartz plate (51) as shown in FIG. 8, when storing the wafer (W) in the quartz boat (41) as shown in FIG. The quartz plate (51) is then placed in the wafer (W) and the quartz plate (51) in turn, and then the quartz board (51) is placed in the wafer (W) and the quartz plate (51) alternately. ) (41) shown in Fig. 7 (
42> and heat-treated. In addition, in this example, the quartz plate (
In No. 51), the outer diameter was approximately the same as the outer diameter of the wafer (W), the inner diameter d was 1/3 of the outer diameter of the wafer (W), and the thickness t was about 0.5 to 2 mm.

By doing this, when the temperature rises, the outer peripheral part (W) of the wafer (W) is
Although the temperature increases from a) (see curve I in Figure 10B),
Since the quartz plate (51) has poor thermal conductivity, its outer periphery (51)
a) is warm <<, the hollow center (51b
), the temperature rises more easily (see curve ■ in Figure 10B). Therefore, when the temperature rises, this quartz plate (51) suppresses the temperature rise in the periphery of the furnace (42), and the temperature in the center of the furnace (42) continues to rise, as shown by the curve ■ in Figure 1C. As a result, the temperature distribution of the wafer (W) is flattened, and the temperature difference between the outer periphery and the center is reduced.
As shown in FIG. 11A, the wafer ('vV) cools from the outer circumference (Wa) (see curve I in FIG. 11B),
The outer periphery (51a) of the quartz plate (51) does not cool easily,
The temperature decreases more easily in the center (51b) (11th
See curve ■ in Figure B>. Therefore, when the temperature drops, the quartz plate (51)
This suppresses the temperature drop in the periphery of the furnace (42) and accelerates the temperature drop in the center of the furnace (42).As a result, the temperature distribution of the wafer (W) is The surface is flattened, and the temperature difference between the outer periphery (Wa) and the center (wb) is reduced.

In this way, when the temperature is raised and lowered during heat treatment, the temperature distribution of the wafer (W) changes from the outer periphery (Wa) to the center (Wa).
Since the wafer (W) is flattened over the wafer (wb), thermal shock to the wafer (W) is prevented, a highly reliable wafer (W>) can be obtained, and the yield of devices can be improved.

〔Effect of the invention〕

A method for manufacturing a semiconductor substrate according to the present invention includes laminating first and second insulating films having mutually different etching characteristics on the main surface of a semiconductor substrate having a step, and then bonding the semiconductor substrate and another substrate. Next, the semiconductor substrate is selectively polished until all of the plurality of island-shaped semiconductor regions partitioned by the first insulating film are exposed, and then the exposed first insulating film is removed by etching, and the second insulating film is etched. The second insulating film around the island-shaped semiconductor region is exposed, and then the island-shaped semiconductor region is polished using the exposed surface of the second insulating film as a stopper. Alternatively, after forming an insulating film on the stepped main surface of the semiconductor substrate, the semiconductor substrate is bonded to another substrate, and then the semiconductor substrate is exposed so that all of the plurality of island-shaped semiconductor regions partitioned by the insulating film are exposed. After selective polishing until the insulating film is etched, the exposed part of the insulating film around the island-shaped semiconductor region is removed by etching, and then the etched-removed surface of the insulating film is used as a stopper to remove the exposed part of the insulating film around the island-shaped semiconductor region. Since the semiconductor substrate (SOI substrate) It is possible to achieve high quality.

Further, the method for manufacturing a semiconductor substrate according to the present invention includes forming an insulating film on the main surface of the semiconductor substrate having a step, bonding the semiconductor substrate with another substrate, and then partitioning the semiconductor substrate with an insulating film. After selectively polishing until all of the plurality of island-shaped semiconductor regions are exposed, the insulating film that is exposed around the island-shaped semiconductor regions is polished halfway along with the island-shaped semiconductor regions, so that the substrate It is possible to form a uniform island-shaped semiconductor region over the entire surface, reduce the surface roughness of the island-shaped semiconductor region, and improve the quality of the semiconductor substrate (S○■ substrate). Moreover, it is possible to further simplify the manufacturing process of the semiconductor substrate.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing a method for manufacturing an SOI substrate according to a first embodiment, FIG. 2 is a process diagram showing a method for manufacturing an SOI substrate according to a second embodiment, and FIG. 3 is a process diagram showing a method for manufacturing an SOI substrate according to a third embodiment. Figure 4 is a process diagram showing the polishing method for the flattening layer, Figure 5 is a block diagram showing the polishing disk, Figure 6 is a diagram showing the quartz boat, and Figure 7 is a diagram showing the polishing method for the flattening layer. Block diagram showing the furnace, No. 8
Figures A and B are a plan view and a side sectional view showing the quartz plate, Figure 9 is an explanatory diagram showing the accommodation state of the wafer and the quartz plate, and Figure 10 is an explanatory diagram showing the temperature distribution of the wafer when the temperature is increased. 11th
The figure is an explanatory diagram showing the temperature distribution of the wafer when the temperature decreases.
FIG. 2 is a process diagram showing a method of manufacturing a S○ board according to a conventional example. (A, ), (A2) and (A3) are SOI substrates, (1)
and (6) are silicon wafers, (2) are island-shaped silicon regions (element forming areas), (3), (11) and (
21) is a 5102 film, (4) is a SiN film, (5) is a flattening layer, and (7) is a depression. Agent Hidemori Matsukuma Diagram 15O11 Sheets iv-Iren Process diagram Diagram 2 Al5ol Atsushi Kureita 3 flight example construction f! Fig. 3 Fig. 7 A Fig. 9 Fig. 10 Fig. 11 Fig. 64 4 layers for Ryosha

Claims (1)

[Claims] 1. A step of laminating first and second insulating films having mutually different etching characteristics on a main surface having a step of a semiconductor substrate, and a step of bonding the semiconductor substrate and another substrate. , selectively polishing the semiconductor substrate until a plurality of island-shaped semiconductor regions partitioned by the first insulating film are all exposed; etching away the first insulating film and removing the second insulating film; The method is characterized by comprising a step of exposing a second insulating film around the island-shaped semiconductor region, and a step of polishing the island-shaped semiconductor region using the exposed surface of the second insulating film as a stopper. Manufacturing method for semiconductor substrates. 2. A step of forming an insulating film on the stepped main surface of the semiconductor substrate, and a step of bonding the semiconductor substrate to another substrate. All of the plurality of island-shaped semiconductor regions partitioned by the insulating film on the semiconductor substrate are exposed. a step of etching away part of the insulating film around the island-shaped semiconductor region of the insulating film, and using the surface of the insulating film after etching as a stopper as a stopper for the island-shaped semiconductor 1. A method for manufacturing a semiconductor substrate, comprising the step of polishing a region. 3. A step of forming an insulating film on a main surface having a step of a semiconductor substrate; a step of bonding the semiconductor substrate with another substrate; A method for manufacturing a semiconductor substrate, comprising the steps of: selectively polishing until all of the insulating film is exposed; and polishing part of the insulating film around the island-shaped semiconductor region together with the island-shaped semiconductor region. .