JPH03188630A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To improve the film thickness precision of an island type semiconduc tor region by inserting two wafers, which are mutually stuck, between two polishing surface plates in the manner in which a polish reference surface is put in a natural state, and polishing one surface only. CONSTITUTION:A laminated wafer formed by sticking a wafer of an Si layer 5 on a wafer wherein a silicon layer 1A, an SiO2 layer 3 and a flattened layer 4 are stacked is inserted between the upper surface plate 12 and the lower surface plate 14 of a both-surface polishing machine 15 so as to be in a natural state. By a hard cloth 11 of the surface plate 12 and a soft cloth 13 of the surface plate 14, both-surface polishing is performed, and, practically, single- surface polishing is performed by the cloth 11. Thickness irregularity of the layer 1A is gradually corrected by the flatness correction effect of the above both-surface polishing. When polishing is continued until the layer 3 is exposed, an island type semiconductor region of a residual part of the layer 1A is formed with excellent film thickness precision.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor substrate in which a semiconductor region is formed on a substrate through an insulating film, so-called SOJ (silico
The present invention relates to a method for manufacturing an (on-insulator) substrate, and particularly to a method for manufacturing an SO2 substrate having a plurality of island-shaped semiconductor regions by bonding semiconductor substrates having steps.

[Summary of the invention]

The present invention is a method for manufacturing a semiconductor substrate having a plurality of island-shaped semiconductor regions separated by an insulating film, in which two wafers are bonded together, and then the two bonded wafers are placed between two polishing surface plates. By sandwiching the polishing reference surfaces in a natural state and polishing only one wafer until the plurality of island-shaped semiconductor regions partitioned by the insulating film are exposed, each film in the plurality of island-shaped semiconductor regions is polished. This is intended to reduce variations in thickness, improve the accuracy of the film thickness of the island-shaped semiconductor region, and improve the quality of the semiconductor substrate and the yield of devices formed on the substrate. .

[Conventional technology]

2. Description of the Related Art Recently, progress has been made in the development of manufacturing VLSIs using so-called SOI substrates in which a thin semiconductor silicon layer is formed on an insulating film. Among the various methods for producing Sol substrates, the bonding method is considered to have the best crystallinity and superior properties (for example, reduction of parasitic capacitance and kink phenomenon).

The bonding method involves creating a step on the main surface of one mirror-finished silicon wafer, oxidizing it, and then filling the step with a planarizing layer such as a SiL layer or a polycrystalline silicon wafer. After planarizing the silicon wafer and bonding it to another mirror-finished silicon wafer, one silicon wafer is selectively polished until it becomes a thin film, forming multiple island-shaped semiconductor regions (device formation regions).
This is a method of forming. During the selective polishing, as shown in FIG. 10, the bonded wafer (41) after bonding the two wafers is attached to the template (43) provided on the lower surface of the equalizing mechanism pressure plate (42). )
After the bonded wafer (41) is mounted inside the wafer, the main surface of the bonded wafer (41) is pressed against the polishing surface plate (44) by applying a load to the pressure plate (42) to perform polishing (single-sided polishing). There is.

[Problem to be solved by the invention]

In general, the state of the bonded wafer 41) before selective polishing is such that, as shown in FIG. (a-b = 3-4 μm). Therefore, as in the past, the wafer (41) is attached to the template (43).
) and place the polished surface of the wafer (41) on the polishing surface plate (
44), since the pressure plate (42) has an equalizing mechanism, the pressure plate (42) is also set at the reference position (axial direction, indicated by the - dotted line) according to the slope of the polished surface. ), and when a load is applied to the pressure play (42), the entire surface of the polishing surface of the silicone layer (52) is under almost the same pressure. When polishing is performed in this state, as shown in FIG. 12, during the polishing, the thickness of the silicon layer (52) (c-d) becomes uneven before polishing (a-b = 3 to 4 μm). 5102 film (51
) is exposed. When further polishing is performed to completely remove the silicon layer (52), as shown in FIG.
In the part where the 5in2 film (51) has already been exposed, the silicon layer (island-shaped semiconductor region) (53
-1) and (53-) are also slightly polished (polishing rate ratio with recon layer (52) -1710 to 1/20
), the top surface of the island-shaped semiconductor region (53,), (532) and the top surface of the 8102 film (51) are almost on the same plane at the part where the silicon layer (52) is removed as soon as the polishing is completed. However, the island-shaped semiconductor region (5:L-+) at the exposed part of the Sin2 film (51), (+3.)
The upper surface is depressed below the upper surface of the Sin□ film (51), and the thickness of each of the island-shaped semiconductor regions (53,) to (53°) in the plane of the wafer (41) is extremely large. There is a problem that large variations occur in the film thickness of the island-shaped semiconductor regions (53,) to (53n), which are important for the quality of the SOI substrate, and that there is no precision (accuracy with respect to a predetermined film thickness and accuracy with which the top surface is flat).

This is due to the fact that the back surface of the wafer (41) itself becomes the polishing reference surface, and that the polishing reference surface is fixed to the pressure plate (42). A situation arises in which no semiconductor region exists at all, which is disadvantageous in that it causes a decrease in yield in terms of device fabrication.

The present invention has been made in view of the above points, and an object thereof is to be able to reduce variations in film thickness in a plurality of island-shaped semiconductor regions, and to reduce film thickness variations in the island-shaped semiconductor regions. An object of the present invention is to provide a method for manufacturing a semiconductor substrate that can improve thickness accuracy, improve the quality of the SOI substrate, and increase the yield of devices formed on the SOI substrate. .

[Means to solve the problem]

The method for manufacturing a semiconductor substrate of the present invention is a method for manufacturing a semiconductor substrate (8) having a plurality of island-shaped semiconductor regions (7,) to (7°) separated by an insulating film (3). )
The bonded wafer (6) after bonding and (5) is sandwiched between two polishing plates (12) and (14) with the polishing reference surface in a natural state, and one wafer (1)
Polishing is performed until a plurality of island-shaped semiconductor regions (71) to (7o) partitioned by insulating films (3) are exposed.

[Effect]

According to the manufacturing method of the present invention described above, the bonded wafer (6)
is placed between two polishing surface plates (12) and (14), and one wafer (
Since only 1) is polished, the flatness correction effect (the effect of polishing the convex parts preferentially) works during polishing, and the thick part of the silicon layer (IA) is preferentially polished, and during polishing, Thickness unevenness (a) of silicon layer (IA) before polishing
~b) is gradually corrected and when the silicon layer (IA) is completely polished, each island-shaped semiconductor region (7,) ~ (7n)
The variation in film thickness is reduced, and the accuracy of the film thickness (accuracy for a predetermined film thickness and top surface flatness accuracy) is improved, which improves the quality of the semiconductor substrate (S○■ substrate) (8) and improves the quality of the device. High yield can be achieved.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to FIGS. 1 to 9.

FIG. 1 is a process diagram showing a method for manufacturing a Sol substrate according to this embodiment. The steps will be explained step by step below.

First, as shown in FIG. 1A, a plurality of O5 parts (2) with a thickness of approximately 1,000 layers are formed on the main surface of a silicon wafer (1) whose both sides are mirror-finished using photolithography technology. A predetermined pattern of steps is formed.

Next, as shown in FIG.
D (Chemical Vapor Deposition) method is used to form a Sin film (3), and then a planarizing film (4) such as a Sin2 layer or a polycrystalline silicon layer is formed to a thickness of 5 to fill these steps.
After depositing about μm, this layer (4) is polished to flatten the surface.

Next, as shown in FIG. 1C, another mirror-finished silicon wafer (5) is bonded to the flattened surface m to form a bonded wafer (6).

Next, as shown in the first diagram, one silicon wafer (1) is selectively polished from its back surface to form a plurality of island-shaped silicon regions (7,) separated from each other by an S10 film (3).

(72) to (7,,) are formed to obtain a SOR substrate (8) according to this example. As shown in Fig. 2, the polishing surface plate used for this selective polishing process has a hard cloth (1
1) with the upper surface plate (12) and the soft cloth (13) on the top surface.
) A so-called double-sided polishing machine (1
5) is used. The upper surface plate (12) is fixed to the equalizing mechanism (applied pressure plate) (16) at its upper part, and is configured to rotate, for example, clockwise via a rotating shaft (17). On the other hand, the lower surface plate (14) has a rotary shaft (18
), for example, in a counterclockwise direction. In addition, between the upper surface plate (12) and the lower surface plate (14), as shown in Fig. 3, a spur gear-like outer shape is located at an eccentric position slightly smaller than the outer diameter of the bonded wafer (6). (Tenbrae provided with a hole (20) having a large diameter)
(21) are disposed, and an internal gear (22) that meshes with the teeth of the template (21) is provided at the outer peripheral portion between the upper surface plate (12) and the lower surface plate (14). ) and the lower surface plate (14) is provided with a spur gear (23) that meshes with the teeth of the template (21). The internal gear (22) is connected to a rotating shaft (25) via a holder (24), and is configured to rotate clockwise, for example, by rotation of the rotating shaft (25).

On the other hand, the internal gear (22) is configured to rotate, for example, counterclockwise via the rotation shaft (26).

Therefore, each tensile wheel is rotated by an internal gear (22) that rotates clockwise and a spur gear (23) that rotates counterclockwise.
(21) are each forced to rotate clockwise. When polishing the bonded wafer (6) using this double-sided polisher (15), the wafer (6)
This is done by installing it into the hole (20) of the tension plate (21) placed between the upper surface plate (12) and the lower surface plate (14). still,
At this time, polishing liquid is injected. The polishing liquid is an alkaline solution (which chemically reacts with silicon but does not chemically react with 5102).
For example, an aqueous solution of ethylenediamine or potassium hydroxide) is used. In the case of polishing using this double-sided polishing machine (15), since the wafer (6) is polished from both sides, the wafer (6) is not fixed to the polishing plates (12) and (14), and the wafer (6) is polished from both sides. ) The polishing reference surface changes to the front or back surface of the wafer (6) depending on the unevenness of the front or back surface of the wafer (6). In this way, since the polishing reference surface is not held in its natural state, both sides of the wafer are polished in a free state, so the flatness correction effect (the effect of polishing the convex parts preferentially) is activated during polishing. As shown in Figure 4, the silicon layer (wafer) on the 3102 film (3) before selective polishing (
IA) thickness unevenness of 3 to 4 μm (a to b = 3 to 4 μm)
Even if this occurs, the thickness unevenness (a-b) of the silicon layer (18) before polishing is gradually corrected during the polishing process, and in FIG. 5, the thickness unevenness (c-d) becomes 1.
When the silicon layer (IA) is completely polished to expose the Si film (3), the upper surfaces of the island-shaped silicon regions (71) to (7o) are reduced to ~2 μm, as shown in FIG. 1C. and the upper surface of the SiO□ film (3) are almost on the same plane. This is due to the flatness correction effect of the polishing M from both sides, and polishing often progresses from a portion of the 7937 layer (IA).
/ Recon r = While polishing progresses slightly on the thin part of (IA), the silicon layer (1 person This is thought to be because the thinned part of ) appears to be attending to the polishing.

In selective polishing by the double-sided polisher (15), both sides of the wafer (6) are polished. However, in this example, as shown in FIGS. 1B and C, one wafer (
1), as mentioned above, the upper surface plate (12) uses a hard cloth (11) with a high polishing rate, and the lower surface plate (14) uses a soft cloth (13) with a low polishing rate. ) is used. In this way, when polishing of one wafer (1) is completed, only a small amount of polishing is required for the other wafer (5).

As shown in Fig. 6, a method of polishing only one wafer (1) with a double-sided polisher (15) is to form a polishing-resistant protective film (27) on the end surface of the other wafer (5) in advance. I'll keep it. As this protective film (27), for example, an S1 film is used, which does not chemically react with the alkaline polishing liquid supplied during selective polishing. If this film (27) is formed on the other wafer (5) in advance, the polishing cloths (11) and (13) can be applied to both the upper surface plate (12) and the lower surface plate (14).
) can be used as a hard cloth.

As mentioned above, according to this example, only one wafer (1) is polished using the double-sided polishing machine (15) during the selective polishing shown in FIG. The thicker parts of the silicon layer (IA) are polished first, and the entire silicon layer (IA) is polished to form island-shaped silicon regions (7,), (7□) to (7,,). When this happens, the top surface of each island-shaped silicon region (7,) to (7h) and the top surface of S r 02 MC3) become almost flush,
Island-shaped silicon region (71) in the wafer (5) plane
-7°) variations in film thickness are reduced. Therefore, the accuracy of making the film thickness of each island-like silicon region (7,) to (7o) a predetermined thickness in the plane of the wafer (5) and the precision of making the upper surface flat are excellent, and the SOI substrate (8,
) as well as a high yield of devices formed on the Sol substrate (8).

Island-shaped silicon regions (71) to (7o) after the above selective polishing
Due to the etching effect of the alkaline solution during selective polishing, the surface roughness of the upper surface of the substrate deteriorates and polishing damage remains. Therefore, a polishing solution containing abrasive grains is used to polish an island-shaped silicon area with a thickness of 3,500 mm (normally, after selective polishing, a second polishing M, which will be described later, is carried out for the purpose of removing damage and reducing surface roughness). In order to be carried out, in advance in Fig. 1,
It is designed to form a convex part (2) of 3,500 people)
The upper surfaces of (7,) to (7n) are polished again, but this polishing causes variations in the polishing allowance between wafers and within the wafer surface. This is thought to be caused by variations in the pressure distribution of the polishing disk against the wafer (5) and the abrasive grain distribution in the polishing liquid. That is, the island-shaped silicon regions (71) to (7o) were polished at a polishing rate of 2000 by the above-mentioned normal polishing method.
Even if an attempt is made to improve the surface roughness and damage by polishing by several people, as shown in Figure 7, the first wafer (5A) is polished by 1,400 people, and the second wafer (5B) is polished by 1,400 people.
wafers (5A) were polished by 2,600 people.
) and (5B) in terms of polishing allowance.

In addition, as shown in Figure 8, variations occur in the polishing allowance within one wafer (5), such as polishing by 1800 people or polishing at 220 OA within one wafer (5). . Therefore, during selective polishing, the upper surface of the island-like silicon region (7,) to (7°) is covered with a 5in2 film (3).
Even if it is made flush with the top surface, some of the island-like silicon regions (7I) to (7n) may be removed due to variations in the polishing amount during the second polishing aimed at reducing surface roughness and damage. However, the film thickness exceeded the quality standards, and S
○ This causes the inconvenience of significantly deteriorating the quality of the engineered board (8).

Therefore, in this example, as shown in FIG. 9A, thermal oxidation is applied to the surface where the island-like silicon regions (7,) to (7o) are exposed to form a thermal oxide film (31) of 8102 on the entire surface. Form. At this time, each island-like silicon region (71) to (7o) is thermally oxidized to a depth of about 1000 polishing degree.

Next, as shown in No. 9-8, an island-like licon region (71
) - (7o) The thermal oxide film (31) on the entire surface is etched away using an HF solution until the thermal oxide film (31) is completely removed. At this time, the island-like Nrifun regions (7,) to (7
o) Etch and remove to the extent that the 5in2 film (3) separating the two is not lost. That is, the island-like region (7,
Etching is stopped at the stage when each silicon surface of ) to (7, ) is exposed. The thermal oxide film (31) is a SiO□ film (
Since the thickness is significantly different from that of 3), it is easier to control the etching stop.

In this way, after thermal oxidation is once applied to the upper surfaces of the island-shaped silicon regions (71) to (7o), a thermal oxide film (31) is formed on the island-like silicon regions (71) to (7o). Since it is removed by etching, polishing damage caused during selective oxidation can be removed together with the thermal oxide film (31), and the surface roughness can be improved. In addition, in the 118th step, the height difference (thickness of the convex portion (2)) of the wafer (1) was taken into account in advance the thickness (1000 layers) required as an element formation area and the depth of thermal oxidation (1000 layers). If it is treated as a person, in the final process (Fig. 9B), the island-shaped silicon region (7,) ~
The thickness of (7o) can be made uniform to the desired thickness (1000 layers) over the entire surface of the wafer (5), and the surface roughness and polishing damage of the island-like silicon regions (71) to (7n) can be reduced. be able to.

〔Effect of the invention〕

The method for manufacturing a semiconductor substrate according to the present invention involves bonding two wafers together, and then sandwiching the bonded two wafers between two polishing plates with their polishing reference surfaces in a natural state; Since only the wafer is polished until the plurality of island-shaped semiconductor regions partitioned by insulating films are exposed, it is possible to reduce variations in film thickness in the plurality of island-shaped semiconductor regions, and the island-shaped semiconductor It is possible to improve the accuracy of the film thickness of the region (accuracy for a predetermined film thickness and flatness accuracy), and also to improve the quality of the semiconductor substrate and the yield of devices formed on the substrate.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing a method for manufacturing a semiconductor substrate according to this embodiment, FIG. 2 is a configuration diagram showing a polishing surface plate according to this embodiment, and FIG.
The figure is a plan view showing the space between the upper surface plate and the lower surface plate, FIG. 4 is a cross-sectional view showing the state of the wafer before selective polishing, FIG. 5 is a cross-sectional view showing the state of the wafer during selective polishing, and FIG. An explanatory diagram showing an example of a method of polishing only one wafer, Fig. 7 is an explanatory diagram showing variations between wafers in the second polishing, and Fig. 8 is an explanatory diagram showing variations within the wafer 71 plane in the second polishing. An explanatory diagram showing variation, Fig. 9 is a process diagram showing a method for reducing surface roughness and laboratory damage, Fig. 10 is a configuration diagram showing a conventional polishing surface plate, and Fig. 11 is a conventional selective polishing. FIG. 12 is a cross-sectional view showing the state of the wafer before selective polishing; FIG.
FIG. 3 is a sectional view showing the state of a wafer after conventional selective polishing. (1), (5) are silicon wafers, (2) are convex parts, (3) are Sin, film, (4) are flattening layers, (6
) is a bonded wafer, (71) to (7o) are island-like silicon regions, (8) is an SOI substrate, (11) is a hard cloth, (12) is an upper surface plate, (13) is a soft cloth, (14) ) is the lower surface plate, (15) is the double-sided polisher, (16) is the pressure plate, (17), (18),
(25) and (26) are rotating shafts, (21) is a template, (22) is an internal gear, and (23) is a spur gear. Deputy Hide Hitomatsu Kuma 1st polishing machine 21 1st part Figure 8 Section procedural amendment

Claims (1)

[Claims] In a method for manufacturing a semiconductor substrate having a plurality of island-shaped semiconductor regions separated by an insulating film, after bonding two wafers, the bonded two
A wafer is sandwiched between two polishing plates with the polishing reference surface in a natural state, and only one wafer is polished until the plurality of island-shaped semiconductor regions partitioned by the insulating film are exposed. Characteristic semiconductor substrate manufacturing method.