JPH03180928A - Floating point multiplier - Google Patents

Abstract

PURPOSE:To speed up multiplication by simultaneously executing addition to be executed after the partial product operation of mantissa part operation and rounding addition, previously executing the operation of a correction value which may be required at the time of operating an exponential part and the detection of an overflow and an underflow, and when the correction is required, selecting only the necessary part. CONSTITUTION:An exponential arithmetic circuit 110 calculates an exponential part, previously calculates the correction value of the exponential since the correction of a normalizing circuit or a rounding circuit may execute the correction of + or -1, and checks the overflow and underflow of uncorrected data and corrected data. Namely, an adder/subtractor 2201 calculates normal exponentials. A + or -1 correcting circuit 2203 calculates a correction value which may be generated at the time of normalizing or rounding operation and an overflow/underflow deciding circuit 2202 executes checking operation when the correction is zero, and if an overflow/underflow is generated, interrupts the floating point computing processing at the time of deciding the overflow/underflow. Thus, the processing can be executed at the high speed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to floating point multiplication devices.

[Conventional technology]

FIG. 2 shows a typical example of a conventional floating point multiplication circuit, in which two pieces of data X each having a length of 64 bits are processed.

When Y is input, the floating point multiplication is executed and 64-bit data W is output. Input data X, Y is ○~5
Up to 1 bit is arranged based on the mantissa part, 52 to 62 bits are arranged based on the exponent part, and 63 bits are arranged based on the code information. This standard is a “Floating Point Subcommittee Working Document”;
Ai Eeeee (11F1oatjngpoint
Subcommittee Illorking D
ocumont”.

IEEE) p, 754.1987.

The operation of a floating-point multiplication circuit consists of three operations on the sign part, exponent part, and mantissa part. The sign of output data W is positive if the signs of input data X and Y are the same, and negative if they are different. The sign calculation circuit 206 calculates the exclusive OR of the sign bits 210X and 210Y of the input data and outputs it to the signal line 215 as the sign bit I~ of the data W.

The one-exponent calculation circuit 205 has a sign 210 of the input data X and Y.
X, , 210Y, index 2], 1. X, 211Y
are input, addition is performed when the signs are the same, subtraction is performed when the signs are different, and the result is output to the signal line 216. Index correction 1 Kamoji 204 is
When the mantissa normalization circuit 202 or the rounding circuit 203 requests a maximum correction of 1 or -1, when the sign 215 of the output W is positive, it is corrected by 1, and when it is negative, it is corrected by -1, and the result is is output to the signal line 222 as the exponent part of the output data W.

The calculation of the mantissa part is performed by the partial product calculation circuit 201. Addition unit (AU) 230, normalization circuit 202, and round-1
The mantissa part of the output data W is calculated from the product of the mantissa parts of the input data X and Y.

The mantissa part of the input data X is PX=1. +1'* Book ・ ・ ・ [2
Ko... ・(1). Mantissa part of input data Y 1) The same goes for Y, both are 53 pits I
It becomes the binary number of ~. However, [2] indicates that it is a binary number. Therefore, multiplication is performed between the two numbers PX, PY of the form of equation (1), and the result is 11, * Shin Kushi... [2] 10, * Shin Kushi ・ ・ ・ [2]
...... (2)01, *Ning*...[2] It takes the form of one of the following. However, this book here is 10
It is a sequence of four "O" and '1'.The multiplication up to this point is performed by first inputting data X, Y (7) to the partial product calculation circuit 201.
When the mantissa parts 212X and 212Y are input, a product calculation is performed on the numbers in the form of equation (1) in which 1 is added to the most significant bit (MSB) of the input. The partial product calculation circuit 201 performs CS A (CarrySave Add
er), and its output is a sum set 232 (102 bits) and a carry set 231
(106 bits). AU (Ar
ithmetj, c 1Jnit) 23 adds these two outputs and outputs a 106-bit multiplication result in the form of equation (2) to the signal line 217.

When the result of the above multiplication is one of the first two forms of 7- in equation (2), it is necessary to convert this into the form of equation (1) and use it as the mantissa part of output data W. Normalization circuit 20
In this case, 2 shifts the multiplication output 217 to the left by 1 bit, corrects the calculation result of the exponent part, and at the same time converts the least significant bit (LSB) after the left shift for the next rounding operation to the LSB before the left shift (this (disappears due to shift) and the logical sum of its higher order bits.

The output 218 of the normalization circuit 202 obtained in this way has a length of 105 bits, but the rounding circuit 203 converts it to the formula (
The data is 53 bits long in the form 1). According to the above-mentioned IEEE standard, four modes are provided as this rounding method: RZ, RM, RM, RP, and RN. The RZ mode rounds to approach O, and performs rounding down. The RM mode is for making the value closer to -■ and executes a rounding down process. In the RP mode, rounding up is performed in a way that brings the value closer to +■. The last RN mode performs a rounding process. These processes are performed using the following equation, where the 52nd bit after the decimal point is removed, the 53rd bit is G, the 54th bit is R1, the OR of each bit from the 55th bit is S, and the sign of the operation result is S. The value obtained according to the above is added to the 52nd bit below the decimal point, and the portion after the 53rd bit below the decimal point is removed.

RZ mode: O RM mode: S, (G+R+5) RP mode: S, (G+R+5) RN mode 2G・(R+S)+L -G・ (R+S)
......(3) Of the 53 bits of data rounded in this way, the MSB
The "1" in the output data W is automatically removed and set in the mantissa part of the output data W.

The special data processing circuit 207 has 1, +, and N A N (not a
This is a control circuit for detecting an exceptional number such as ber) and terminating the process, but since it is not related to the present invention, its explanation will be omitted.

Next, a conventional example of the partial product calculation circuit 201 related to the present invention will be described in detail. 9- Similarly to multiplication by hand calculation, multiplying the multiplicand by each digit of the multiplier produces one partial product at a time, and the multiplication is completed by adjusting the digits of the partial products obtained in this way and adding them. If you carry out the same method as this manual calculation, you will add the first partial product and the next partial product,
The process of adding the result and the next partial product is repeated. However, in this case, carry propagation occurs during each addition, so parallel processing cannot be performed and performance does not improve. To improve this, the C8A method was devised. This C8A
The configuration of circuit 4 (b) is shown in FIG.
A partial product calculation circuit 201 is constructed by connecting the iIJ) as shown in FIG. The unit circuit 4 (i, j) converts the Jl-L bits X(j
), Y(i) (both the J+1st bit counting from the LSB) are ANDed using an AND gate AND (jl i), and its output and the other two inputs c (i-11jL
A full adder FA(i,j) calculates a full addition for three inputs with s(i-11j+1). The result is Sam s(
i.

10-S), and is output as carry (-i, j). Here, the truth table of the outputs s and c of the full adder FA for three inputs is as shown in Table 1.

The operation of the circuit configuration shown in Table 1-Table 3 is as follows. Figure 3 (a
), the unit circuit at No. 1- to which Y(i-1) is input...4 (i-1, j+1).

4 (i-t,']) + 4 (i-1t j-
, t) is... is the (i-th) when PY is the multiplier
1) Each bit of the partial product between bit Y (i, -1) and multiplicand 1) j, j → 1)
.

'] (,; r, j) + 4 (j,, +j-
i) ... is the 'th bit Y(:i,) of PY and P
Each bit of the partial product with X is calculated. On the other hand, since the bits of the same digit of PX are input to each unit circuit in the vertical direction, the output bit of each unit circuit in the first row of J- is one digit lower than that in the second row. Equivalent to. Therefore, as shown in the figure, the sum S of each unit circuit is inputted to the unit circuit 1 from the right in the bottom row, and the carry C is input to the unit circuit immediately below, and the full adder FA performs an AND operation. By performing addition in each unit circuit together with the output of the gate, the necessary sum of partial products can be obtained. Moreover, according to this method, propagation of carries within each row in FIG. 3(a) is eliminated, and carries are added at the next addition, so addition of partial products can be performed in parallel for each bit. The number of bits in PY is 53, but for the LSB of PY and its one bit Y (o), y (1), the unit circuit shown in Fig. 3(b) is not necessary and the
Only 1- is sufficient. Then, the outputs of each AND gate of these two stages need only be input to the full adder in the row of the unit circuit for Y(2) in the third stage, so in the end, the addition of the above partial products can be performed using a 51-stage full adder. It can be executed with a delay time of , and high-speed calculation is possible.

However, each unit circuit in the bottom row and each unit circuit in the rightmost column in FIG. A carry assembly 231 is formed. The result of adding these at A U 230 is the multiplication result. The entire situation is shown in FIG. 4(a). (In this figure, however, each input data is shown as 8 bits for simplicity.) Another conventional example of a technique for increasing the speed of partial product calculation will be described next. The method shown in Figure 3 is to sequentially add each partial product using the C8A method as shown in Figure 4 (,). are divided into even numbers and executed in parallel using the C8A method, and the respective sum aggregates AI, Bl and carry aggregates A2 . Find B2.

3 Next, each thumb aggregate A1. ．． B1 and each carry aggregate A2. After calculating the sum of B2, these sums are added in AU.For details, refer to TSSCC84 (Inter
natjonal 5olid 5tate Cj,r
Cuit Conference), pages 92-93.

Another speed-up technique is called the Wall, ac+q method. This method calculates partial products while forming a tree structure for each digit, but it is disadvantageous when the bit length becomes large due to the irregular structure.

However, it is effective for the part where the results of each partial product are summarized using the method shown in Figure 3(b), that is, for the part where four aggregates are made into two aggregates, and both the C8A and Wal,]ace formulas are effective. There are some that are used in combination. Regarding the Wallace method, IEEE Trans, Electr
on.

Computers, vol, EC-13, PP14
-17. li'eb, ]96i1.

Another modest method for speeding up partial product operations is Booth's algorithm. The feature of this algorithm is that the number of partial products is halved, thereby achieving speedup14. This algorithm is described by Quart, J.
.

Mech, Appl, Math, vol. 4.
Part 2.1951, and FIG. 5 shows an example of a partial product calculation circuit of this method. Figure 5 (a
), 1. is added to the mantissa part of input data Y. The data PY marked with is input to the Booth decoder 530 and converted into a selection signal B (i) to each unit circuit. The number of signals B(i) is half the number of bits of data PY,
Each signal B (i) is a 3-bit selection signal via three signal lines. Unit circuit 5 (i.

j) has a configuration as shown in FIG. 5(b), and data PX (7) 2'') (7) bits X (j),
5 from (j-1) by selector SEL (il j)
One of the data is selected according to the value of the selection signal B (i). Since this becomes the value of the partial product, C8A type addition is performed using the three-input full adder FA (11j), as in the case of FIG.

According to this example, the number of stages of partial products is 27, and the addition is 25.
It can be executed using the delay time of the full adder in the stage.

5- [Problem R to be solved by the invention] In all of the above-mentioned conventional techniques, two additions are performed serially: the addition of the sum set and the carry set, and the rounding addition during the multiplication of the mantissa part. Because of this, the processing speed was increased unnecessarily. Furthermore, when a correction is required in the calculation of the exponent part, a correction value is calculated and its overflow or underflow is detected, which also poses an obstacle to speeding up the calculation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a floating-point multiplication device that can perform floating-point multiplication at higher speed.

[Means to solve the problem]

In order to achieve the above object, the present invention has a configuration in which the addition after partial product operation in the mantissa operation and the rounding addition are executed at the same time, and in the exponent operation, the Calculation of a certain correction value and detection of overflow and underflow are performed in advance, and when correction becomes necessary, these are simply selected, and
In the partial product operation, a full adder with five or more inputs is used to calculate the sum of two or more partial products at the same time.

[For production]

In the mantissa calculation, if the correction value necessary for rounding is generated from the sum set and carry set obtained by adding the partial products using the C8A method, this correction value can be done easily and in a short time. If the sum and the two aggregates are added at the same time, there is no need to provide additional addition time for rounding.

In addition, if you perform the calculation of the exponent part, the calculation of its correction value, and the detection of overflow or underflow in advance, you only need to select it when the result of the mantissa part is obtained. Underflow detection time can be saved. Furthermore, if a plurality of partial products are added in parallel using a full adder having five or more inputs, the processing time can be shortened and the processing speed can be increased.

〔Example〕

The present invention will be explained below using examples. The floating point multiplication circuit 100 of the present invention differs from the conventional structure shown in FIG. 2 in the configuration of the exponent operation section and the mantissa operation section, and these different parts will be explained below.

The exponent calculation circuit 110 calculates the exponent part 21 of input data X, Y.
11 bits each of 1X, 211Y and sign operation circuit 206
Calculation of the exponent is performed from the output 215 of Check for overflow and underflow of the data after correction. FIG. 6 shows the configuration of the exponent calculation circuit 110, in which an adder/subtractor 2201 performs conventional exponent calculations. The ±1 correction circuit 2203 calculates in advance correction values that may occur during normalization or rounding. The overflow/underflow determination circuit 2202 checks when the correction is O, and if overflow/underflow has occurred, it may interrupt the floating point arithmetic processing at the time of the determination. This is because if overflow/underflow has already occurred before correction, overflow/underflow will still occur after correction.

The overflow/underflow determination circuit 2204 is ±
The output of the 1 correction circuit 2203 is determined in advance.

When interrupting the process when an overflow/underflow is detected by this determination, the process is not interrupted immediately after the detection, but is interrupted when it becomes clear that correction is necessary.

In the above process, the calculation of the correction value and the overflow/underflow judgment process are already completed before it is determined whether or not to correct based on the calculation result of the mantissa, so all that is left to do is to make the selection, reducing the overall processing time. can.

Returning to FIG. 1, the calculation of the mantissa part will be explained. Mantissa part 2 of input data X, Y] From 2X, 2+, 2Y, formula (
Data PX and PY explained in 1) (53 bits each)
is generated, the sum of the partial products is calculated using the C8A method, and the sum set 232 and carry set 231 are transferred to the partial product calculation circuit 201.
The calculation is the same as before. In the embodiment of the present invention, after this, each aggregate 232.231 is added by AU to 1
Rather than obtaining a 06-bit result, each aggregate 232,
A correction value generation circuit 1]6 generates a correction value from the lower bits of 231 and performs addition of the upper bits of each set 232.23 and rounding addition at the same time. Finally, normalization is performed to complete the process.

FIG. 7 is an explanatory diagram of supplementary JIE generation, in which two aggregates 231
．． 232 is an input. Now, if we call the bits I and positions of these data as ■, S13 to Oth bit [~, 1st bit...], then the set 231. , 232, the decimal point is placed between the 104th pitch I- and the 103rd pitch 1~.

And these addition results are the 105th pits 1~ (MSB)
N 1 ++ may occur in some cases. In the conventional method, this addition is performed, and when 111" stands in M and S 13, 1
- Normalization with bit shifting is first performed, and then rounding processing is performed, but in the embodiment of the present invention, rounding processing is performed before addition and normalization. Therefore, when the MSB of the addition result is II Q 11, it is called the A data format, and when it is Pa 1", it is called the B data format. It is necessary to perform rounding processing for both of these cases in advance. Therefore, the formula In the case of the A data format, the information for the rounding process explained in "3" is Ll, Gl for the 52nd to 50th bits.
, R1, the OR of the 49th bit to ○ bit is Sl, and in the case of B data type = 19 (because it has not been shifted yet), the 53rd to 51st bits are L2. G2. R2, OR of 50th-0th bit is S2
'tl-There is. In the rounding process, in the case of the A data type, two corrections are performed: rounding of the 52nd pitch I-to, and correction of the carry signal from the 51st to O bits originally obtained by multiplication. The correction value is O5+1, +2
Take. 0 is when there is no carry signal from below and there is no correction due to rounding, +1 is when there is a carry signal from below or there is correction due to rounding, +2 is when there is a carry from below and there is also correction due to rounding. It is. On the other hand, in the case of the B data format, the same processing as in the case of the A data format may be performed except that each bit is moved up by one.

The correction value generation circuit 116 shown in the upper figure has a carry aggregate 23.
2 and the 53rd of each lower half of the sum aggregate 231
.about.0 bit is taken in, and processing 1161 in FIG. 8 is first executed to generate information for rounding.

Here, flags a, b, and C are two aggregates 23],
, 50th to ○ bits, 51st to 0th bits of the addition result of 232
This indicates whether or not the bits 1 to 52 are all ○, and are used to obtain bits Sl, S2 for rounding processing. This is because Sl and S2 are the logical sum of the addition results, and their logical opposite is equivalent to the addition result of all O's. And this detection of all O
As shown in Japanese Patent No. 3-208938, this can be done with a simple circuit and the processing time is short.

Continuation<b-f is a flag indicating the carry output from 51st to 0.52nd to ○ and 50th to 0th I of the addition result,
gQ is (f&, m are code signals of each bit position shown in the figure, and these can also be easily obtained.

Once the above 13 pieces of data are obtained, a correction generation process 1162 corresponding to the rounding mode is executed. This content is the 9th
The correction values corresponding to each mode shown in the figure and explained using equation (3) are obtained from the data in FIG. 8, and these correction values 233 are input to the rounding g1.15.

FIG. 10 shows the configuration of the rounding circuit 115, in which the upper half (105th to 52nd bits) of the sum set 232 and carry set 231 of the output of the partial product calculation circuit 201 and the above correction value 233 are input. , A data type, and B data type 3-input AU circuits 2101 and 2102. As a result, a value obtained by rounding the mantissa multiplication result for each data type is output as each AU circuit output 234.235. Furthermore, the 105th bit data 273 of the 3-input AU circuit 2101 is output as the select signal 235 of the normalization circuit 114. The normalization circuit 114 is
It is a selector, and by the select signal 1711,
Switch target data.

If the select signal 273 is O, then if the data type is 1, then the B data format may be output. In this way, according to the present embodiment, since the calculation of the correction values in FIGS. 8 and 9 is a simple logical process and requires only a very short time, it is possible to calculate the correction values in FIGS. Addition for rounding can be performed simultaneously by the rounding circuit 115.

Next, several embodiments will be described in which full adders with five or more inputs are used to speed up partial product operations. Below, 7
An input full adder is used, and a specific example of its configuration is shown in FIG. This is constructed using four 3-input full adders, and adds seven inputs 1001 to 1007 to produce three outputs: sum S, first carry c1
．． Obtain a second carry C2. This input/output relationship can be shown in the same way as the truth table for three inputs (Table 1) shown above, but since there are 2'=128 combinations of inputs, the table is long, so it will be omitted. In short, there are 7 inputs (all are “O” or “
When the number of "1"s in "1") is defined as n, the binary representation of this is (c2.cl, s).

If there are 7 inputs in this way, the output is 0 to 7 in decimal, so 3 bits are required in binary, and 2 carries c
2. cl is required as output. In the circuit configuration shown in FIG. 11, the delay time of the circuit corresponds to the delay time of three stages of three-input full adders, and the area corresponds to four stages. In addition, 7
The input full adder may not be constructed as shown in FIG. 11, but may be directly constructed into an optimal circuit using pool algebra.

Figure 12 shows a C8A using this 7-input full adder (FA).
This figure shows an example of a partial product calculation circuit based on the partial product calculation circuit of the n+2. n+1. This is an extraction of the part to which the partial products [i] to [i + 7] of the n-th digit (same as the pit position) are added. Taking the 7-input full adder at the bottom left of the figure as an example, inputs 1005 to 1007 have a sum output S immediately above, a carry output c1 to the right of it, and a carry output c1. Further, the carry output C2 on the right thereof is input, and these are the sum and carry obtained as a result of adding the partial products [i] to [i + 3].

On the other hand, inputs 1001 to 1004 contain partial products [i+4] to [
i+7] (circled in the diagram; this is the value obtained by ANDing the corresponding bits of the multiplier and multiplicand) is input as is.

This kind of connection relationship is the same for any full adder (
(except for the periphery) is regular. In addition, here, among the 7 input data, the upper stage calculation output is input 1005 to 1005.
Input the partial product you just found into 1007 1001 to 1004
However, logically, the 7 inputs are symmetrical, so any input can go into any input. However, in general, since the upper stage calculation output becomes a critical path, it is preferable to use a connection method in which three full adders with the smallest delay time are used for this calculation output.

24- Next, the operation of this embodiment will be explained. FIG. 13 shows a calculation method for the n-th digit when performing a 53-bit×53-bit partial product operation, and only the n-th digit is extracted from the connection relationship shown in FIG. 12. First, it is assumed that 27 partial products are generated from 53-bit data through the Booth algorithm described in FIG.

In this figure, the numbers written in circles indicate the n-th digit partial products. When these 27 partial products are calculated using a 7-input full adder, the 7-input full adder in the first stage calculates the sum of partial products 1 to 7. The second stage adder adds the sum of partial products 8 to 11 and the output of the first stage, and then adds 4 partial products at each stage, making a total of 6 stages of 7-input full addition. The value of the n-th digit (n can be anywhere) is calculated by the device. Since there are three calculation results for each digit in the sixth stage,
The well-known three-input 11allace method produces two outputs. In this way, the correction generation circuit 11 shown in Fig.
6 and two input data 232 to the rounding circuit 115.
231. Note that in Figure 12, the part for calculating partial products is simply indicated by a circle, but when using Booth's algorithm, the circuit configuration for partial product generation as shown in Figure 5 can be changed to a 7-input full adder. It is also necessary to do so. The details are shown in FIGS. 14 and 15, and FIG. 14 shows the full adder 90 in FIG. 13 whose seven inputs are all partial products],
, 902.

Data XP in which the mantissa part of input data X is in the form of formula (1)
Each selector SEL generates five values from two of each of the eight consecutive bits X(j-1) to X(j+6) (this is the same as the selector in Figure 5), and Booth's The inputs 1001 to 1007 of the 7-input full adder 1000 are selected by the decoder outputs B (i) to B (j+6), respectively. Also, Fig. 15 shows the case where FA calculations are performed after the second row in Fig. 13, and the circuit (selector) that takes the partial product of the input part of carry C1, C2 ° sum S is removed in the configuration shown in Fig. 14. The structure is as follows.

According to this embodiment, in order to perform a partial product operation on 27 pieces of data, a 6-stage 7-input adder and a 3-input l1llall are used.
Partial product operations can be performed using the delay time of the ace circuit.

If the 7-input full adder is the circuit shown in Figure 11, then 3
The delay time of the input all Calorie calculator is converted into 19 steps,
2 when combining the conventional booth method and C8A method
Even faster than the 7th gear.

FIG. 16 shows another embodiment of a partial product calculation circuit using a 7-input full adder, and shows only the part for partial product calculation of n digits 1. The 53-bit input is converted into 27 partial products (indicated by symbols 1 to 27 with circles) by the Booth decoder and the circuit shown in Figures 14 and 15, resulting in two series of 7 inputs. They are added in parallel by a full adder.

The 7-input full adders 901° and 902 add the first to partial products.
Add the 7th and 8th to 14th, respectively. below,
The 7-input full adder 903 adds the 15th to 18th partial products, two carries from other digits, and the sum S of the full adder 901, and the 7-input full adder 904 adds the 19th to 22nd partial products.
Two carries from number 11 and other digits and full adder 902
The configuration is such that the sum S is added to the sum S.

Here, carry cl and a2 from other digits are each 1
This is the carry output from the next or second digit below.

And finally bl a l, 1. A carry aggregate 231 and a sum aggregate 232 are generated by the ace circuit (6-input full adder) 7 .

FIG. 17 is an explanatory diagram of the operation of the above embodiment, in which the sum is divided into two systems and calculated in parallel. That is, the first time, partial products 1 to 7 and 8 to 14 are calculated simultaneously, and then partial products 15 to 18 and 1 are calculated simultaneously.
Add 4 each of 9 to 22 at the same time, then add partial products 23 to 22 at the same time.
24 and 25 to 27 are added at the same time, so at this stage there are not 4 each, but enter 0 in the remaining places), and finally Wal,
iac, e circuit, aggregate 231. , 232 as the rounding circuit 115 and correction cropping circuit in Figure 1]
Output to Coro. The delay time for the above calculation is equivalent to three stages of 7-input full adders and j stages of 6-input Wallace circuits.If each of these adders is configured as shown in Fig. 11, it is equivalent to 12 stages in terms of a 3-input full adder. The delay time will be 1 minute, and even faster speeds will be possible.

In addition, in this example, the number of inputs to the 7-input full adder that performs the third operation is insufficient, and O is input there, but the 7-input addition by the C8A method is performed until the second operation. Then, the partial products 23 to 27 may be added using the Wall and aee methods. In this case, 11 inputs Wal, 1ace
28 circuits are required, and the total delay time is equivalent to two stages of 7-input full adders and one stage of 11-input LNallace circuit. Looking at this in terms of the delay time of a 3-input full adder, there are 11 stages.

In this way, if exactly four partial products do not remain, those can be calculated using the Wal and 1ace circuits.

Next, an example in which the degree of parallelism is further increased will be described.

Fig. 18 is an operation explanatory diagram of a method of adding partial products in four parallel ways using a 7-input full adder.
~]4.15~21. and 22 to 27 (enter O for remainder) at the same time. The result of this operation is for each digit]
Since there are 2 outputs (4 parallel outputs each with 3 outputs),
The well-known 12-person Wallace method has two outputs. Rounding circuit 1 summarizes this output by each digit.
15 mag/\ output.

A circuit configuration for realizing the method shown in FIG. 18 is shown in FIG. 19(a). This embodiment shows the entire partial product calculation circuit 201, as shown in FIGS. 3(b) and 3(c) below, and is a schematic diagram of the arrangement of each circuit when integrated into an LSI.

Both input data X and Y are 53 bits, and input data Y
is converted into 27 outputs by the Booth decoder.

In the figure, U7 is a unit circuit for calculating the partial products and sums shown in FIG. 14, and the four unit circuits arranged in the vertical direction simultaneously calculate the sum of the partial products for the number of steps shown in FIG. 18. And the result is 12 input Wal, ], ace circuit W1 circuit main 1
I can't stand it. Here, from each unit circuit U7 to Walla
The length of the arrow up to the ce circuit W12 qualitatively represents the actual wiring length. Therefore, if necessary, the driving capacity of the output driver of each stage unit circuit U7 may be changed in accordance with the wiring length.

According to this embodiment, one stage of 7-input full adder and 12-input W
Since it has the delay time of the allace circuit, the delay time of a 3-input full adder becomes 8 stages, which increases the speed of the layer.

Figure 19(b) shows the 12-input Wall of Figure 19(a).
This shows an embodiment in which the ace circuit W12 is divided into two 6-input Wa1.1 ace circuit w6 and a 4-input Va1.1 ace circuit W4. Upper two unit times M
The output of U7 is the upper 6 input Wa1. ], ace circuit w6
The outputs of the two lower unit circuits U7 are added together in the lower 6-input Wallace circuit W6, and each of the 6-person 1Ila11ace circuit W"" outputs are added to the 4-input W
a11. It is summarized by the ace circuit w4. According to this embodiment, as shown by the arrow in the figure, the upper 6 inputs 11
Only the output driver of the allace circuit needs to be a device with high driving capability, which has the effect of reducing the area of the driver and further reducing the peak current.

Figure 19(c) shows the circuit design in the configuration of Figure 19(b) by changing the positions of the two 6-input Wallace circuits w6 and aligning the output loads of the unit circuits U7 that send input thereto. It's easy to understand.

Various embodiments have been described above. Although we have not mentioned speeding up by pipelining, pipelining is possible in any of the embodiments, and speeding up of -layers can be achieved. Furthermore, although the data length to be calculated is 64 bits, it goes without saying that the present invention can be applied even if this length changes. Furthermore, we showed an example of using a 7-input full adder to speed up addition in a partial product calculation circuit, but this uses a 3-bit output (sum and 2 carries) =
31-, the maximum number of inputs is 7, so in the intermediate stage, 4 partial products are combined with the previous results (2 carries and sum) and -
This is because it can perform addition at once, and is more efficient than a 4- to 6-input full adder with the same 3-bit output. If a full adder has an n-bit output (sum n-1 carries), the number of inputs can be up to 2n-1 bits, and it is easy to extend the present invention to the use of such a full adder. .

〔Effect of the invention〕

According to the present invention, it is possible to simultaneously perform rounding processing and part of the arithmetic processing for calculating the product of the mantissa parts, to detect in advance the calculation of the exponent part and overflow/underflow of the multiplication results, and to detect inputs of 5 or more. By using a full adder, multiple partial product additions can be executed in parallel, which has the effect of allowing floating point multiplication processing to be performed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 5 is a diagram showing the configuration and operation of a conventional floating-point multiplication circuit, and FIG. 6 is a diagram showing an example of the configuration of the exponent calculation circuit in FIG. 1.
7 to 9 are diagrams illustrating the operation of the correction value generation circuit 2 in Figure 1, Figure 10 is a diagram showing an example of the configuration of the rounding circuit in Figure 1, and Figure 11 is the configuration of a 7-input full adder. 12 to 19 are diagrams illustrating an example in which a 7-input full adder is used to increase the speed of the partial product calculation circuit shown in FIG. 1, and its operation. 100... Floating point multiplication circuit, 110... Exponential calculation circuit, 113... Selector, 114... Normalization circuit, 1
15... Rounding circuit, 116... Correction value generation circuit,
201...Partial product calculation circuit.

Claims (1)

[Claims] A sign operation unit that takes one or two floating point numbers as input data and calculates the sign of output data from the signs of the two input data, and a product of the mantissa parts of the two input data and the result. a mantissa operation unit that performs normalization and rounding processing to calculate the mantissa part of the output data, and a mantissa calculation unit that performs addition and subtraction processing of the exponent parts of two input data and correction processing that corresponds to the result of the normalization and rounding processing of the processing result. In a floating-point multiplication device, the exponent calculation unit is configured to perform corrections that may be necessary depending on the results of the normalization and rounding processing. a first means for calculating a value in advance from the result of the addition/subtraction processing; a second means for detecting in advance the presence or absence of overflow or underflow of the output of the means and the result of the addition/subtraction processing; and the mantissa calculation section. When the normalization and rounding processing results are output, a necessary value is selected from the above addition/subtraction processing results or a pre-calculated correction value according to the result and is used as the exponent part of the output data, and the above-mentioned pre-detected 1. A floating point multiplication device comprising: third means for extracting a determination result as to the presence or absence of overflow or underflow. 2. When an overflow or an underflow of the result of addition/subtraction processing of the exponent part is detected by the second means, the multiplication processing is interrupted at the time of detection, and the correction calculated by the first means is Floating point multiplication according to claim 1, characterized in that the multiplication process is interrupted when an overflow or underflow of a value is detected by the second means and the correction value is selected by the third means. Device. 3. Partial product calculation means for calculating the product of the mantissa calculation unit and the entire input data of the other for each bit or multiple bits of one input data as a partial product, and each partial product calculated by the means; Addition is performed by calculating the sum of each bit of the data to be added as the sum bit and carry bit at that bit position, and when adding the next data, the sum bit and carry bit calculated above are combined with the respective corresponding bits of the next data. A means for calculating partial sums by repeating the process of addition, and a set of sum bits and a set of carry bits obtained by adding all the above partial products by means, and a means for calculating a partial sum by repeating the process of addition, and a set of sum bits and a set of carry bits obtained by adding all the above partial products. a correction value generating means for generating correction data; and a means for generating a mantissa multiplication result obtained by adding the correction value generated by the means to the set of sum bits and the set of carry bits and performing rounding processing. 2. The floating point multiplication device according to claim 1, further comprising: rounding means; and normalization means for normalizing the output of said means to generate a mantissa part of output data. 4. The partial sum calculation means outputs one sum bit and n-1 carry bits, and has 2^n-1 input bits, where n is an integer of 3 or more. The inputs of the full adder are bits of the same digit of 2^n-1 partial products, or 2^n
- n-1 bits of the same digit of the above partial products, the sum bit output corresponding to the corresponding digit of the other full adders, and the carry bit corresponding to the corresponding bit output from the other n-1 full adders. 4. A floating point multiplication device as claimed in claim 3. 5. When m is an integer of 2 or more, divide the portion to be added into m groups, calculate a partial sum by the partial sum calculating means provided for each divided group, and further calculate the calculated m
The configuration is such that a set of sum bits and a set of carry bits are generated when all partial products are added by a composition means that calculates the respective sums of the set of sum bits and the set of carry bits for each partial sum. 5. A floating point multiplication device according to claim 3 or 4.