JPH03180053A - Printed board for hybrid ic - Google Patents
Printed board for hybrid icInfo
- Publication number
- JPH03180053A JPH03180053A JP1319233A JP31923389A JPH03180053A JP H03180053 A JPH03180053 A JP H03180053A JP 1319233 A JP1319233 A JP 1319233A JP 31923389 A JP31923389 A JP 31923389A JP H03180053 A JPH03180053 A JP H03180053A
- Authority
- JP
- Japan
- Prior art keywords
- board
- conductor pattern
- thickness
- substrate
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 229920005989 resin Polymers 0.000 claims abstract description 13
- 239000011347 resin Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 28
- 239000011248 coating agent Substances 0.000 abstract description 8
- 238000000576 coating method Methods 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000007747 plating Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 230000008602 contraction Effects 0.000 description 2
- 238000012938 design process Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
Abstract
Description
【発明の詳細な説明】
［発明の目的］ 、
（産業上の利用分野）
この発明は樹脂で封止して保護する必要がある半導体ベ
アチップを実装するハイブリットＩＣ用プリント基板に
関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a printed circuit board for a hybrid IC on which a semiconductor bare chip that needs to be protected by being sealed with a resin is mounted.
（従来の技術）
混成集積回路、いわゆるハイブリットＩＣは基板上に形
成された膜回路及び個別部品をはんだ接続等の方法によ
り集積したもので、最近では小形化され、より高度の機
能と集積度をもったものが望まれている。(Prior art) A hybrid integrated circuit, so-called hybrid IC, is a circuit in which film circuits and individual components formed on a substrate are integrated using methods such as soldering. What you have is what you want.
このようなハイブリットＩＣの高集積化の要１清に対応
したｂ″法の一つに、搭載部品のチップ化があげられる
。これには、より高い集積度を得るため実装部品として
、プリント基板に装着後、封ＩＥ等、何らかの保護技術
が必要とされる半導体ベアチップが用いられることが多
い。One of the b'' methods to meet the requirements for high integration of hybrid ICs is to convert mounted components into chips. Semiconductor bare chips are often used that require some kind of protection technology, such as an encapsulation IE, after being mounted on the chip.
第２図は実装部品の一つとして半導体ベアチップを実装
したＣ ＯＢ （ｃｈｉｐ ｏｎ ｂｏａｒｄ）タイ
プの従来のハイブリットＩＣ用プリント基板の購成を示
す断面図である。絶縁基板ｌ１表面上及び與面上に部品
配線や膜回路のための導体パターン１２．１３か形成さ
れ、スルーホール１４による接続箇所が設けられている
。基板１１表面には半導体ベアチップ１５が例えば接着
剤Ｉ６により装着され、周辺に設けられた所定の導体パ
ターンにボンディングワイヤ１７によって接続が施され
た後、防湿と機械的保護のため、コーティング樹脂１８
によりチップ１５とワイヤ１７を覆うように樹脂封止さ
れている。FIG. 2 is a sectional view showing the purchase of a conventional COB (chip on board) type printed circuit board for a hybrid IC on which a semiconductor bare chip is mounted as one of the mounted components. Conductor patterns 12 and 13 for component wiring and film circuits are formed on the surface and the bottom surface of the insulating substrate l1, and connection points by through holes 14 are provided. A semiconductor bare chip 15 is attached to the surface of the substrate 11 using, for example, an adhesive I6, and after connection is made to a predetermined conductor pattern provided around the periphery using a bonding wire 17, a coating resin 18 is applied to the surface of the substrate 11 for moisture proofing and mechanical protection.
The chip 15 and wires 17 are sealed with resin.
ところで、一般に基板１１の表面上及び裏面上の導体パ
ターン１２．１３はそれぞれ同程度の膜厚で形成されて
いる。このようなプリント基板に前記したような半導体
ベアチップ１５が実装される場合、樹脂封ＩＬの際の基
板１１とチップ１５及びコーティング樹脂１８には、熱
膨脹率やその後冷却される際の収縮率に差があり、その
ストレスによって２＆＆１１が歪み、実装部品のある表
面側にそり上がることが多い。Incidentally, the conductor patterns 12 and 13 on the front and back surfaces of the substrate 11 are generally formed with approximately the same film thickness. When the semiconductor bare chip 15 as described above is mounted on such a printed circuit board, the substrate 11, the chip 15, and the coating resin 18 during resin sealing IL have different coefficients of thermal expansion and contraction rates when cooled afterwards. 2&&11 is often distorted by the stress and warped toward the surface side where the mounted components are located.
上記ストレスによって基ｉｔｔが歪み、そりが発生した
プリント基板では、チップ１５とワイヤ１７を覆うコー
ティング樹脂１８にクラックが生じ易く、実装部品の耐
湿性が劣化するという問題がある。In a printed circuit board in which the base is distorted and warped due to the above stress, cracks are likely to occur in the coating resin 18 covering the chip 15 and the wires 17, and there is a problem in that the moisture resistance of the mounted components is deteriorated.
そりが発生しないように十分な厚みを持たせることや、
素材の異なったプリント基板を製造しようとすると、設
計、製造工程上の設備投資にコストがかかり、経済的に
困難である。It must be thick enough to prevent warping,
Attempting to manufacture printed circuit boards made of different materials requires costly equipment investment for design and manufacturing processes, making it economically difficult.
（発明が解決しようとする課題）
このように従来では、半導体ベアチップを樹脂封止にて
基板表面上に実装すると、封止時の熱膨脹率や収縮率が
基板のそれと與なるため、そのストレスによって基板が
歪み、製造されたハイブリッドＩＣの信頼性を劣化させ
る要因となっていた。この対処策として、基板にそりが
発生しないように十分な厚みをＩｊｆたせることや、素
材の異なったプリント基板を製造することは、設計、製
造工程上の設備投資にコストがかかることになり経済的
に問題がある。(Problem to be Solved by the Invention) Conventionally, when a bare semiconductor chip is mounted on the surface of a substrate by resin sealing, the thermal expansion rate and contraction rate at the time of sealing are the same as those of the substrate. The substrate was distorted, which was a factor in deteriorating the reliability of the manufactured hybrid IC. As a countermeasure to this problem, it is not economical to make the board sufficiently thick to prevent warping or to manufacture printed circuit boards made of different materials, as this requires costly capital investment in the design and manufacturing process. There is a problem with this.
この発明は上記のような事情を考慮してなされたもので
あり、その目的は、安価で、ストレスによる基板の歪み
をなくした信頼性の高いハイブリットＩＣ用プリント基
板を提供することにある。This invention was made in consideration of the above circumstances, and its purpose is to provide a highly reliable printed circuit board for a hybrid IC that is inexpensive and free from distortion of the board due to stress.
［発明の構成］
（課題を解決するための手段）
この発明のハイブリットＩＣ用プリント基板は、半導体
ベアチップが直接実装され樹脂封止される基板面におけ
る導体パターン膜厚よりも前記樹脂封止される半導体ベ
アチップが装着されない基板面における導体パターン膜
厚を大きくして構成される。[Structure of the Invention] (Means for Solving the Problems) The hybrid IC printed circuit board of the present invention has a conductor pattern film thickness that is smaller than the thickness of the conductor pattern on the substrate surface on which a semiconductor bare chip is directly mounted and resin-sealed. It is constructed by increasing the thickness of the conductor pattern on the substrate surface where the semiconductor bare chip is not mounted.
（作用）
この発明では、導体パターンを形成するメツキ工程で、
基板の主表面とこれに対する裏面とで異なるメッキ厚制
御をすることにより、実装表面の導体パターン膜厚より
も基板裏面における導体パターン膜厚が大きく形成され
る。これにより、従来の製造工程のままで容易にストレ
スに強いハイブリットＩＣ用プリント基板が得られる。(Function) In this invention, in the plating process for forming the conductor pattern,
By controlling the plating thickness differently between the main surface of the substrate and the back surface thereof, the thickness of the conductor pattern on the back surface of the substrate is formed to be larger than the thickness of the conductor pattern on the mounting surface. As a result, a stress-resistant printed circuit board for a hybrid IC can be easily obtained using conventional manufacturing processes.
（実施例）
以下、図面を参照してこの発明を実施例により説明する
。(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.
第１図はこの発明にかかるＣ ＯＢ （ｃｈｉｐ ｏｎ
ｂｏａｒｄ）タイプのハイブリットＩＣ用プリント基板
を用いて半導体ベアチップを実装した部分の構成を示す
断面図である。絶縁基板１の表面上及び裏面上に部品配
線や膜回路のための導体パターン２．３が形成され、ス
ルーホール４による接続箇所が設けられている。基板１
の所定の表面上には半導体ベアチップ５が例えば接着剤
６により装着され、周辺に設けられた所定の導体パター
ン２にボンディングワイヤ７によって接続が施された後
、防湿と機械的保護のため、コーティング樹脂８により
チップ５とワイヤ７を覆うように樹脂封止されている。Figure 1 shows the COB (chip on
FIG. 2 is a cross-sectional view showing the configuration of a portion where a semiconductor bare chip is mounted using a hybrid IC printed circuit board type. Conductive patterns 2.3 for component wiring and film circuits are formed on the front and back surfaces of the insulating substrate 1, and connection points by through holes 4 are provided. Board 1
A semiconductor bare chip 5 is mounted on a predetermined surface using, for example, an adhesive 6, and after connection is made to a predetermined conductor pattern 2 provided around the periphery with a bonding wire 7, a coating is applied for moisture proofing and mechanical protection. The chip 5 and the wires 7 are sealed with a resin 8 so as to cover them.
このようなプリント基板において、従来と大きく違う点
は、主に実装面となる基板１の主局上における導体パタ
ーン膜厚よりも、主に他の実装部品とのコンタクトがと
られる配線が形成されている前記基板１の裏面における
導体パターン膜厚を大きくしたことである。The major difference between this type of printed circuit board and conventional printed circuit boards is that the thickness of the conductor pattern on the main board of the board 1, which is the mounting surface, is not so much that the wiring that makes contact with other mounted components is formed. The thickness of the conductor pattern on the back surface of the substrate 1 is increased.
異ならせる導体パターン３の膜ノブは例えば、基板の面
積及び半導体ベアチップの樹脂のコーティングの度合に
よって決まり、導体パターン３形成するメツキ工程で、
７！仮の表面と裏面とで叉なるメッキ厚制御をすること
により実現される。このメッキ厚制御により、実装され
る部品に合った強度の基板が得られ、従来の製造工程の
ままで容易にストレスに強いハイブリットＩＣ用プリン
ト基板が完成される。例えば、ガラスエポキシ樹脂基板
材上に電解銅箔を導体パターンとして形成する場合、そ
のメツキ工程において、主面におけるメツキ時間に対し
、裏面は２倍程度の時間をかけてメツキを行い、主面の
導体パターン膜厚に対して裏面は２倍程度の導体パター
ン膜厚を得る。これにより、基板１が厚みを増したこと
になり、ストレスに対する強度が大きくなる。The film knob of the conductor pattern 3 to be made different is determined, for example, by the area of the substrate and the degree of resin coating of the semiconductor bare chip, and is determined in the plating process for forming the conductor pattern 3.
7! This is achieved by controlling the plating thickness differently on the temporary front and back sides. By controlling the plating thickness, a board with a strength suitable for the components to be mounted can be obtained, and a stress-resistant printed circuit board for a hybrid IC can be easily completed using conventional manufacturing processes. For example, when forming electrolytic copper foil as a conductive pattern on a glass epoxy resin substrate material, in the plating process, the back side is plated for about twice as long as the main surface. The conductor pattern film thickness on the back side is approximately twice that of the conductor pattern film thickness. This increases the thickness of the substrate 1 and increases its strength against stress.
従って、第１図のようにこのプリント基板に半導体ベア
チップ５が実装される場合、樹脂封止の際の基板１とチ
ップ５及びコーティング樹脂８に、熱膨脹率やその後冷
却される際の収縮率に多少の差があっても、そのストレ
スによって基板１が歪んで、いわゆる、そりが発生する
ことはない。この結果、コーティング樹脂８の効用は劣
化することなく、実装部品の気密性が向上する。Therefore, when the semiconductor bare chip 5 is mounted on this printed circuit board as shown in FIG. Even if there is a slight difference, the stress will not distort the substrate 1 and cause so-called warpage. As a result, the effectiveness of the coating resin 8 is not deteriorated, and the airtightness of the mounted components is improved.
さらに上記構成によれば、膜厚の大きい導体パターン３
を他の実装部品とつなぐ配線としてなるべく多く利用す
れば、より低抵抗の配線が形成できる利点がある。Furthermore, according to the above configuration, the conductor pattern 3 having a large film thickness
There is an advantage that wiring with lower resistance can be formed by using as many wires as possible to connect with other mounted components.
なお、この発明の実施例は１層の基板について説明した
が、多層構造の基板についても同様であり、各層の導体
パターン膜厚を必要に応じて変化させて基板のそりを防
ぐことができる。Although the embodiments of the present invention have been described with respect to a single-layer substrate, the same applies to a multi-layer substrate, and warpage of the substrate can be prevented by changing the thickness of the conductive pattern of each layer as necessary.
［発明の効果］
以上説明したようにこの発明によれば、従来の製造工程
のまま安価でストレスによる基板の歪みをなくした信頼
性の高いハイブリットＩＣ用プリントｕ板が提供できる
。[Effects of the Invention] As described above, according to the present invention, it is possible to provide a highly reliable printed U-board for a hybrid IC that is inexpensive and eliminates substrate distortion due to stress using conventional manufacturing processes.
第１図はこの発明の一大施例による構成の断面図、第２
図は従来のハイブリットＩＣ用プリント越板を説明する
ための断面図である。
１・・・絶縁基板、２．３・・・導体パターン、４・・
・スルーホール、５・・・半導体ベアチップ、６・・・
接着剤、７・・・ボンディングワイヤ、８・・・コーテ
ィング樹脂。FIG. 1 is a sectional view of a configuration according to a major embodiment of the present invention, and FIG.
The figure is a sectional view for explaining a conventional printed board for hybrid IC. 1... Insulating substrate, 2.3... Conductor pattern, 4...
・Through hole, 5...Semiconductor bare chip, 6...
Adhesive, 7... Bonding wire, 8... Coating resin.
Claims (1)
ターンと、 前記基板上に半導体ベアチップが直接実装され樹脂封止
された樹脂封止型半導体装置とを具備し、前記導体パタ
ーンにおいて、前記樹脂封止型半導体装置が装着される
基板面での導体パターン膜厚よりも前記樹脂封止型半導
体装置が装着されない基板面での導体パターン膜厚を大
きくしたことを特徴とするハイブリットＩＣ用プリント
基板。[Scope of Claims] A semiconductor device comprising conductor patterns formed on both surfaces of a substrate with different thicknesses, and a resin-sealed semiconductor device in which a semiconductor bare chip is directly mounted on the substrate and sealed with resin, The pattern is characterized in that the thickness of the conductor pattern on the surface of the substrate to which the resin-sealed semiconductor device is not mounted is greater than the thickness of the conductor pattern on the surface of the substrate to which the resin-sealed semiconductor device is mounted. Printed circuit board for hybrid IC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1319233A JPH03180053A (en) | 1989-12-08 | 1989-12-08 | Printed board for hybrid ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1319233A JPH03180053A (en) | 1989-12-08 | 1989-12-08 | Printed board for hybrid ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03180053A true JPH03180053A (en) | 1991-08-06 |
Family
ID=18107898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1319233A Pending JPH03180053A (en) | 1989-12-08 | 1989-12-08 | Printed board for hybrid ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03180053A (en) |
-
1989
- 1989-12-08 JP JP1319233A patent/JPH03180053A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7180012B2 (en) | Module part | |
| KR950012658B1 (en) | Semiconductor chip mounting method and substrate structure | |
| US7906835B2 (en) | Oblong peripheral solder ball pads on a printed circuit board for mounting a ball grid array package | |
| US20060038235A1 (en) | Semiconductor device | |
| US8302277B2 (en) | Module and manufacturing method thereof | |
| US6486551B1 (en) | Wired board and method of producing the same | |
| JP2001015628A (en) | Semiconductor device and substrate therefor | |
| JP3370498B2 (en) | Substrate for semiconductor device | |
| JPH1056101A (en) | Ball grid array package without mutual connection among through holes and vias | |
| JPH11233531A (en) | Structure and method for packaging electronic part | |
| KR100199286B1 (en) | Chip-scale package having pcb formed with recess | |
| JPH04206658A (en) | Hermetic seal type electric circuit device | |
| JPH03180053A (en) | Printed board for hybrid ic | |
| KR100207902B1 (en) | Multi chip package using lead frame | |
| JP2925609B2 (en) | Method for manufacturing semiconductor device | |
| JPH0342860A (en) | Flexible printed wiring board | |
| JPH0645763A (en) | Printed wiring board | |
| JPH098222A (en) | Electronic component device with mounted semiconductor device | |
| JPH06112633A (en) | Circuit board | |
| JP2652222B2 (en) | Substrate for mounting electronic components | |
| JP3136274B2 (en) | Semiconductor device | |
| JPH08167676A (en) | Semiconductor device | |
| JP2700257B2 (en) | Lead frame with wiring board and method of manufacturing the same | |
| JP2822446B2 (en) | Hybrid integrated circuit device | |
| KR19990002341A (en) | Printed circuit board for mixing heterogeneous chip parts and manufacturing method |