JPH06112633A - Circuit board - Google Patents

Circuit board

Info

Publication number
JPH06112633A
JPH06112633A JP25841592A JP25841592A JPH06112633A JP H06112633 A JPH06112633 A JP H06112633A JP 25841592 A JP25841592 A JP 25841592A JP 25841592 A JP25841592 A JP 25841592A JP H06112633 A JPH06112633 A JP H06112633A
Authority
JP
Japan
Prior art keywords
circuit board
resist layer
layer
circuit pattern
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25841592A
Other languages
Japanese (ja)
Inventor
Teruyoshi Baba
照義 馬場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP25841592A priority Critical patent/JPH06112633A/en
Publication of JPH06112633A publication Critical patent/JPH06112633A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a circuit board which is so constituted as to have a very high resistance against corrosive gas and humidity. CONSTITUTION:A circuit pattern 2 is formed on a printed board 1. A first resist layer 3 is applied to a part of the circuit pattern 2. A conducting layer 4 (a plating layer of metal such as solder, nickel or gold) is applied to the part of the circuit pattern 2 which is not covered with the first resist layer 3. A boundary 10 between the first resist layer 4 and the conducting layer 1 is covered with a second resist layer 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ソルダーレジストを有
する回路用基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board having a solder resist.

【0002】[0002]

【従来の技術】図3は、ソルダーレジストを有する回路
用基板の従来例を示す平面図であり、図2(b)は図3
のB−B断面図を示す。又、図2(a)は該回路用基板
を作成する過程の一部を示す図である。
2. Description of the Related Art FIG. 3 is a plan view showing a conventional example of a circuit board having a solder resist, and FIG.
FIG. In addition, FIG. 2A is a diagram showing a part of the process of producing the circuit board.

【0003】従来、ガスが発生したり湿度が極めて高い
等の悪条件な場所に取り付けられる例えば火災感知器等
の機器においては、亜硫酸ガス等の腐食ガスによる腐食
試験に耐える構造が必要となっており、そのため、前記
亜硫酸ガスにより内蔵のプリント基板が腐食破壊されな
いように該プリント基板の表面にソルダーレジストを形
成して該プリント基板を保護するようになっている。こ
のように、プリント基板1の表面にソルダーレジストを
施して成る回路用基板としては従来、例えば図2(b)
又は図3に示すようなものがある。即ち、該回路用基板
は、表面に銅による回路パターン2を敷設したプリント
基板1において、回路素子をはんだ接続する素子接続部
分の表面に、導電層4を被着し、該導電層4を除く全て
のプリント基板1表面部分に、エポキシ樹脂等によるレ
ジスト層3を被着して成っている。尚、例えば半導体チ
ップがワイヤーボンディングされるような回路パターン
2表面には、ニッケルや金等の金属メッキにより前記導
電層4を形成し、その他一般の電子素子等が半田接続さ
れるような回路パターン2表面には、半田により前記導
電層4を形成する。
[0003] Conventionally, in equipment such as fire detectors, which is installed in places where gas is generated or humidity is extremely high, it is necessary to have a structure that can withstand a corrosion test using a corrosive gas such as sulfurous acid gas. Therefore, a solder resist is formed on the surface of the printed circuit board to protect the printed circuit board from being corroded and destroyed by the sulfurous acid gas. As described above, a circuit board formed by applying a solder resist to the surface of the printed circuit board 1 is conventionally used, for example, as shown in FIG.
Alternatively, there is one as shown in FIG. That is, in the printed circuit board 1 having a circuit pattern 2 made of copper laid on the surface thereof, the circuit board has a conductive layer 4 attached to the surface of an element connecting portion for soldering a circuit element, and the conductive layer 4 is removed. A resist layer 3 made of epoxy resin or the like is attached to the entire surface of the printed circuit board 1. It should be noted that, for example, on the surface of the circuit pattern 2 to which the semiconductor chip is wire bonded, the conductive layer 4 is formed by metal plating such as nickel or gold, and other general electronic elements are connected to the circuit pattern by soldering. The conductive layer 4 is formed on the surface 2 by soldering.

【0004】従来、前記構成の回路用基板を作成するに
は、先ず図2(a)に示すように、前記回路パターン2
の素子接続部分以外のプリント基板1表面部分に、前記
レジスト層3を被着し、その後、図2(b)に示すよう
に、前記レジスト層3をマスクとして該レジスト層3が
被着していない全ての部分、即ち前記回路パターン2の
素子接続部分に、半田や金属メッキ等により導電層4を
被着形成する。
Conventionally, in order to produce a circuit board having the above-mentioned structure, first, as shown in FIG.
The resist layer 3 is deposited on the surface portion of the printed circuit board 1 other than the element connection portion of FIG. 2, and then, as shown in FIG. 2B, the resist layer 3 is deposited using the resist layer 3 as a mask. The conductive layer 4 is deposited on all the remaining portions, that is, the element connection portions of the circuit pattern 2 by soldering or metal plating.

【0005】[0005]

【発明が解決しようとする課題】然しながら、従来の構
成においては、前記回路パターン2上における導電層4
とレジスト層3との境界10に、前記回路パターン2に
まで達するようなピンホールが出来やすく、該ピンホー
ルが少しでも存在すると、腐食試験の際に該ピンホール
から回路パターン2が腐食されて該回路パターン2が切
断してしまうという重大な問題が生じていた。又、前記
境界10以外の場所においてもピンホールがあると該ピ
ンホールから回路パターン2が腐食されてしまうという
重大な問題が生じていた。又、該ピンホールから湿気が
入り込んで回路パターン2に錆が発生する等の問題もあ
った。
However, in the conventional structure, the conductive layer 4 on the circuit pattern 2 is used.
At the boundary 10 between the resist layer 3 and the resist layer 3, it is easy to form a pinhole reaching the circuit pattern 2. If there is any pinhole, the circuit pattern 2 is corroded from the pinhole during the corrosion test. There has been a serious problem that the circuit pattern 2 is cut off. Further, if there is a pinhole at a place other than the boundary 10, the circuit pattern 2 is corroded from the pinhole, which is a serious problem. Further, there is a problem that moisture enters from the pinholes and rust is generated on the circuit pattern 2.

【0006】本発明は、係る問題に鑑みてなされたもの
であり、その目的とするところは、腐食ガスや湿気に対
して極めて強い構成の回路用基板を提供することにあ
る。
The present invention has been made in view of the above problems, and an object thereof is to provide a circuit board having a structure extremely resistant to corrosive gas and humidity.

【0007】[0007]

【課題を解決するための手段】上記課題を解決するため
本発明は、基板に敷設された回路パターンの表面に、第
1レジスト層と導電層とが被着されて成ると共に、前記
第1レジスト層と前記導電層との境界が第2レジスト層
により覆われて成ることを特徴とする回路用基板であ
る。
In order to solve the above-mentioned problems, the present invention comprises a first resist layer and a conductive layer deposited on the surface of a circuit pattern laid on a substrate, and the first resist. The circuit board is characterized in that a boundary between the layer and the conductive layer is covered with a second resist layer.

【0008】[0008]

【作用】本発明によれば、腐食ガスや湿気から基板を完
全に保護出来る。
According to the present invention, the substrate can be completely protected from corrosive gas and moisture.

【0009】[0009]

【実施例】以下に図面を参照して、本発明の実施例を説
明する。尚、前記従来例と同様の構成要件については同
一符号を付する。
Embodiments of the present invention will be described below with reference to the drawings. The same components as those of the conventional example are designated by the same reference numerals.

【0010】図1(b)は、本発明実施例の回路用基板
を示す平面図であり、図1(a)は、図1(b)のA−
A断面図である。
FIG. 1 (b) is a plan view showing a circuit board according to an embodiment of the present invention, and FIG. 1 (a) is an A- line in FIG. 1 (b).
FIG.

【0011】本発明実施例の回路用基板は、ソルダーレ
ジストが2層から成っており、前記の図2(b)に示す
従来例の回路用基板のレジスト層3(以下、「第1レジ
スト層3」という)に更に第2レジスト層5が被着され
ており、該レジスト層5により、前記第1レジスト層3
と前記導電層4との境界10が覆われて成っている。前
記第1レジスト層3と前記第2レジスト層5とは、従来
と同様、エポキシ樹脂等の絶縁樹脂を以て構成する。
The circuit board of the embodiment of the present invention comprises two layers of solder resist, and the resist layer 3 (hereinafter referred to as "first resist layer") of the circuit board of the conventional example shown in FIG. 3 ") is further coated with a second resist layer 5 by means of which the first resist layer 3
The boundary 10 between the conductive layer 4 and the conductive layer 4 is covered. The first resist layer 3 and the second resist layer 5 are made of an insulating resin such as an epoxy resin as in the conventional case.

【0012】本発明実施例の回路用基板を作成する場
合、先ず、従来と同様に、前記回路パターン2の素子接
続部分以外のプリント基板1表面部分に、前記第1レジ
スト層3を被着する。前記プリント基板1に前記第1レ
ジスト層3を被着するには、孔空きの印刷版を使用して
前記絶縁樹脂を前記プリント基板1に塗布して硬化させ
るようにする。
In producing the circuit board of the embodiment of the present invention, first, as in the conventional case, the first resist layer 3 is applied to the surface portion of the printed board 1 other than the element connection portion of the circuit pattern 2. . In order to deposit the first resist layer 3 on the printed circuit board 1, a printing plate having holes is used to apply the insulating resin to the printed circuit board 1 and cure it.

【0013】その後、前記第1レジスト層3をマスクと
して該第1レジスト層3が被着していない全ての部分、
即ち前記回路パターン2の素子接続部分に、半田又はニ
ッケル、金等の金属メッキ等による導電層4を被着形成
して、図2(b)に示す従来構造を作成する。
Thereafter, using the first resist layer 3 as a mask, all the portions where the first resist layer 3 is not deposited,
That is, the conductive layer 4 is deposited on the element connection portion of the circuit pattern 2 by soldering or metal plating of nickel, gold or the like to form the conventional structure shown in FIG.

【0014】その後、前記第1レジスト層3の上から前
記印刷版の位置をずらして更に前記絶縁樹脂を印刷被着
し、硬化させて、第2レジスト層5を被着形成する。こ
のとき、前記第1レジスト層3と前記導電層4との境界
10を前記絶縁樹脂が完全に覆うように、前記印刷版の
位置を前記第2レジスト層5の厚さ分だけずらして、前
記絶縁樹脂を印刷する。それにより、図1に示すよう
に、前記第1レジスト層3と前記導電層4との境界10
を覆う第2レジスト層5が被着形成される。該第2レジ
スト層5により、前記境界10に発生していたピンホー
ルは外気から完全に遮断されるので、亜硫酸ガス等の腐
食ガスや湿気が前記回路パターン2にまで達することが
無く、該回路パターン2の腐食や錆発生等を確実に防止
出来る。
After that, the position of the printing plate is shifted from the first resist layer 3 and the insulating resin is printed and adhered and cured to form the second resist layer 5. At this time, the position of the printing plate is shifted by the thickness of the second resist layer 5 so that the boundary 10 between the first resist layer 3 and the conductive layer 4 is completely covered with the insulating resin. Print the insulating resin. Thereby, as shown in FIG. 1, a boundary 10 between the first resist layer 3 and the conductive layer 4 is formed.
A second resist layer 5 is deposited to cover. The second resist layer 5 completely shields the pinholes generated at the boundary 10 from the outside air, so that corrosive gas such as sulfurous acid gas or humidity does not reach the circuit pattern 2 and the circuit is prevented. It is possible to reliably prevent the corrosion and rust of the pattern 2.

【0015】尚、本実施例の回路用基板における第2レ
ジスト層5は、前記第1レジスト層3と前記導電層4と
の境界10を覆うばかりで無く、前記第1レジスト層3
の殆どを外観から隠すように覆っているので、前記境界
10以外の場所のピンホールをも覆うことが出来、前記
回路パターン2にまで達するようなピンホールは殆ど存
在し得ないので、腐食ガスに対して非常に強い回路用基
板を構成することが出来る。又、前記回路用基板を高湿
度の条件下において使用しても、従来のようにピンホー
ルから湿気が入り込むことが無いので前記回路パターン
2における錆等の発生を防止出来、本発明実施例の回路
用基板は湿気に対しても非常に強い。
The second resist layer 5 in the circuit board of this embodiment not only covers the boundary 10 between the first resist layer 3 and the conductive layer 4, but also the first resist layer 3
Since most of them are covered so as to be hidden from the appearance, pinholes other than the boundary 10 can be covered, and there can be almost no pinhole reaching the circuit pattern 2. It is possible to construct a circuit board that is extremely strong against. Further, even if the circuit board is used under high humidity conditions, moisture does not enter from the pinhole as in the conventional case, so that the generation of rust or the like in the circuit pattern 2 can be prevented. Circuit boards are also extremely resistant to moisture.

【0016】[0016]

【発明の効果】以上の如く構成した本発明によれば、腐
食ガスや湿気等に非常に強い回路用基板を構成出来る。
According to the present invention constructed as described above, it is possible to construct a circuit board which is extremely resistant to corrosive gas, moisture and the like.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例の回路用基板を示す断面図(a)
及び平面図(b)。尚、(a)は(b)のA−A断面図
を示す。
FIG. 1 is a sectional view showing a circuit board according to an embodiment of the present invention (a).
And a plan view (b). In addition, (a) shows the AA sectional view of (b).

【図2】従来例の回路用基板を示す断面図(b)及び該
回路用基板を作成する過程の一部を示す断面図(a)。
尚、(b)は図3のB−B断面図であり、本発明実施例
の回路用基板を作成する過程の一部をも示す。
FIG. 2 is a cross-sectional view showing a circuit board of a conventional example (b) and a cross-sectional view showing a part of a process of producing the circuit board (a).
3B is a sectional view taken along the line BB in FIG. 3 and also shows a part of the process of producing the circuit board of the embodiment of the present invention.

【図3】従来例の回路用基板を示す平面図。FIG. 3 is a plan view showing a conventional circuit board.

【符号の説明】[Explanation of symbols]

1 プリント基板 2 回路パターン 3 第1レジスト層 4 導電層 5 第2レジスト層 10 境界 1 Printed Circuit Board 2 Circuit Pattern 3 First Resist Layer 4 Conductive Layer 5 Second Resist Layer 10 Boundary

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基板に敷設された回路パターンの表面
に、第1レジスト層と導電層とが被着されて成ると共
に、前記第1レジスト層と前記導電層との境界が第2レ
ジスト層により覆われて成ることを特徴とする回路用基
板。
1. A surface of a circuit pattern laid on a substrate is coated with a first resist layer and a conductive layer, and a boundary between the first resist layer and the conductive layer is formed by a second resist layer. A circuit board characterized by being covered.
JP25841592A 1992-09-28 1992-09-28 Circuit board Pending JPH06112633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25841592A JPH06112633A (en) 1992-09-28 1992-09-28 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25841592A JPH06112633A (en) 1992-09-28 1992-09-28 Circuit board

Publications (1)

Publication Number Publication Date
JPH06112633A true JPH06112633A (en) 1994-04-22

Family

ID=17319912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25841592A Pending JPH06112633A (en) 1992-09-28 1992-09-28 Circuit board

Country Status (1)

Country Link
JP (1) JPH06112633A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003037353A (en) * 2001-07-24 2003-02-07 Shindo Denshi Kogyo Kk Flexible circuit board and its manufacturing method
JP2004055846A (en) * 2002-07-19 2004-02-19 Matsushita Electric Works Ltd Method for isolating wiring pattern of printed wiring board and fire detector equipped with printed wiring board whose wiring pattern is isolated thereby
JP2014053608A (en) * 2012-09-10 2014-03-20 Samsung Electro-Mechanics Co Ltd Circuit board and production method of the same
JP2015141998A (en) * 2014-01-28 2015-08-03 ファナック株式会社 Printed circuit board including structure for preventing disconnection of wiring pattern due to corrosion
JP2020035898A (en) * 2018-08-30 2020-03-05 京セラ株式会社 Substrate for mounting electronic element, electronic apparatus, and electronic module
CN111201842A (en) * 2017-10-18 2020-05-26 住友电气工业株式会社 Printed circuit board and method of manufacturing printed circuit board

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003037353A (en) * 2001-07-24 2003-02-07 Shindo Denshi Kogyo Kk Flexible circuit board and its manufacturing method
JP2004055846A (en) * 2002-07-19 2004-02-19 Matsushita Electric Works Ltd Method for isolating wiring pattern of printed wiring board and fire detector equipped with printed wiring board whose wiring pattern is isolated thereby
JP2014053608A (en) * 2012-09-10 2014-03-20 Samsung Electro-Mechanics Co Ltd Circuit board and production method of the same
JP2015141998A (en) * 2014-01-28 2015-08-03 ファナック株式会社 Printed circuit board including structure for preventing disconnection of wiring pattern due to corrosion
CN111201842A (en) * 2017-10-18 2020-05-26 住友电气工业株式会社 Printed circuit board and method of manufacturing printed circuit board
JP2020035898A (en) * 2018-08-30 2020-03-05 京セラ株式会社 Substrate for mounting electronic element, electronic apparatus, and electronic module

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