JPH03174731A - Bump electrode for integrated circuit and manufacture thereof - Google Patents

Bump electrode for integrated circuit and manufacture thereof

Info

Publication number
JPH03174731A
JPH03174731A JP24562990A JP24562990A JPH03174731A JP H03174731 A JPH03174731 A JP H03174731A JP 24562990 A JP24562990 A JP 24562990A JP 24562990 A JP24562990 A JP 24562990A JP H03174731 A JPH03174731 A JP H03174731A
Authority
JP
Japan
Prior art keywords
base
bump electrode
chip
tip
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24562990A
Other languages
Japanese (ja)
Inventor
Hiroyuki Ishikawa
弘之 石川
Akira Amano
彰 天野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of JPH03174731A publication Critical patent/JPH03174731A/en
Pending legal-status Critical Current

Links

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the risk of damage to the base and chip during the mounting of the chip by employing a stepped bump structure, in which each bump electrode protruding from the chip surface of a semiconductor integrated circuit includes a base and a tip, coaxial with the base, having a cross section half that of the base. CONSTITUTION:Small bump electrodes 10 are provided on a chip 1. Each bump electrode has a stepped structure, which includes a base 11 and a tip 12 that is smaller than, and coaxial with, the base 11. The tip 12 has loss than half the cross section of the base 11. These bump electrodes are pressed against wiring conductors 32 of a printed-circuit board 30, or they are bonded using shrink curing resin. At first, the tip must be pressed to bring all the bump electrodes into contact with the corresponding conductors 32. The required pressure to be applied is relatively small because the small-area tips 12 can easily be deformed. Therefore, it is possible to eliminate damage to the base and chip during the mounting of the chip.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路装置の外部接続用にそのチップから
突設されるバンプ電極に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to bump electrodes that protrude from a chip of an integrated circuit device for external connection.

〔従来の技術〕[Conventional technology]

近年の高集積化技術の進展とともに1個の集積回路装置
内に組み込まれる回路数が増加し、これに応じて外部と
の接続点数が増加傾向にあり、最近では実装と外部接続
形態を合理化するために外部接続点としてバンプ電極を
設けたフリップチップを利用することが多くなってきた
With the recent progress in high-integration technology, the number of circuits built into a single integrated circuit device has increased, and the number of connection points with the outside has also tended to increase accordingly. Therefore, flip chips equipped with bump electrodes as external connection points are increasingly being used.

かかる高集積化された集積回路装置のフリップチップで
は、数mm角の小形チップの周縁に沿って各数十μmの
ヅイズの小形バンプ電極が数十μmの狭い配列ピッチで
数十から数百個程度配設される。
In the flip chip of such a highly integrated integrated circuit device, dozens to hundreds of small bump electrodes, each several tens of micrometers in size, are arranged at a narrow arrangement pitch of several tens of micrometers along the periphery of a small chip of several millimeters square. It is arranged to a certain extent.

第3図は従来の小形バンプ電極を、第4図はこれを備え
るフリップチップを配線基板に実装した状態をそれぞれ
拡゛大して示すものである。
FIG. 3 is an enlarged view of a conventional small bump electrode, and FIG. 4 is an enlarged view of a flip chip equipped with the same mounted on a wiring board.

第3図において、集積回路装置のチップ1の表面を覆う
酸化膜2上に配線膜3が配設され、さらにその上に保護
膜4が被せられており、配線膜3の端部上の保護膜4に
明けた窓部にバンプ電極IOが設けられる。この小形の
バンプ電極10用の金属には金や銅が主に用いられ、窓
部内で配線膜3に導電接触する下側下地膜5aと上側下
地膜5bの上に電解めっき法によって成長される。かか
る従来の小形バンプ電極10は例えば30μm角ないし
径のサイズと20μmの高さを有するが、電解めっきで
成長される関係上図示のようにその先端部が基部よりも
大に例えば40〜50μmに膨れたいわば露状に形成さ
れるのがふつうである。
In FIG. 3, a wiring film 3 is disposed on an oxide film 2 covering the surface of a chip 1 of an integrated circuit device, and a protective film 4 is further placed thereon to protect the ends of the wiring film 3. Bump electrodes IO are provided in the windows opened in the membrane 4. Gold or copper is mainly used as the metal for this small bump electrode 10, and is grown by electrolytic plating on the lower base film 5a and upper base film 5b that are in conductive contact with the wiring film 3 within the window. . Such a conventional small bump electrode 10 has a size of, for example, 30 μm square or diameter and a height of 20 μm, but since it is grown by electrolytic plating, the tip is larger than the base, for example, 40 to 50 μm, as shown in the figure. It is usually formed in a swollen, dew-like shape.

第4図はかかるバンプ電極10を備えるチップ1を配線
基板30上にいわゆるフェースダウン実装した状態を示
す。この実装時にハング電極10は、この例のように配
線基板30のセラミック等の絶縁基板31上に配設され
た配線導体32と直接に、あるいはその上に突設された
同様なバンプ電極と接続ないしは接合される。この際の
接続手段としては、加温加圧下でいわゆる圧接する手段
や、接続部のまわりを赤外線硬化樹脂で囲みその硬化時
収縮カを利用して接続する手段等が採用される。
FIG. 4 shows a state in which the chip 1 having such a bump electrode 10 is mounted on a wiring board 30 in a so-called face-down manner. During this mounting, the hang electrode 10 is connected directly to the wiring conductor 32 disposed on the insulating substrate 31 made of ceramic or the like of the wiring board 30 as in this example, or to a similar bump electrode protruding thereon. or joined. As the connection means in this case, a means of so-called pressure contact under heating and pressure, a means of surrounding the connection part with an infrared curable resin and making use of the shrinkage force of the resin upon curing, etc., are employed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、集積回路装置のチップから突設される数十な
いし数百側のバンプ電極にはその高さに最低±10%程
度のばらつきが不可避的に発生するので、配線基板等へ
の実装時に上述のどの接続手段をとるにせよバンプ電極
あたり例えば30g程度の加圧力を加えてバンプ電極の
高さのばらつきを補償する必要があり、この加圧力によ
ってバンプ電極自体やその下側のチップの表面部が損傷
するトラブルが発生しやすい問題がある。
However, since the height of the bump electrodes, which protrude from the chip of an integrated circuit device by several tens or hundreds, inevitably varies by at least ±10%, the above-mentioned differences occur when mounting on a wiring board, etc. Regardless of which connection method is used, it is necessary to apply a pressure force of, for example, about 30 g per bump electrode to compensate for variations in the height of the bump electrode. There are problems that can easily lead to damage.

第4図では高さが平均よりも大なバンプ電極が符号10
aで示されており、上述の加圧力により正常な高さのバ
ンプ電極10の配線導体32との接続を確実にするため
図示のようにかなり大きく変形される。これと同時に、
第3図に小円りで示した個所の配線膜3.酸化膜2ある
いはチップ1の表面部に加圧力Pにより損傷が発生しゃ
すく、バンプ電極10が外れてしまったり、保護膜4に
クラックないし破損が生じて集積回路の特性劣化を招い
たりするトラブルが発生しゃすい。
In Figure 4, the bump electrode with a height larger than the average is numbered 10.
The bump electrode 10 is deformed considerably by the above-mentioned pressing force as shown in the figure in order to ensure the connection with the wiring conductor 32 of the normal height. At the same time,
Wiring film 3 at the location indicated by a small circle in FIG. Damage may occur on the surface of the oxide film 2 or the chip 1 due to the pressure P, causing troubles such as the bump electrode 10 coming off or cracks or damage occurring in the protective film 4, resulting in deterioration of the characteristics of the integrated circuit. It happens.

さらに、従来のバンプ電極1oは前述のように露状で基
部の強度が低いので、その先端が物に触れまたは当たっ
て第3図でSで示す剪断方向に外力が掛かると比較的簡
単に外れてしまいやすい問題があり、実装時はもちろん
運搬時等にも取り扱いを慎重にせねばならない。
Furthermore, as mentioned above, the conventional bump electrode 1o is exposed and has low strength at the base, so if the tip touches or hits an object and an external force is applied in the shearing direction shown by S in FIG. 3, it will come off relatively easily. There is a problem in that it is easy to be damaged, so it must be handled with care not only during mounting but also during transportation.

また、バンプ電極10を熱圧着ではんだっけする場合、
バンプ電極10の高さのばらつき、配線導体32との高
さばらつきにより、バンプ電極1oと配線導体32とが
接触しない、あるいは余剰はんだのはんだたれによる隣
接バンプ電極とのブリッジが生じるというトラブルが発
生しゃすい。
In addition, when soldering the bump electrode 10 by thermocompression bonding,
Due to variations in the height of the bump electrode 10 and the height with respect to the wiring conductor 32, problems occur such that the bump electrode 1o and the wiring conductor 32 do not come into contact with each other, or bridges with adjacent bump electrodes occur due to excess solder dripping. Shasui.

本発明はかかる問題を解決して、集積回路装置のチップ
の実装時に加圧力が掛かった際にバンプ電極自体あるい
はチップ本体が損傷を受ける危険を減少させるあるいは
バンプ電極と配線導体との接続を確実にすることを目的
とする。
The present invention solves this problem and reduces the risk of damage to the bump electrode itself or the chip body when pressure is applied during mounting of a chip in an integrated circuit device, or ensures the connection between the bump electrode and the wiring conductor. The purpose is to

〔課題を解決するための手段〕[Means to solve the problem]

この目的は本発明によれば、集積回路装置のチップ面か
ら突設される金属のバンプ電極を同心状に積み重なった
基部と先端部とからなる段付構造とし、先端部の面積を
基部の面積の2分の1以下に形成することによって達成
される。
According to the present invention, the metal bump electrodes protruding from the chip surface of an integrated circuit device are formed into a stepped structure consisting of a concentrically stacked base and a tip, so that the area of the tip is equal to the area of the base. This can be achieved by forming it to one-half or less.

上述のバンプ電極の基部と先端部は、それぞれ別のフォ
トレジスト膜をマスクとして、そのめっき用開口内に拘
束された状態で電解めっき法により成長させるのが好適
である。
The base and tip of the bump electrode described above are preferably grown by electrolytic plating while being restrained within the plating openings using separate photoresist films as masks.

〔作用〕[Effect]

本発明は従来のバンプ電極の問題がその露状の形状に起
因していることに着目して、バンプ電極を電解めっきに
よる成長に有利なよう基部と先端部からなる段付構造と
し、かつ先端部の面積を基部の面積の2分の1以下にす
ることにより、チップの実装時に特定のバンプ電極の大
きな加圧力が掛かったときにその先端部のみを変形させ
、基部の変形やその下側のチップ表面部の損傷が発生し
ないようにしたものである。また、すべてのバンブ電極
が配線導体と確実に接続される。
The present invention focuses on the fact that the problem with conventional bump electrodes is caused by their dewy shape.The present invention provides bump electrodes with a stepped structure consisting of a base and a tip to facilitate growth by electrolytic plating. By making the area of the bump electrode less than half of the area of the base, when a large pressing force is applied to a specific bump electrode during chip mounting, only the tip of the bump electrode is deformed, preventing deformation of the base and the area below it. This prevents damage to the chip surface. Moreover, all the bump electrodes are reliably connected to the wiring conductors.

〔実施例〕〔Example〕

以下、図を参照しながら本発明の詳細な説明する。第1
図は本発明によるバンブ電極を備えた集積回路装置のチ
ップ1を配線、基板30上にフェースダウン実装する際
の状態を、第2図はこのバンブ電極10をチップ1上に
作り込む要領をそれぞれ例示するもので、第3図と第4
図との対応部分には同符号が付されている。
Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure shows the state when a chip 1 of an integrated circuit device equipped with a bump electrode according to the present invention is mounted face-down on wiring and a substrate 30, and FIG. 2 shows the procedure for making this bump electrode 10 on the chip 1. For illustrative purposes, Figures 3 and 4
Parts corresponding to those in the figure are given the same reference numerals.

第1図において、チップlから突設された本発明による
バンブ電極10は例えば金からなる小形のバンブ電極で
あって、基部11とこれと同心でかつそれよりも面積の
小さな先端部12とからなる段付構造をもち、例えば基
部11は20μm角ないし径、先端部12は10μm角
ないし径のサイズとされ、全体の高さは10μm程度と
される。本発明によるハング電極10では、先端部12
のM部11に対する面積比は2分の1以下とされ、その
下限はふつう6分の1以上とされるが、実装時に先端部
12が容易に変形し得るようにこの実施例のように4分
の1程度とするのが実用上鏝も望ましい。
In FIG. 1, a bump electrode 10 according to the present invention protruding from a tip l is a small bump electrode made of, for example, gold, and is made up of a base 11 and a tip 12 that is concentric with the base and has a smaller area. For example, the base portion 11 is 20 μm square or in diameter, the tip portion 12 is 10 μm square or in diameter, and the overall height is about 10 μm. In the hang electrode 10 according to the present invention, the tip portion 12
The area ratio of the M part 11 to the M part 11 is set to be 1/2 or less, and the lower limit is usually set to 1/6 or more, but in order to easily deform the tip part 12 during mounting, the Practically speaking, it is desirable to use a trowel to reduce the amount by about 1/2.

本発明によるバンブ電極10においてもその高さに最低
±10%程度のばらつきが出るので、これを配線基板3
0の配線導体32等に前述のように圧接しまたは収縮硬
化性樹脂を利用して接続する際に、従来と同様にまず加
圧力を加えてチップ1の全てのバンブ電極10を図のよ
うに対応する配線導体32に確実に接触させる必要があ
るが、本発明の場合はバンブ電極10の面積の小な先端
部12が容易に変形可能なので、このための加圧力は従
来よりも低くてよく、例えばこの実施例ではバンプ電極
膜たり10〜15gとすることでよい。
Even in the bump electrode 10 according to the present invention, there is a variation in height of at least ±10%, so this is
When connecting to the wiring conductors 32, etc. of chip 1 by pressure contact or by using shrinkable hardening resin as described above, first apply pressure as in the past to connect all the bump electrodes 10 of chip 1 as shown in the figure. It is necessary to reliably contact the corresponding wiring conductor 32, but in the case of the present invention, the small-area tip portion 12 of the bump electrode 10 can be easily deformed, so the pressing force for this purpose may be lower than in the conventional case. For example, in this embodiment, the amount may be 10 to 15 g per bump electrode film.

かかる低められた加圧力によっても、チップ1内の高さ
の大なバンブ電極10の先端部12は図の符号12aで
示すように容易に変形するが、それよりも面積の犬な基
部11やその付は根部に変形は生じない。このように変
形をもっばら先端部12に生じさせるには、その面積を
小にするばかその高さを基部11よりも大にするのが望
ましく、経験上からは基部11と先端部12の高さの比
を3ニア前後に設定するのが最も望ましい。
Even with such a reduced pressing force, the tip 12 of the bump electrode 10, which has a large height inside the chip 1, is easily deformed as shown by the reference numeral 12a in the figure, but the base 11 and the tip 12, which have a smaller area, are easily deformed. No deformation occurs at the root of the attachment. In order to cause deformation to occur in the tip 12 as much as possible, it is desirable to make the area smaller and its height larger than the base 11. From experience, it is known that the height of the base 11 and the tip 12 should be increased. It is most desirable to set the ratio to around 3 near.

次にかかる段付構造のバンブ電極をチップ上に作り込む
要領例を第2図を参照して説明する。
Next, an example of how to fabricate such a bump electrode with a stepped structure on a chip will be described with reference to FIG. 2.

同図(a)はバンブ電極を作り込む前のチップの状態を
示す。通例のようにチップ1は集積回路が作り込まれる
例えばn形のエピタキシャル層ないし半導体領域1a、
p形の接合分離層1b、p形の半導体層1C等を含んで
おり、その表面を覆う二酸化ケイ素等の酸化膜2に明け
た窓部内で半導体層ICに導電接触するようにアルミ等
の配線膜3が配設され、さらにその上を窒化シリコン等
の保護膜4が覆っている。
Figure (a) shows the state of the chip before the bump electrodes are formed. As usual, the chip 1 includes, for example, an n-type epitaxial layer or semiconductor region 1a, in which an integrated circuit is fabricated.
It includes a p-type junction separation layer 1b, a p-type semiconductor layer 1C, etc., and a wiring made of aluminum or the like is placed in a window formed in an oxide film 2 made of silicon dioxide or the like covering the surface thereof so as to make conductive contact with the semiconductor layer IC. A film 3 is provided, which is further covered with a protective film 4 made of silicon nitride or the like.

配線膜3の端部上の保護膜4に明けられた開口部にバン
ブ電極が電解めっきで成長されるが、通例のようにそれ
用の1μm弱のごく薄い下地膜としてチタン等の下側下
地膜5aとパラジウムや銅の」二側下地膜5bが各開口
部内で配線膜3に導電接触するようにスパック法等で順
次被着され、図のようにこの内の上側下地膜5bのみが
バンブ電極を成長させたいパターンにフォトエツチング
され、下側下地膜5aの方はめっき電極膜として利用す
るために全面上に残される。
A bump electrode is grown by electrolytic plating in the opening made in the protective film 4 on the edge of the wiring film 3, and as is customary, a very thin base film of just under 1 μm is formed using titanium or the like on the lower side. The base film 5a and the two-side base film 5b made of palladium or copper are sequentially deposited by a spackle method or the like so as to be in conductive contact with the wiring film 3 within each opening, and only the upper base film 5b is bumped as shown in the figure. A pattern in which an electrode is to be grown is photo-etched, and the lower base film 5a is left on the entire surface to be used as a plating electrode film.

第2図(b)はバンブ電極の基部11の電解めっき工程
であって、この電解めっき用マスクとしてふつうフォト
レジスト膜21をこの例では3〜5μmの厚みに被着し
、フォトプロセスで上側下地膜5bを露出させるように
めっき用開口を明ける。バンブ電極用金属この例では金
の電解めっきは前述のように下側下地膜5aをめっき電
極として行われ、この際に基部ll用の金属がチップ1
内の全ての上側下地膜5b上に同時に成長されるが、本
発明では図示のようにこの成長高さがフォトレジスト膜
21の厚みを越える前に電解めっきを停止させて、基部
11がフォトレジスト膜21の開口壁に規制された形状
で成長され、その成長先端が末広がりの形状にならない
ようにされる。
FIG. 2(b) shows the electrolytic plating process for the base 11 of the bump electrode, in which a photoresist film 21, which is usually used as a mask for electrolytic plating, is deposited to a thickness of 3 to 5 μm in this example, and the upper and lower sides are coated using a photo process. A plating opening is opened to expose the ground film 5b. Metal for the bump electrode In this example, gold electrolytic plating is performed using the lower base film 5a as the plating electrode as described above, and at this time, the metal for the base 11 is applied to the chip 1.
However, in the present invention, as shown in the figure, electrolytic plating is stopped before the growth height exceeds the thickness of the photoresist film 21, so that the base 11 is grown on the photoresist film 21 at the same time. It is grown in a shape regulated by the opening wall of the film 21, and the growth tip is prevented from becoming flared at the end.

第2図(C)はバンブ電極の先端部12の電解めっき工
程であって、 この例では5〜7umの厚みの上側フォ
トレジスト膜22に明けた上よりは狭いめっき用開口内
にバンプ電極の先端部12用の金属を基部11に接続さ
せかつ上ど同様にこの開口壁によってあくまで規制され
た状態で成長させる。
FIG. 2(C) shows the electrolytic plating process for the tip portion 12 of the bump electrode, and in this example, the bump electrode is formed in a narrower plating opening in the upper photoresist film 22 with a thickness of 5 to 7 um. The metal for the tip portion 12 is connected to the base portion 11 and grown in a state where it is strictly regulated by the opening wall in the same manner as above.

第2図(d)はバンプ電極10の完成状態を示し、同図
(C)の状態からフォトレジスト膜21および22を剥
離した上で、下側下地膜5aを上側下地膜5bをマスク
とする化学エツチングによって除去することにより、バ
ンプ電極10が相互に分離されたこの完成状態とする。
FIG. 2(d) shows the completed state of the bump electrode 10. After removing the photoresist films 21 and 22 from the state shown in FIG. 2(C), the lower base film 5a is used as a mask and the upper base film 5b is used as a mask. Removal by chemical etching leaves the bump electrodes 10 in this completed state separated from each other.

このようにチップ1上に作り込まれるバンプ電極10で
は、第2図(ロ)と(e)におけるフォトレジスト膜2
1と22の厚みを正確に制御し、めっき用開口の面積を
フォトプロセスでそれぞれ正確に明けておくことにより
、基部11と先端部12用の金属をそれぞれ正確な高さ
と面積で成長させ、かつその側面形状をめっき用開口壁
により正確に規制できる。
In the bump electrode 10 formed on the chip 1 in this way, the photoresist film 2 in FIGS.
By accurately controlling the thicknesses of parts 1 and 22 and accurately opening the areas of the plating openings using the photo process, the metals for the base part 11 and the tip part 12 can be grown with accurate heights and areas, respectively. The side shape can be precisely controlled by the plating opening wall.

この際、フォトレジスト膜21と22のフォトプロセス
時のフォトマスク合わせをこの例では2μm程度の精度
で行うことにより、基部11と先端部12の同心度が正
確に保たれる。なお、バンプ電極10の付は根の下側下
地膜5aのサイズは基部11よりも僅かに小さくなり得
るが、先端部12よりはもちろん充分に大きい面積を有
する。
At this time, the concentricity of the base portion 11 and the tip portion 12 can be maintained accurately by aligning the photomasks during the photoprocessing of the photoresist films 21 and 22 with an accuracy of about 2 μm in this example. Note that the size of the base film 5a under the root of the bump electrode 10 may be slightly smaller than the base 11, but of course has a sufficiently larger area than the tip 12.

次に段付構造のバンプ電極をチップ上に作り込む他の要
領例を第5図を参照して説明する。
Next, another example of how to form stepped bump electrodes on a chip will be described with reference to FIG.

同図(a)はバンプ電極を作り込む前のチップの状態を
示す。チップ1はS1ウエハあるいはセラミックス、ガ
ラス等の基板からなり、その表面に二酸化ケイ素等の酸
化膜2.アルミ等の配線膜3が配設され、さらにその上
を窒化シリコン等の保護膜4が覆っている。
Figure (a) shows the state of the chip before bump electrodes are formed. The chip 1 consists of an S1 wafer or a substrate made of ceramics, glass, etc., and has an oxide film 2, such as silicon dioxide, on its surface. A wiring film 3 made of aluminum or the like is provided, and further covered with a protective film 4 made of silicon nitride or the like.

配線膜3上の保護膜4に明けられた開口部にバンプ電極
が電解めっきで成長されるが、通例のようにそれ用の1
μm弱のごく薄い下地膜として多層の下地膜5が開口部
内で配線膜3に導電接触するようにスパック法等で被着
される。
Bump electrodes are grown by electrolytic plating in the openings made in the protective film 4 on the wiring film 3.
A multilayer base film 5 as a very thin base film of a little less than .mu.m is deposited by spuck method or the like so as to be in conductive contact with the wiring film 3 within the opening.

次にフォトレジスト膜23を被着し、フォトマスク40
を介して光Qで露光し、フォトマスク透明部41により
フォトマスク露光部51を得る。このフォトマスク透明
部41の大きさは得ようとするバンプの大きさに応じて
決定される(第5図Q)))。続いてフォトレジスト膜
24を被着し、前記フォトマスク透明部41より小さな
フォトマスク透明部43を有するフォトマスク42を介
して光Qで露光し、フォトマスク透明部43によりフォ
トマスク露光部52を得る(第5図(C))。次に前記
フォトレジスト膜23゜24を同時に現像するとフォト
マスクパターニング部61.62が形成される(第5図
cd))。続いて電解めっきを行い、めっきの成長高さ
がフォトレジスト膜24の厚みを越える前に電解めっき
を停止させる。その後フォトレジスト膜23.24を除
去した上で、不要のバンプ下地金属膜5を除去すること
により、バンプ電極10が得られる(第5図(e))。
Next, a photoresist film 23 is deposited, and a photomask 40 is
A photomask exposed portion 51 is obtained using the photomask transparent portion 41. The size of the photomask transparent portion 41 is determined depending on the size of the bump to be obtained (FIG. 5Q)). Subsequently, a photoresist film 24 is deposited and exposed to light Q through a photomask 42 having a photomask transparent part 43 smaller than the photomask transparent part 41, and the photomask exposed part 52 is exposed by the photomask transparent part 43. (Figure 5(C)). Next, the photoresist films 23 and 24 are simultaneously developed to form photomask patterning portions 61 and 62 (FIG. 5c)). Subsequently, electrolytic plating is performed, and the electrolytic plating is stopped before the growth height of the plating exceeds the thickness of the photoresist film 24. Thereafter, the photoresist films 23 and 24 are removed, and then the unnecessary bump underlying metal film 5 is removed to obtain the bump electrode 10 (FIG. 5(e)).

このようにバンプ電極を形成することで、めっき工程が
1度で済み、工程の簡略化が図れ、かつばらつき要因の
多い工程をなくすことができる。
By forming the bump electrodes in this manner, the plating process can be performed only once, simplifying the process, and eliminating processes that cause many variations.

さらにめっき工程が1度であるので、バンプ電極10の
基部11と先端部12との間にごみが付着することがな
く、バンプ電極10の信頼性を損なうことがない。
Furthermore, since the plating process is performed only once, there is no possibility that dust will adhere between the base portion 11 and the tip portion 12 of the bump electrode 10, and the reliability of the bump electrode 10 will not be impaired.

〔発明の効果〕〔Effect of the invention〕

以上のとおり本発明では、集積回路装置のチップ表面に
突設されるバンプ電極を同心状に積み重なった基部と先
端部からなる段付構造に構成し、先端部の面積を基部の
面積の2分の1以下に形成したので、チップの実装時に
バンプ電極に加圧力が掛かったとき面積の小なその先端
部のみを容易に変形させて、従来の2分の1以下の加圧
力でチップ内のすべてのバンプ電極を接続相手方と確実
に接触させながら、バンプ電極の基部特に付は根部やそ
の下側のチップ表面部に過大な圧力が掛かるのを有効に
防止することができ、これにより従来の露状バンプ電極
のように実装時にその付は根部が外れたりチップが損傷
したりするトラブルを根絶することができる。
As described above, in the present invention, the bump electrodes protruding from the chip surface of an integrated circuit device are configured in a stepped structure consisting of a concentrically stacked base and a tip, and the area of the tip is half the area of the base. Since the bump electrode is formed to have a thickness of less than 1, when pressure is applied to the bump electrode during chip mounting, only the small tip of the bump electrode is easily deformed, and the inside of the chip can be easily deformed with less than half the pressure of conventional bump electrodes. While ensuring that all bump electrodes are in contact with their connection partners, it is possible to effectively prevent excessive pressure from being applied to the base of the bump electrode, especially the base of the bump electrode, and the chip surface underneath. It is possible to eliminate problems like dew bump electrodes, such as the root part coming off or chip damage during mounting.

また、本発明によるバンプ電極では、実装時やチップの
運搬時に誤って物がその先端に触れないしは当たっても
従来のように簡単に外れてしまうおそれがなく、本発明
の実施によりチップの取り扱いが従来より格段に容易に
なる。
In addition, with the bump electrode according to the present invention, even if an object accidentally touches or hits the tip during mounting or transporting the chip, there is no risk of it coming off easily unlike in the past, and the implementation of the present invention makes it easier to handle the chip. Much easier than before.

かかる特徴をもつ本発明は、数十μm以下のサイズの小
形バンプ電極が多数個設けられる高集積度のフリップチ
ップに適用して特に効果が高く、実装時のトラブル発生
をほぼ根絶し、その外部接続上の信頼性をも向上できる
The present invention having such characteristics is particularly effective when applied to highly integrated flip chips in which a large number of small bump electrodes with a size of several tens of micrometers or less are provided. Connection reliability can also be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図が本発明に関し、第1図は本発明に
よるバンプ電極をそれが作り込まれた集積回路装置チッ
プの実装状態で例示する側面図、第2図はバンプ電極を
チップに作り込む要領例を主な工程ごとの状態で示す断
面図、第3図、第4図は従来技術に関し、第3図は従来
のバンプ電極の断面図、第4図はそれが作り込まれた集
積回路装置チップの実装状態の側面図、第5図はバンプ
電極をチップに作り込む他の要領例を主な工程ごとの状
態で示す断面図である。これらの図において、
1 and 2 relate to the present invention, FIG. 1 is a side view illustrating a bump electrode according to the present invention in a mounted state of an integrated circuit device chip in which the bump electrode is built, and FIG. A cross-sectional view showing an example of how to create a bump electrode in each main process. Figures 3 and 4 relate to the conventional technology. Figure 3 is a cross-sectional view of a conventional bump electrode, and Figure 4 shows how it is manufactured. FIG. 5 is a side view of the integrated circuit device chip in a mounted state. FIG. 5 is a cross-sectional view showing each main step of another example of how bump electrodes are formed on the chip. In these figures,

Claims (1)

【特許請求の範囲】 1)集積回路装置の外部接続用にそのチップ表面から突
設される金属のバンプ電極であって、同心状に積み重な
った基部と先端部からなる段付構造をもち、先端部の面
積が基部の面積の2分の1以下に形成されたことを特徴
とする集積回路装置用バンプ電極。 2)チップの表面に配線膜と該配線膜上に開口部を有す
る保護膜を被着後、該開口部で前記配線膜に接触するバ
ンプ電極を形成する製造方法において、前記保護膜上に
第1のフォトレジスト膜形成後、第1の露光により前記
配線膜の開口部上に面積大な第1の露光部を形成し、さ
らに第2のフォトレジスト膜を形成後第2の露光により
前記第1の露光部上に面積小な第2の露光部を形成し、
該第1、第2のフォトレジスト膜を同時に現像を行い、
しかる後電解めっきによりバンプ電極を形成することを
特徴とする集積回路装置用バンプ電極の製造方法。 3)請求項2記載のバンプ電極が同心状に積み重なった
基部と先端部からなる段付構造を有することを特徴とす
る集積回路装置用バンプ電極。
[Scope of Claims] 1) A metal bump electrode protruding from the chip surface of an integrated circuit device for external connection, which has a stepped structure consisting of a concentrically stacked base and a tip. 1. A bump electrode for an integrated circuit device, characterized in that the area of the portion is one-half or less of the area of the base. 2) A manufacturing method in which a wiring film and a protective film having an opening on the wiring film are deposited on the surface of the chip, and then a bump electrode is formed in contact with the wiring film at the opening. After forming the first photoresist film, a first exposure part with a large area is formed on the opening of the wiring film by a first exposure, and after forming a second photoresist film, a second exposure part is formed on the opening of the wiring film. forming a second exposed portion with a small area on the first exposed portion;
Developing the first and second photoresist films simultaneously,
1. A method for manufacturing a bump electrode for an integrated circuit device, which comprises forming the bump electrode by subsequent electrolytic plating. 3) A bump electrode for an integrated circuit device, wherein the bump electrode according to claim 2 has a stepped structure consisting of a base portion and a tip portion concentrically stacked.
JP24562990A 1989-09-14 1990-09-14 Bump electrode for integrated circuit and manufacture thereof Pending JPH03174731A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-238692 1989-09-14
JP23869289 1989-09-14

Publications (1)

Publication Number Publication Date
JPH03174731A true JPH03174731A (en) 1991-07-29

Family

ID=17033879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24562990A Pending JPH03174731A (en) 1989-09-14 1990-09-14 Bump electrode for integrated circuit and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH03174731A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5708283A (en) * 1994-10-20 1998-01-13 Hughes Aircraft Flip chip high power monolithic integrated circuit thermal bumps
US5773897A (en) * 1997-02-21 1998-06-30 Raytheon Company Flip chip monolithic microwave integrated circuit with mushroom-shaped, solder-capped, plated metal bumps

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5708283A (en) * 1994-10-20 1998-01-13 Hughes Aircraft Flip chip high power monolithic integrated circuit thermal bumps
US5773897A (en) * 1997-02-21 1998-06-30 Raytheon Company Flip chip monolithic microwave integrated circuit with mushroom-shaped, solder-capped, plated metal bumps

Similar Documents

Publication Publication Date Title
US7662670B2 (en) Manufacturing method of semiconductor device
US5466635A (en) Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US6248962B1 (en) Electrically conductive projections of the same material as their substrate
JPH10321631A (en) Semiconductor device and its manufacture
KR20030084707A (en) Semiconductor device and manufacturing method thereof
JP2653179B2 (en) Method of manufacturing bump electrode for integrated circuit device
US6649507B1 (en) Dual layer photoresist method for fabricating a mushroom bumping plating structure
JP2001144125A (en) Semiconductor device and method of forming the semiconductor device
JPH07201864A (en) Projection electrode formation method
CN100514590C (en) Method and structure for preventing soldering pad stripping
JP2830351B2 (en) Semiconductor device connection method
US7112881B2 (en) Semiconductor device
JPH03174731A (en) Bump electrode for integrated circuit and manufacture thereof
JPH0357617B2 (en)
JP3877700B2 (en) Semiconductor device and manufacturing method thereof
JPH0922912A (en) Semiconductor device and manufacture thereof
JPH0766207A (en) Surface mount device, manufacture thereof, and soldering method
JP2005294875A (en) Semiconductor device and manufacturing method therefor
KR100343454B1 (en) Wafer level package
JP2001077142A (en) Semiconductor device and manufacture of it
JPH03101233A (en) Electrode structure and its manufacture
JP3019065B2 (en) Semiconductor device connection method
JPH05283412A (en) Semiconductor device and its manufacture
KR100233866B1 (en) The structure of semiconductor chip for flip-chip and its manufacturing method
JP3351878B2 (en) Semiconductor device and method of manufacturing the same