JPH03173475A - Compound semiconductor device and its manufacture - Google Patents
Compound semiconductor device and its manufactureInfo
- Publication number
- JPH03173475A JPH03173475A JP31392589A JP31392589A JPH03173475A JP H03173475 A JPH03173475 A JP H03173475A JP 31392589 A JP31392589 A JP 31392589A JP 31392589 A JP31392589 A JP 31392589A JP H03173475 A JPH03173475 A JP H03173475A
- Authority
- JP
- Japan
- Prior art keywords
- film
- compound semiconductor
- deposited
- eliminated
- window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 150000001875 compounds Chemical class 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000010408 film Substances 0.000 claims abstract description 50
- 229910052717 sulfur Inorganic materials 0.000 claims abstract description 19
- 239000011593 sulfur Substances 0.000 claims abstract description 19
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000010409 thin film Substances 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 claims description 19
- 239000000203 mixture Substances 0.000 claims description 7
- 239000011261 inert gas Substances 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 17
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 abstract description 6
- 229910045601 alloy Inorganic materials 0.000 abstract description 4
- 239000000956 alloy Substances 0.000 abstract description 4
- 238000006116 polymerization reaction Methods 0.000 abstract description 4
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 238000000034 method Methods 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000000354 decomposition reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- LZZYPRNAOMGNLH-UHFFFAOYSA-M Cetrimonium bromide Chemical compound [Br-].CCCCCCCCCCCCCCCC[N+](C)(C)C LZZYPRNAOMGNLH-UHFFFAOYSA-M 0.000 description 1
- 101100130497 Drosophila melanogaster Mical gene Proteins 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 101100345589 Mus musculus Mical1 gene Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 150000003463 sulfur Chemical class 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
＾Ｓを含む化合物半導体のショットキー接合の構成に関
し、
接合界面の欠陥準位を低減することによってショットキ
ー接合特性の向上を図ることを目的とし、砒素（Ａｓ）
を含む化合物半導体上にイオウ（Ｓ）を含む薄膜を介し
て導電膜が形成されてなるショットキー接合を有するよ
うに構成し、不活性ガスプラズマによって分解されたＳ
Ｈ２ガス、ＳＦ＆ガスあるいはそれらの混合ガスを前記
化合物半導体上に移送し付着させたプラズマ重合膜によ
って前記イオウを含む薄膜を形成する工程を有するよう
に構成する。[Detailed Description of the Invention] [Summary] Regarding the structure of a Schottky junction of a compound semiconductor containing ^S, the purpose of improving the Schottky junction characteristics by reducing the defect levels at the junction interface is to (As)
The structure has a Schottky junction in which a conductive film is formed on a compound semiconductor containing sulfur (S) via a thin film containing sulfur (S), and S decomposed by an inert gas plasma.
The method includes a step of transferring H2 gas, SF&gas, or a mixture thereof onto the compound semiconductor and forming a thin film containing sulfur using a plasma polymerized film deposited on the compound semiconductor.
本発明は化合物半導体装置に係り、特に＾Ｓを含む化合
物半導体のショットキー接合の構成に関する。The present invention relates to a compound semiconductor device, and particularly to a Schottky junction configuration of a compound semiconductor containing ^S.
化合物半導体素子はシリコン素子とは異なる種々の優れ
た特徴を持つことが知られており、その実用化が望まれ
ている。しかし、化合物半導体には化学量論的組成比か
らのずれによる欠陥が生じ易くこれが素子特性の均一性
、再現性の向上を阻む原因となっており、その解決を図
ることが必要である。Compound semiconductor devices are known to have various excellent features different from silicon devices, and their practical use is desired. However, compound semiconductors are prone to defects due to deviations from the stoichiometric composition ratio, which hinders improvements in the uniformity and reproducibility of device characteristics, and it is necessary to solve this problem.
化合物半導体における化学量論的組成比からのずれは、
特に表面あるいは界面において生じ易く、これに起因す
る欠陥準位は通常バンドギャップの深い位置に生じる。The deviation from the stoichiometric composition ratio in compound semiconductors is
Defect levels are particularly likely to occur at the surface or interface, and the resulting defect levels usually occur at a deep position in the band gap.
一般に、Ａｓを含む化合物半導体の表面ではＡｓ過剰と
なり易く、例えばＧａＡｓ半導体では、本来Ｇａが占め
るべき位置を＾Ｓが代わって占有することによりＡｓ過
剰となり、これによって生じた欠陥準位はＡｓｃ、アン
チサイトと称され、伝導帯の底からおよそ０．７５ ｅ
Ｖの位置に生じることが知られている。また、このＡｓ
ａａアンチサイトによる準位密度は表面付近で凡そ１０
’ ”ｃｏ＋−”ｅＶ−’と非常に大きいことが知ら
れており、これによって表面におけるキャリヤの再結合
速度が大きくなり、キャリヤの寿命を短くして素子特性
の劣化をもたらす。In general, the surface of a compound semiconductor containing As tends to have an excess of As. For example, in a GaAs semiconductor, the position that should normally be occupied by Ga is replaced by ^S, resulting in an excess of As, and the resulting defect levels are Asc, It is called an antisite and is approximately 0.75 e from the bottom of the conduction band.
It is known that this occurs at the V position. Also, this As
The level density due to aa antisites is approximately 10 near the surface.
It is known that the recombination rate of carriers on the surface is large, shortening the lifetime of the carriers and deteriorating the device characteristics.
一方、ＧａＡｓおよびＡｌＧａＡｓからなるバイポーラ
トランジスタをＮａ 、Ｓ・９ＨｚＯを含む溶液で処理
することによりトランジスタの増幅率が増加することが
報告されている（ Ｃ，Ｊ、５ａｎｄｒｏｆｆ ｅｔ、
ａｌ、”Ｄｒａｍａｔｉｃｅｎｈａｎｃｅｍｅｎｔ ｉ
ｎ ｔｈｅ ｇａｉｎ ｏｆ ａ ＧａＡｓ／ＡＩＧａ
Ａｓｈｅｔｅｒｏｓｔｒｕｃｔｕｒｅ ｂｉｐｏｌａｒ
ｔｒａｎｓｉｓｔｏｒ ｂｙ ｓｕｒｆａｃｅｃｈｅ
ｍｉｃａｌ ｐａｓｓｉｖａｔｉｏｎ” Ａｐｐｌ、Ｐ
ｈｙｓ、Ｌｅｔｔ、５１＋１＋６１９８７）、このよう
な特性の改善は、ＧａＡｓおよびＡｌＧａＡｓの界面に
おける欠陥準位がイオウ（Ｓ）を含む溶液処理によって
低減されたことによるものと考えられる。しかしながら
、上記の処理はトランジスタ製作工程完了後に行ってい
るため、その効果が不安定であり素子特性は数時間ある
いは数日で元に戻ってしまう。On the other hand, it has been reported that the amplification factor of a bipolar transistor made of GaAs and AlGaAs is increased by treating it with a solution containing Na, S.
al, “Dramatic enhancement i
n the gain of a GaAs/AIGa
Asheterostructure bipolar
transistor by surfaceche
“mical passivation” Appl, P
hys, Lett, 51+1+61987), such improvement in properties is considered to be due to reduction of defect levels at the interface between GaAs and AlGaAs by treatment with a solution containing sulfur (S). However, since the above process is performed after the transistor manufacturing process is completed, its effect is unstable and the device characteristics return to their original state in a few hours or days.
化合物半導体のショットキー接合はショットキーダイオ
ードあるいはショットキーゲートトランジスタ等の素子
を構成する重要な要素であるが、化合物半導体の表面あ
るいは界面に形成されるため、前述したような化学量論
的組成比からのずれの影響を受けやすい。特に、Ａｓを
含む化合物半導体では、過剰なＡｓによって生じた欠陥
の影響を受けてショットキー接合におけるキャリヤの寿
命が理論値に比べて−著しく短くなるとともに、その場
所的な不均一性も著しくなる。そのため、ショットキー
ゲートトランジスタにおいてはその増幅特性を劣化させ
たり、しきい値電圧の変動をもたらす等の問題を引き起
こすが、従来はこれを防ぐ有効な対策がなかった。Schottky junctions in compound semiconductors are important elements constituting devices such as Schottky diodes or Schottky gate transistors, but because they are formed on the surface or interface of compound semiconductors, they do not have the same stoichiometric composition as described above. susceptible to deviations from In particular, in compound semiconductors containing As, the lifetime of carriers in Schottky junctions becomes significantly shorter than the theoretical value due to the effects of defects caused by excess As, and the local non-uniformity becomes significant. . This causes problems in Schottky gate transistors, such as deterioration of their amplification characteristics and fluctuations in threshold voltage, but conventionally there has been no effective measure to prevent this.
そこで本発明は、Ａｓを含む化合物半導体の欠陥準位を
低減することによってショットキー接合特性の向上を図
ることを目的とする。Therefore, an object of the present invention is to improve the Schottky junction characteristics by reducing the defect levels of a compound semiconductor containing As.
上記課題の解決は、砒素（Ａｓ）を含む化合物半導体上
にイオウ（Ｓ）を含む薄膜を介して導電膜が形成されて
なるショットキー接合を有することを特徴とする化合物
半導体装置、あるいは、不活性ガスプラズマによって分
解されたＳＨ，ガス、ＳＦ６ガスあるいはそれらの混合
ガスを前記化合物半導体上に移送し付着させたプラズマ
重合膜によって前記イオウを含む薄膜を形成する工程を
有することを特徴とする前記化合物半導体装置の製造方
法によって達成される。The solution to the above problem is to provide a compound semiconductor device characterized by having a Schottky junction in which a conductive film is formed on a compound semiconductor containing arsenic (As) via a thin film containing sulfur (S), or a non-conductive semiconductor device. The method further comprises a step of transferring SH, gas, SF6 gas, or a mixture thereof decomposed by active gas plasma onto the compound semiconductor and forming the thin film containing sulfur using a plasma polymerized film deposited on the compound semiconductor. This is achieved by a method for manufacturing a compound semiconductor device.
本発明では、Ａｓを含む化合物半導体の表面にイオウを
含む薄膜が形成されており、このイオウが欠陥を不活性
化してキャリヤの再結合を防ぎ、ショットキー接合特性
の向上、安定化をもたらすものである。イオウが欠陥を
不活性化する理由は、現在の所かならずしも明らかでな
いものの、イオウ（Ｓ）が過剰なＡｓによって生じた欠
陥中の＾Ｓと結合してこのような欠陥を減少させる一方
、新たに形成されたＡｓ−５結合がキャリヤの再結合中
心としての機能を有しないためと考えられる。In the present invention, a thin film containing sulfur is formed on the surface of a compound semiconductor containing As, and this sulfur inactivates defects and prevents carrier recombination, thereby improving and stabilizing Schottky junction characteristics. It is. Although the reason why sulfur inactivates defects is not entirely clear at present, sulfur (S) combines with ^S in defects caused by excess As, reducing such defects while creating new This is considered to be because the formed As-5 bond does not function as a carrier recombination center.
また、イオウを含む薄膜は、一般にイオウを含むガスを
不活性ガスプラズマ中で分解したものを半導体表面に付
着させて得られるが、この工程において半導体表面を不
活性ガスプラズマ中に直接さらした場合には、不活性ガ
ス中の高エネルギーイオンが半導体表面を衝撃して別の
新たな欠陥を生じさせる。そこで、半導体表面から離れ
た場所においてＳＨ，ガス、ＳＦ６ガスあるいはそれら
の混合ガスを不活性ガスによって分解し、これを半導体
表面に移送してプラズマ重合膜として付着させると、新
たな欠陥が発生する確率を小さくすることができる。Additionally, a thin film containing sulfur is generally obtained by decomposing a sulfur-containing gas in an inert gas plasma and attaching it to the semiconductor surface, but if the semiconductor surface is directly exposed to the inert gas plasma in this process, In this process, high-energy ions in an inert gas bombard the semiconductor surface, creating new defects. Therefore, if SH, gas, SF6 gas, or a mixture thereof is decomposed using an inert gas at a location away from the semiconductor surface, and then transferred to the semiconductor surface and deposited as a plasma polymerized film, new defects will occur. The probability can be reduced.
〔実施例］
第１図は、ＧａＡｓを用いたショットキーゲートトラン
ジスタの製作に本発明を適用した例を示す工程断面図で
ある。[Example] FIG. 1 is a process sectional view showing an example in which the present invention is applied to manufacturing a Schottky gate transistor using GaAs.
同図（ａ）に示すように、半絶縁性ＧａＡｓ基板１上に
レジスト膜２を形成し素子領域を窓開けした後、これを
マスクとしてＳｉイオンの注入を行い、ｎ型チャネル領
域３を形成する。As shown in FIG. 5(a), a resist film 2 is formed on a semi-insulating GaAs substrate 1 to open a window in the element region, and then Si ions are implanted using this as a mask to form an n-type channel region 3. do.
ついでレジスト膜２を除去した後同図（ｂ）に示すよう
に、ＣＶＤ法によりシリコン窒化膜４を堆積する。続い
てレジスト膜５を全面に塗布し、この上にＣＶＤ法によ
りシリコン酸化膜６を堆積しソース／ドレイン領域とな
る部分を窓開けする。続いて、窓開けされたシリコン酸
化膜６をマスクにレジスト膜５の過剰露光・現像処理を
行う。さらに、シリコン酸化膜６をマスクにして加速電
圧３００ＫｅＶ、 ドーズ１６ ＸＩＯ”ｃｍ−２の
条件でシリコン窒化膜４を通して半絶縁性ＧａＡｓ基板
１内にＳイオンの注入を行い、ｎ゛型ソース／ドレイン
領域７を形成する。続いてＣＶＤ法により全面にシリコ
ン酸化膜８を堆積する。After removing the resist film 2, a silicon nitride film 4 is then deposited by CVD, as shown in FIG. 2(b). Subsequently, a resist film 5 is applied to the entire surface, and a silicon oxide film 6 is deposited thereon by the CVD method, and windows are opened in the portions that will become the source/drain regions. Subsequently, using the opened silicon oxide film 6 as a mask, the resist film 5 is subjected to overexposure and development processing. Furthermore, using the silicon oxide film 6 as a mask, S ions are implanted into the semi-insulating GaAs substrate 1 through the silicon nitride film 4 under the conditions of an acceleration voltage of 300 KeV and a dose of 16 A region 7 is formed.Subsequently, a silicon oxide film 8 is deposited over the entire surface by CVD.
ついで同図（Ｃ）に示すように、リフトオフ法を用いて
レジスト膜５とこの上のシリコン酸化膜６および８を除
去する。Then, as shown in FIG. 2C, the resist film 5 and the silicon oxide films 6 and 8 thereon are removed using a lift-off method.
ついで同図（ｄ）に示すように、レジスト膜９を形成し
ソース／ドレイン領域７上を窓開けした後、これをマス
クにしてシリコン酸化膜８およびシリコン窒化膜４を選
択的にエツチング除去し、さらにこの上にＡｕＧｅ合金
膜ｌＯをスパッタ蒸着法により堆積する。Next, as shown in FIG. 4(d), a resist film 9 is formed to open a window over the source/drain region 7, and then, using this as a mask, the silicon oxide film 8 and the silicon nitride film 4 are selectively etched away. Further, an AuGe alloy film 1O is deposited thereon by sputter deposition.
ついで同図（ｅ）に示すように、リフトオフ法を用いて
レジスト膜９とこの上のＡｕＧｅ合金膜１０を除去する
。Then, as shown in FIG. 2E, the resist film 9 and the AuGe alloy film 10 thereon are removed using a lift-off method.
ついで同図（ｆ）に示すように、チャネル領域３上のシ
リコン窒化膜４を選択的にエツチング除去した後、全面
にイオウを含むプラズマ重合膜１１を以下のような方法
で形成する。Next, as shown in FIG. 2F, after the silicon nitride film 4 on the channel region 3 is selectively etched away, a plasma polymerized film 11 containing sulfur is formed on the entire surface by the following method.
第２図はイオウを含む薄膜を形成するために用いたプラ
ズマ重合装置である。このプラズマ重合装置はプラズマ
室１４と試料室１５とに別れており、まず、プラズマ室
１４にバルブ１６を通してＡｒガスを導入し、これをコ
イル１７によってプラズマ化する。FIG. 2 shows a plasma polymerization apparatus used to form a thin film containing sulfur. This plasma polymerization apparatus is divided into a plasma chamber 14 and a sample chamber 15. First, Ar gas is introduced into the plasma chamber 14 through a valve 16, and is turned into plasma by a coil 17.
コイル１７にはインピーダンス整合装置１８を通して高
周波電源１９より周波数１３．５６ ＭＨｚ 、電力３
０Ｗを印加する。次にバルブ２０を通して導入されたＳ
ＨｚガスとＳＦ６ガスの混合ガスを、以上のようにして
形成されたＡｒプラズマによって分解し、この分解生成
物を試料室１５内へ移送し、試料ホルダー２１に固定さ
れた試料、即ちＧａＡｓ基板１上に導きこの上に付着さ
せる。この際、試料ホルダー２１を水冷することによっ
てＧａＡｓＪＪ板温度の上昇を防ぐ。以上のことから明
らかなように、本装置においては、ＳＨｔガスとＳＦ、
ガスは、コイル１７に供給された高密度の電力によって
直接分解することな（Ａｒガスプラズマによって間接的
に分解する。そのため分解生成物にはＳを含むガス分子
構造の多くが分解されずに含まれている。そして、この
分解生成物が低温のＧａＡｓ基板１上に付着し、Ｓを含
むガス分子からなるプラズマ重合膜となる。この付着過
程においてＧａＡｓ基板１の表面付近には高エネルギー
イオンが存在しない。そのため、膜の付着に伴う新たな
欠陥が生じることはない。The coil 17 is supplied with a frequency of 13.56 MHz and a power of 3 from a high frequency power source 19 through an impedance matching device 18.
Apply 0W. Then S introduced through valve 20
The mixed gas of Hz gas and SF6 gas is decomposed by the Ar plasma formed as described above, and this decomposition product is transferred into the sample chamber 15, and the sample fixed on the sample holder 21, that is, the GaAs substrate 1 Guide it upwards and attach it on top. At this time, the sample holder 21 is cooled with water to prevent the temperature of the GaAs JJ plate from increasing. As is clear from the above, in this device, SHt gas and SF,
The gas is not decomposed directly by the high-density electric power supplied to the coil 17 (it is decomposed indirectly by the Ar gas plasma. Therefore, the decomposition products contain most of the gas molecular structure containing S without being decomposed. This decomposition product then adheres to the low-temperature GaAs substrate 1, forming a plasma polymerized film consisting of gas molecules containing S. During this adhesion process, high-energy ions are deposited near the surface of the GaAs substrate 1. Therefore, no new defects are generated due to film adhesion.
以上のようにしてイオウを含むプラズマ重合膜１１を形
成した後、この上にＡｌ膜を堆積し第１図（局に示すよ
うに、パターニングしてショットキー電極１２を形成す
る。After forming the plasma polymerized film 11 containing sulfur as described above, an Al film is deposited thereon and patterned to form a Schottky electrode 12 as shown in FIG.
なお、本実施例で述べたＧａＡｓ以外のＡｓを含む化合
物半導体、例えば、ＩｎＧａＡｓ、 ＡｌＧａＡｓ等に
対しても本発明により良好なショットキー接合特性を得
ることができる。Note that good Schottky junction characteristics can also be obtained by the present invention for compound semiconductors containing As other than GaAs described in this embodiment, such as InGaAs and AlGaAs.
以上のように本発明によれば、過剰なＡｓによる欠陥準
位を低減することができるため、ショットキーダイオー
ドあるいはショットキーゲートトランジスタ等のショッ
トキー接合を利用するＡｓを含む化合物半導体素子の特
性向上、およびその均一性、再現性の向上に有益である
。As described above, according to the present invention, defect levels caused by excessive As can be reduced, so that characteristics of As-containing compound semiconductor devices using Schottky junctions such as Schottky diodes or Schottky gate transistors can be improved. , and is useful for improving its uniformity and reproducibility.
第１図は本発明の実施例を示す工程断面図、第２図は本
発明の実施例に用いたプラズマ重合装置である。
図において、
１は半絶縁性ＧａＡｓ基板、
２．５．９はレジスト膜、
３はチャネル領域、
４はシリコン窒化膜、
６．８はシリコン酸化膜、
７はソース／ドレイン傾城、
１０はＡｕＧｅ合金、
１１はイオウを含むプラズマ重合膜、
１２はショットキー電極、
１４はプラズマ室、
１５は試料室、
１６．２０はバルブ、
１７はコイル、
１８はインピーダンス整合装置、
１９は高周波電源、
２１は試料ホルダー
２２は真空計、
１ １ １ １
杢発θ目／′）実袷例乞示す工程餠面記第 １図（イの
１）
本発明０１演り１１乞示イ工イ吋面図
第 １ 図 （イの−２）FIG. 1 is a process sectional view showing an example of the present invention, and FIG. 2 is a plasma polymerization apparatus used in an example of the present invention. In the figure, 1 is a semi-insulating GaAs substrate, 2.5.9 is a resist film, 3 is a channel region, 4 is a silicon nitride film, 6.8 is a silicon oxide film, 7 is a source/drain slope, 10 is an AuGe alloy , 11 is a plasma polymerized film containing sulfur, 12 is a Schottky electrode, 14 is a plasma chamber, 15 is a sample chamber, 16.20 is a valve, 17 is a coil, 18 is an impedance matching device, 19 is a high frequency power supply, 21 is a sample The holder 22 is a vacuum gauge, and the holder 22 is a vacuum gauge. Figure (A-2)
Claims (2)
）を含む薄膜を介して導電膜が形成されてなるショット
キー接合を有することを特徴とする化合物半導体装置。(1) Sulfur (S) on a compound semiconductor containing arsenic (As)
) A compound semiconductor device characterized by having a Schottky junction in which a conductive film is formed through a thin film comprising:
ガス、ＳＦ＿６ガスあるいはそれらの混合ガスを前記化
合物半導体上に移送し付着させたプラズマ重合膜によっ
て前記イオウを含む薄膜を形成する工程を有することを
特徴とする請求項（１）記載の化合物半導体装置の製造
方法。(2) SH_2 decomposed by inert gas plasma
The compound semiconductor device according to claim 1, further comprising the step of forming the sulfur-containing thin film using a plasma polymerized film that is deposited by transferring a gas, SF_6 gas, or a mixture thereof onto the compound semiconductor. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31392589A JPH03173475A (en) | 1989-12-01 | 1989-12-01 | Compound semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31392589A JPH03173475A (en) | 1989-12-01 | 1989-12-01 | Compound semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03173475A true JPH03173475A (en) | 1991-07-26 |
Family
ID=18047175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31392589A Pending JPH03173475A (en) | 1989-12-01 | 1989-12-01 | Compound semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03173475A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03261147A (en) * | 1990-03-12 | 1991-11-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device, and method and apparatus for manufacturing semiconductor device |
-
1989
- 1989-12-01 JP JP31392589A patent/JPH03173475A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03261147A (en) * | 1990-03-12 | 1991-11-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device, and method and apparatus for manufacturing semiconductor device |
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