JPH03173430A - Formation of wiring - Google Patents
Formation of wiringInfo
- Publication number
- JPH03173430A JPH03173430A JP31362689A JP31362689A JPH03173430A JP H03173430 A JPH03173430 A JP H03173430A JP 31362689 A JP31362689 A JP 31362689A JP 31362689 A JP31362689 A JP 31362689A JP H03173430 A JPH03173430 A JP H03173430A
- Authority
- JP
- Japan
- Prior art keywords
- film
- etched
- resist
- layer
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 29
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000001312 dry etching Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 32
- 239000002356 single layer Substances 0.000 claims description 9
- 238000002844 melting Methods 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- 230000007261 regionalization Effects 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 150000002736 metal compounds Chemical class 0.000 claims description 2
- 229910000838 Al alloy Inorganic materials 0.000 claims 1
- 239000007795 chemical reaction product Substances 0.000 claims 1
- 240000007711 Peperomia pellucida Species 0.000 abstract description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 229910052593 corundum Inorganic materials 0.000 abstract description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 241000283973 Oryctolagus cuniculus Species 0.000 description 25
- 210000005069 ears Anatomy 0.000 description 24
- 230000001681 protective effect Effects 0.000 description 9
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 102100023170 Nuclear receptor subfamily 1 group D member 1 Human genes 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、多層又は単層レジスト膜を用いたドライエツ
チング工程を含む配線の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a method for forming wiring including a dry etching process using a multilayer or single layer resist film.
従来の技術
第４図に示すのは、従来の多層レジストを用いたドライ
エツチング工程を含む、配線の形成方法の一例である。BACKGROUND OF THE INVENTION FIG. 4 shows an example of a conventional method for forming wiring, including a dry etching process using a multilayer resist.
図中２０１はＳｉ基板、２０２は５ｉｎ２膜、２０３は
ＡＩ！Ｓｉ膜、２０４は下層レジスト、２０５はＳＯＧ
の中間層、２０６は上層の電子ビーム（以下ＥＢと書く
）用レジスト、２０７はＥＢ露光でパターン出しした。In the figure, 201 is a Si substrate, 202 is a 5in2 film, and 203 is an AI! Si film, 204 is lower resist, 205 is SOG
The intermediate layer 206 is an upper layer resist for electron beam (hereinafter referred to as EB), and the pattern 207 is formed by EB exposure.
上層のＥＢレジスト２０６の残しの部分、２０８は上層
のＥＢレジストパターン２０７をマスクにしてエツチン
グした、ＳＯＧの中間層２０５の残しの部分、２０９は
ＳＯＧの中間層パターン２０８をマスクにしてエツチン
グした、下層レジスト２０４の残しの部分、２１０はＳ
ＯＧの中間層パターン２０８を除去する際に、下層レジ
ストパターン２０９の側壁に形成されたラビットイヤー
１．２１１は下りレジストパターン２０９をマスクにし
てエツチングした、ＡｆｆＳｉ膜２０３の残しの部分、
２１２はＡｆｆＳ ｉ膜のパターン２１１を形成する際
に、ＡｌＳｉ膜のパターン２１１及び下層レジストパタ
ーン２０９の側壁に形成されたラビットイヤー２．２１
３は表面保護膜、２１４はラビットイヤーによる表面保
護膜の盛り上がりである。The remaining portion of the upper layer EB resist 206, 208, was etched using the upper layer EB resist pattern 207 as a mask.The remaining portion of the SOG intermediate layer 205, 209, was etched using the SOG intermediate layer pattern 208 as a mask. The remaining portion of the lower resist 204, 210, is S
When removing the OG intermediate layer pattern 208, the rabbit ears 1.211 formed on the sidewalls of the lower resist pattern 209 are etched using the lower resist pattern 209 as a mask, and are the remaining portions of the AffSi film 203.
Rabbit ears 2.21 212 are formed on the side walls of the AlSi film pattern 211 and the lower resist pattern 209 when forming the AffSi film pattern 211.
3 is a surface protective film, and 214 is a raised portion of the surface protective film due to rabbit ears.
まず第４図（ａｌに示す様にＳｉ基板２０１上に５ｉ０
２膜２０２を形成し、続いて厚さ１μｍのＡ ｊ！ Ｓ
ｉ膜２０２をスパッタ法で堆積する。次に第４図（ｂ
ｌの様に下層レジスト２０４、ＳＯＧの中間層２０５、
上層のＥＢレジスト２０６を連続して形成し、三層レジ
ストを形成する。この三層レジストを以下の手順でパタ
ーン出しする。まず第４図（Ｃ）の様に、ＥＢ露光及び
現像を行ってＥＢレジストパターン２０７を形成し、こ
のＥＢレジストパターン２０７をマスクにしてエツチン
グを行い、ＳＯＧの中間層パターン２０８を形成する。First, as shown in FIG. 4 (al), 5i0
2 film 202 is formed, followed by A j! with a thickness of 1 μm. S
An i film 202 is deposited by sputtering. Next, Figure 4 (b
1, a lower resist layer 204, an SOG intermediate layer 205,
An upper layer of EB resist 206 is continuously formed to form a three-layer resist. This three-layer resist is patterned using the following procedure. First, as shown in FIG. 4C, EB exposure and development are performed to form an EB resist pattern 207, and etching is performed using this EB resist pattern 207 as a mask to form an SOG intermediate layer pattern 208.
そして、第４図（ｄ）の様にこのＳＯＧの中間層パター
ン２０８をマスクにして下層レジスト２０４をエツチン
グし、下層レジストパターン２０９を形成する。またＥ
Ｂレジストパターン２０７は同時に除去される。この時
レジストのエツチングは０２（酸素）プラズマで行うた
め、ＡｌＳｉ膜２０３の表面がこの０２プラズマでたた
かれて、Ａ ｌ又はＳｉ原子が飛び出し、Ａｆ２０：ｉ
（アルミナ）分子等になって下層レジストパターン２０
９の側面に付着し、ラビットイヤー（レジスト除去後に
も除去されないうさぎの耳状の残渣、以下ラビットイヤ
ーと呼ぶ。）１，２１０が形成される。次に第４図ｔｅ
ｌの様にＳＯＧの中間層パターン２０８を除去して下層
レジストパターン２０９のみを残し、第４図ば）の様に
この下層レジストパターン２０９をマスクにしてＡｊ’
Ｓｉ膜２０３をエツチングする。この時ＡｆＳｉ２０３
のエンチング時の反応で更にＡｊ’２０３（アルミナ）
等が下層レジストパターン２０９の側壁に付着し、ラビ
ットイヤー２．２１２が形成される。続いて第４１１ｇ
＋の様に下層レジストパターン２０９を除去し、第４図
（ｈｌの様に表面保護膜２１３を形成して、三層レジス
トを用いたドライエツチング工程を含む、配線の形成を
行うことができる（例えばに、Ｈａｓｈｉｍｏｔｏ ｅ
ｔ、ａｌ、 Ｎｕｃｌｅａｒ Ｉｎｓｔｒｕｍｅｎｔｓ
ａｎｄＭｅｔｈｏｄｓ ｉｎ Ｐｈｙｓｉｃｓ Ｒｅ
５ｅａｒｃｈ Ｂ５９（１９８９） ８１３−８１６、
Ｎｏｒｔｈ−１１ｏ１１ａｎｄ、 Ａｍｓｔｅｒｄａ
ｍ）。Then, as shown in FIG. 4(d), the lower resist 204 is etched using the SOG intermediate layer pattern 208 as a mask to form a lower resist pattern 209. Also E
B resist pattern 207 is removed at the same time. At this time, since the resist is etched using 02 (oxygen) plasma, the surface of the AlSi film 203 is hit by this 02 plasma, and Al or Si atoms fly out, resulting in Af20:i
(alumina) molecules, etc., lower layer resist pattern 20
Rabbit ears (rabbit ear-shaped residues that are not removed even after resist removal, hereinafter referred to as rabbit ears) 1,210 are formed. Next, Figure 4te
As shown in FIG. 4, the intermediate layer pattern 208 of the SOG is removed, leaving only the lower resist pattern 209, and as shown in FIG.
The Si film 203 is etched. At this time AfSi203
Aj'203 (alumina) is further produced by the reaction during enching.
etc. adhere to the side wall of the lower resist pattern 209, forming rabbit ears 2.212. Next, 411g
After removing the lower resist pattern 209 as shown in +, forming a surface protective film 213 as shown in FIG. For example, Hashimoto e
t, al, Nuclear Instruments
andMethods in Physics Re
5earch B59 (1989) 813-816,
North-11o11and, Amsterdam
m).
発明か解決しようとする課題
しかしこの様な従来の方法では、第４図（ｅｌのラビッ
トイヤー１．２１０及びラビットイヤー２２１２が、ド
ライエツチング工程終了後に除去されずに残り、表面保
護膜の盛り上がり２１４が形成される為配線の平坦化の
妨げとなりミプロセス上大きな問題となっていた。Problems to be Solved by the Invention However, in such a conventional method, the rabbit ears 1.210 and 2212 in FIG. This has been a major problem in microprocessing as it has been a hindrance to flattening the wiring.
本発明はかかる点に鑑みてなされたもので、簡単な構成
でラビットイヤーの形成されない、良好な多層又は単層
レジスト膜を用いたドライエツチング工程を含む配線の
形成方法を提供することを目的としている。The present invention has been made in view of the above points, and an object of the present invention is to provide a method for forming a wiring including a dry etching process using a multi-layer or single-layer resist film, which has a simple structure, does not form rabbit ears, and has a good quality. There is.
課題を解決するための手段
本発明は、上記課題を解決するため、バターニングされ
る第１の被エツチング膜と多層又は単層レジスト膜の最
下層レジスト膜との間に、前記多層又は単層レジスト膜
のパターン形成の為のエツチング時に反応しないか、又
は反応しても前記第１の被エツチング膜をエツチングす
ることなく選択的に除去することが可能な、第２の被エ
ツチング膜を形成することにより、ラビットイヤーの形
成されない良好な多層又は単層レジスト膜を用いたドラ
イエツチング工程を含む配線の形成方法を提供するもの
である。Means for Solving the Problems In order to solve the above problems, the present invention provides the multilayer or single layer resist film between the first film to be etched to be patterned and the lowest resist film of the multilayer or single layer resist film. Forming a second film to be etched that does not react during etching for pattern formation of a resist film, or can be selectively removed without etching the first film to be etched even if it reacts. Accordingly, the present invention provides a method for forming interconnections that includes a dry etching process using a multilayer or single layer resist film that is good in that rabbit ears are not formed.
作用
本発明は上記した構成により、バターニングされる第１
の被エツチング膜上を、多層又は単層レジスト膜のパタ
ーン形成の為のエツチング時に反応しないか、又は反応
しても前記第１の被エツチング膜をエツチングすること
なく選択的に除去することが可能な、第２の被エツチン
グ膜が被覆している為、ラビットイヤーか形成されるこ
とがなく、良好な多層レジストを用いたドライエツチン
グ工程を含む、配線の形成を行うことかできる。Function The present invention has the above-described structure, and the first
The first film to be etched does not react during etching for pattern formation of a multilayer or single-layer resist film, or even if it reacts, it can be selectively removed without etching the first film to be etched. Since it is covered with the second film to be etched, no rabbit ears are formed, and wiring can be formed including a dry etching process using a good multilayer resist.
実施例
第１図は本発明の配線の形成方法の第１の実施例である
。図中１０１はＳｉ基板、１０２は５ｉ０２膜、１０３
はＡｊ７Ｓｉ膜、１０４はＴｉＮ膜、１０５は下層レジ
スト、１０６はＳＯＧの中間層、１０７は上層のＥＢレ
ジスト、１０８はＥＢ露光でパターン出しした、上層の
ＥＢレジスト１０７の残しの部分、１０９は上層のＥＢ
レジストパターン１０８をマスクにしてエツチングした
ＳＯＧの中間層１０６の残しの部分、１１０はＳＯＧの
中間層パターン１０９をマスクにしてエツチングした、
下層レジスト１０５の残しの部分、１１１は下層レジス
トパターン１１０をマスクにしてエツチングしたＴｉＮ
膜１０４の残しの部分、１１２は同じ（下層レジストパ
ターン１１０をマスクにしてエツチングしたＡｊ？Ｓｉ
膜の残しの部分、１１３は表面保護膜、１１４はＡｌＳ
ｉ膜１０３のエツチング時に形成されたラビットイヤー
１１５はサイドエツチングで後退したＴｉＮ膜１０４
の残しの部分、１１６はラビットイヤー１１４の除去時
に後退したＴｉＮ膜１０４の残しの部分である。Embodiment FIG. 1 shows a first embodiment of the wiring forming method of the present invention. In the figure, 101 is a Si substrate, 102 is a 5i02 film, and 103
104 is the Aj7Si film, 104 is the TiN film, 105 is the lower resist layer, 106 is the intermediate layer of SOG, 107 is the upper layer EB resist, 108 is the remaining part of the upper layer EB resist 107 patterned by EB exposure, 109 is the upper layer EB of
The remaining portion of the SOG intermediate layer 106 was etched using the resist pattern 108 as a mask, and 110 was etched using the SOG intermediate layer pattern 109 as a mask.
The remaining portion of the lower resist 105, 111, is TiN etched using the lower resist pattern 110 as a mask.
The remaining part of the film 104, 112, is the same (Aj?Si etched using the lower resist pattern 110 as a mask).
The remaining part of the film, 113 is a surface protective film, 114 is AlS
Rabbit ears 115 formed during etching of the i film 103 are the TiN film 104 that has retreated due to side etching.
The remaining portion 116 is the remaining portion of the TiN film 104 that retreated when the rabbit ear 114 was removed.
まず第１図（ａｌに示す様にＳｉ基板１０１上にＳｉＯ
膜１０２を形成し、続いて厚さ１μｍのＡｌＳｉ膜１０
３をスパッタ法で堆積する。次に第１図（ｂｌの様にＴ
ｉＮ膜１０４をＡＩｊ！５ｉ膜１０３の上に形成し、こ
のＴｉＮ膜１０４の上に第１図（Ｃ１の様に、下層レジ
スト１０５、ＳＯＧの中間層１０６、上層のＥＢレジス
ト１０７を連続して形成し、三層レジストを形成する。First, as shown in FIG. 1 (al), SiO
A film 102 is formed, followed by an AlSi film 10 with a thickness of 1 μm.
3 is deposited by sputtering. Next, in Figure 1 (T like bl)
AIj! iN film 104! 5i film 103, and on this TiN film 104, a lower resist 105, an intermediate SOG layer 106, and an upper EB resist 107 are successively formed as shown in FIG. form.
この三層レジストを以下の手順でパターン出しする。ま
ず第１図ｆｄ＋の様にＥＢ露光及び現像を行ってＥＢレ
ジストパターン１０８を形成し、このＥＢレジストパタ
ーン１０８をマスクにしてエツチングを行い、ＳＯＧの
中間層パターン１０９を形成する。次に第１図ｔｅｌに
示す様に、このＳＯＧの中間層パターン１０９をマスク
にして下層レジスト１０５をエツチングし、下層レジス
トパターン１１０を形成する。この時ＥＢレジストパタ
ーン１０８１；ｉ同時に除去される。この時レジストの
エツチングは０２（酸素）プラズマで行うが、ＡＡＳｉ
膜１０３の表面はＴｉＮ膜１０４で覆われている為、Ａ
Ａ’ＳｉＡｌＳｉ膜表面が直接０２（酸素）でたたかれ
て、Ａｌ又はＳｉ原子が飛び出し、ＡＩ！２０３（アル
ミナ）分子等になって下層レジストパター７１１０の側
面に付着し、ラビットイヤーが形成されることはない。This three-layer resist is patterned using the following procedure. First, as shown in FIG. 1fd+, EB exposure and development are performed to form an EB resist pattern 108, and etching is performed using this EB resist pattern 108 as a mask to form an SOG intermediate layer pattern 109. Next, as shown in FIG. 1, the lower resist 105 is etched using the SOG intermediate layer pattern 109 as a mask to form a lower resist pattern 110. At this time, the EB resist pattern 1081;i is removed at the same time. At this time, resist etching is performed using 02 (oxygen) plasma, but AASi
Since the surface of the film 103 is covered with the TiN film 104, A
A'SiAlSi film surface is directly hit with 02 (oxygen), Al or Si atoms fly out, and AI! 203 (alumina) molecules and the like and adhere to the side surfaces of the lower resist pattern 7110, thereby preventing the formation of rabbit ears.
次に第１図（ｆｌの様にＳＯＧの中間層パターン１０９
を除去して下層レジストパターン１１０のみを残し、第
１図ｆｇｌの様にこの下層レジストパターン１１０をマ
スクにしてＴｉＮ膜１０４とＡｌＳｉ膜１０２をエツチ
ングし、ＴｉＮ膜１０４の残しの部分１う、１とＡｌＳ
ｉ膜１０３の残しの部分１１２を形成）る。この時下層
レジストパターン１１０の側壁にはラビットイヤーは形
成されにくい。その理由は第１図ｔｅｌの下層レジスト
パターン１１０の形成時に、下層レジストパターン１１
０の側壁にラビットイヤー１が形成されない為、ＴｉＮ
膜１０４とＡＩ！Ｓｉ膜１０３膜上０３ング時に下層レ
ジストパターン１１０が後退するので、ラビットイヤー
２も形成されないからである。Next, as shown in FIG. 1 (fl), the SOG intermediate layer pattern 109
is removed to leave only the lower resist pattern 110, and the TiN film 104 and AlSi film 102 are etched using the lower resist pattern 110 as a mask as shown in FIG. and AlS
The remaining portion 112 of the i-film 103 is formed). At this time, rabbit ears are less likely to be formed on the sidewalls of the lower resist pattern 110. The reason for this is that when forming the lower resist pattern 110 in FIG.
Because rabbit ear 1 is not formed on the side wall of TiN
Membrane 104 and AI! This is because the lower resist pattern 110 recedes when the Si film 103 is coated, so that the rabbit ears 2 are not formed.
最後に第１図（ｉ）に示す様に表面保護膜１１３を形成
する。この時ラビットイヤーによる表面保護膜の盛り上
がりは形成されない。Finally, a surface protective film 113 is formed as shown in FIG. 1(i). At this time, no protrusions of the surface protective film due to rabbit ears are formed.
以上の理由により本発明の方法を用いれば、多層レジス
トを用いてドライエツチングを行う場合にもラビットイ
ヤーが形成されることがなく、良好な多層レジストを用
いたドライエツチング工程を含む、配線の形成を行うこ
とができる。For the above reasons, if the method of the present invention is used, rabbit ears will not be formed even when dry etching is performed using a multilayer resist, and wiring formation including a dry etching process using a good multilayer resist is possible. It can be performed.
また本実施例においては、第１の被エツチング膜として
ＡｌＳｉ膜、第２の被エツチング膜としてＴｉＮ膜を用
いたが、第１の被エツチング膜としてＡｌ・Ｓｌ・ＣＩ
４等他のＡｌ合金膜、第２の被エツチング膜としてＷや
〜ＶＳｉ、〜１０Ｓ１等池の高融点金属や高融点金属化
合物膜を用いても構わない。Further, in this example, an AlSi film was used as the first film to be etched, and a TiN film was used as the second film to be etched, but Al, Sl, CI was used as the first film to be etched.
As the second film to be etched, a high melting point metal or a high melting point metal compound film such as W, ~VSi, ~10S1, etc. may be used.
また第１図（」）の様に、ＡｆＳｉ膜１０３のエツチン
グ時にラビットイヤー１１４が形成された場合、本発明
の方法を用いれば容易にラビットイヤーを除去すること
ができる。例えば第１図＋ｋｌの様にＴｉＮ膜１０４の
残しの部分にのみ選択的なサイドエッチ１１５を形成し
てから下層レジストパターン１１０を除去すると、第１
図（１）の様にラビットイヤー１１４のない良好な配線
の形成を行うことかできる。Further, as shown in FIG. 1(''), if rabbit ears 114 are formed during etching of the AfSi film 103, the rabbit ears can be easily removed by using the method of the present invention. For example, if a selective side etch 115 is formed only on the remaining portion of the TiN film 104 as shown in FIG.
As shown in FIG. 1, it is possible to form good wiring without rabbit ears 114.
あるいは第１図（−の様に先に下層レジスト１１０を除
去してからＴｉＮ膜１０４の残しの部分を選択的にエツ
チングすると、第１図ｉｎ＋の様にラビットイヤー１１
４は除去され、後退したＴｉＮ膜１０４の残しの部分１
１６が残り、ラビットイヤー１１４のない良好な配線の
形成を行うことができる。Alternatively, if the lower resist 110 is first removed as shown in FIG.
4 is the remaining portion 1 of the TiN film 104 that has been removed and retreated.
16 remain, and it is possible to form a good wiring without rabbit ears 114.
また、この時後退したＴｉＮ膜１０４の残しの部分１１
６は、完全に除去してＡｌＳｉ膜の残しの部分１１２の
みを残しても構わない。Also, the remaining portion 11 of the TiN film 104 that retreated at this time
6 may be completely removed, leaving only the remaining portion 112 of the AlSi film.
第２図に示すのは本発明の配線の形成方法の第２の実施
例である。図中３０１はＳｉ基板、３０２は５ｉ０２膜
、３０３はＡｊ！Ｓｉ膜、３０４はＴｉＮ膜、３０５は
下層レジストパターン、３０６は下層レジストパターン
３０５をマスクにしてエツチングしたＴｉＮ膜３０４の
残しの部分、３０７はＴｉＮ膜の残しの部分３０６をマ
スクにしてエツチングした。へ！Ｓｉ膜３０３の残しの
部分、３０８はＡｌ’Ｓｉ膜３０３をエツチングする際
にＴｉＮ膜の残しの部分３０６の側壁に形成されたＡ
１２０３等の膜、３０９は表面保護膜である。FIG. 2 shows a second embodiment of the wiring forming method of the present invention. In the figure, 301 is a Si substrate, 302 is a 5i02 film, and 303 is Aj! 304 is a Si film, 304 is a TiN film, 305 is a lower resist pattern, 306 is a remaining portion of the TiN film 304 etched using the lower resist pattern 305 as a mask, and 307 is etched using the remaining portion 306 of the TiN film as a mask. fart! The remaining portion 308 of the Si film 303 is an A formed on the side wall of the remaining portion 306 of the TiN film when etching the Al'Si film 303.
Films such as 1203 and 309 are surface protective films.
まず第２図（ａｌの様に下層レジストパターン３０５を
形成する。この下層レジストパターン３０５の形成は、
本発明の配線の形成方法の第１の実施例と全く同じ工程
により行う。次に第２図（ｂｌの様に下層レジストパタ
ーン３０５をマスクにしてＴｉＮ膜３０４をエツチング
し、ＴｉＮ膜の残しの部分３０６を形成した後、第２図
（Ｃ１の様に下層レジストパターン３０５を除去する。First, a lower resist pattern 305 is formed as shown in FIG.
The process is exactly the same as in the first embodiment of the wiring forming method of the present invention. Next, as shown in FIG. 2 (BL), the TiN film 304 is etched using the lower resist pattern 305 as a mask to form a remaining portion 306 of the TiN film. Remove.
続いて第２図（ｄｉの様にＴｉＮ膜の残しの部分３０６
をマスクにしてＡｊ！Ｓｉ膜３０３をエツチングし、Ａ
ｊ！Ｓｉ膜３０３の残しの部分３０７を形成する。この
時ＴｉＮ膜の残しの部分３０６の側壁には、Ａｌ：＋０
：＋等の膜３０８が形成される。最後に第２図＋ｅｌの
様に表面保護膜３０９を形成し、ラビットイヤーのない
良好な配線の形成を行うことができる。Next, the remaining part 306 of the TiN film is shown in Figure 2 (di).
Aj with a mask! Etching the Si film 303,
j! A remaining portion 307 of the Si film 303 is formed. At this time, on the side wall of the remaining portion 306 of the TiN film, Al: +0
:+ film 308 is formed. Finally, a surface protective film 309 is formed as shown in FIG. 2+el, and good wiring without rabbit ears can be formed.
本発明の第２の実施例を用いれば、第２図（ｄｌの様に
ラビットイヤーのもととなるＡｌ２Ｏ：ｒ等の膜３０８
が形成されても、ＴｉＮ膜の残しの部分３０６は除去し
ない為、ラビットイヤーは形成されない。If the second embodiment of the present invention is used, as shown in FIG.
Even if a rabbit ear is formed, the remaining portion 306 of the TiN film is not removed, so no rabbit ear is formed.
第３図に示すのは本発明の配線の形成方法の第３の実施
例である。図中４０１はＳｉ基板、４０２は５ｉ０２膜
、４０３はＡｌＳｉ膜、４０４はタングステン（以下Ｗ
と書く）膜、４０５は下層レジストパターン、４０６は
下層レジストパターン４０５をマスクにしてエツチング
したＷ膜４０４の残しの部分、４０７はＷ膜の残しの部
分４０６をマスクにしてエツチングしたＡｊｌ！Ｓｉ膜
４０３の残しの部分、４０８は表面保護膜である。FIG. 3 shows a third embodiment of the wiring forming method of the present invention. In the figure, 401 is a Si substrate, 402 is a 5i02 film, 403 is an AlSi film, and 404 is a tungsten (hereinafter referred to as W
405 is the lower resist pattern, 406 is the remaining part of the W film 404 etched using the lower resist pattern 405 as a mask, and 407 is the Ajl! film etched using the remaining part 406 of the W film as a mask. The remaining portion of the Si film 403, 408, is a surface protection film.
まず第３図（ａｌの様に下層レジストパターン４０５を
形成する。この下層レジストパターン４０５の形成は、
本発明の配線の形成方法の第１の実施例と全く同じ工程
により行う。次に第３図ｆｂｌの様に下層レジストパタ
ーン４０５をマスクにしてＷ膜４０４をエツチングし、
Ｗ膜の残しの部分４０６を形成した後、第３図（Ｃ）の
様に下層レジストパターン４０５を除去する。続いて第
３図ｔｄｌの様にＷ膜の残しの部分４０６をマスクにし
てＡｊｌ’Ｓｉ膜４０３をエツチングし、Ａｌ’Ｓｉ膜
４０３の残しの部分４０７を形成する。この時Ｗ膜の残
しの部分４０６の側壁は少しサイドエツチングされて後
退する為、Ａｆ２０３等の膜は形成されない。従って第
３図（ｅ）の様にＷ膜の残しの部分４０６を除去すると
、ラビットイヤーは形成されず、最後に第３図（ｆｌの
様に表面保護膜４０８を形成して、良好な配線の形成を
行うことができる。First, a lower resist pattern 405 is formed as shown in FIG.
The process is exactly the same as in the first embodiment of the wiring forming method of the present invention. Next, as shown in FIG. 3 fbl, the W film 404 is etched using the lower resist pattern 405 as a mask.
After forming the remaining portion 406 of the W film, the lower resist pattern 405 is removed as shown in FIG. 3(C). Subsequently, as shown in FIG. 3 tdl, the Ajl'Si film 403 is etched using the remaining portion 406 of the W film as a mask to form a remaining portion 407 of the Al'Si film 403. At this time, the side wall of the remaining portion 406 of the W film is slightly side-etched and retreated, so that no film such as Af203 is formed. Therefore, when the remaining portion 406 of the W film is removed as shown in FIG. 3(e), rabbit ears are not formed, and finally a surface protective film 408 is formed as shown in FIG. can be formed.
本発明の第３の実施例を用いれば、Ｗ膜の残しの部分４
０６はＡｆＳｉ膜４０３のエツチング時にサイドエツチ
ングされて後退する為、Ａｌ２Ｏ３等の膜が側壁に付着
することがなく、ラビットイヤーが形成されない。If the third embodiment of the present invention is used, the remaining portion 4 of the W film
Since 06 is side-etched and retreats when etching the AfSi film 403, a film such as Al2O3 does not adhere to the sidewall, and rabbit ears are not formed.
また、他の実施例としては、第２の被エツチング膜とし
てＳｉＯ□膜を用いることもできる。この場合、ＳｌＯ
□膜はＴＥ０１ （テトラエトキシシラン）を原料とし
てプラズマＣＶＤ法等で成長させればよい。Furthermore, in another embodiment, a SiO□ film may be used as the second film to be etched. In this case, SlO
□The film may be grown by plasma CVD or the like using TE01 (tetraethoxysilane) as a raw material.
発明の効果
以上述へてきた様に本発明によれば、極めて簡易な構成
でラビットイヤーの形成されない非常に良好な配線の形
成を行うことができ、プロセスの改善に大きく寄与する
ものである。Effects of the Invention As described above, according to the present invention, it is possible to form very good wiring without the formation of rabbit ears with an extremely simple configuration, which greatly contributes to process improvement.
第１図〜第３図はそれぞれ本発明の第１〜第３実施例に
おける配線の形成方法を示す工程断面図、第４図は従来
の配線の形成方法を示す工程断面図である。
１０３・・・・・・ＡｌＳｉ膜、１０４・・・・・・Ｔ
ｉＮ膜、１０５・・・・・・下層レジスト、１０６・・
・・・・ＳＯＧの中間層、１０７・・・・・・上層のＥ
Ｂレジスト。1 to 3 are process cross-sectional views showing methods of forming wiring in first to third embodiments of the present invention, respectively, and FIG. 4 is a process cross-sectional view showing a conventional method of forming wiring. 103...AlSi film, 104...T
iN film, 105...lower resist, 106...
...Middle layer of SOG, 107...E of upper layer
B resist.
Claims (3)
グ工程を含む配線の形成方法において、前記ドライエッ
チングによってパターニングされる第１の被エッチング
膜と、前記第１の被エッチング膜表面に直接形成される
前記多層又は単層レジスト膜のうちの最下層レジスト膜
との間に、前記多層又は単層レジスト膜のパターン形成
の為のエッチング時に反応して、反応複生成物を前記多
層又は単層レジスト膜パターンの側壁に堆積しないか、
又は反応した場合でも前記第１の被エッチング膜をエッ
チングすることなく選択的に除去することが可能な、第
２の被エッチング膜を形成することを特徴とする配線の
形成方法。(1) In a wiring formation method including a dry etching process using a multilayer or single-layer resist film, a first film to be etched is patterned by the dry etching, and a film formed directly on the surface of the first film to be etched is patterned by the dry etching. A reaction product is formed between the bottom resist film of the multilayer or single-layer resist film during etching for pattern formation of the multi-layer or single-layer resist film. Does it not accumulate on the sidewalls of the film pattern?
Or, even if a reaction occurs, a second film to be etched can be selectively removed without etching the first film to be etched.
を、第２の被エッチング膜としてＴｉＮ膜を用いること
を特徴とする特許請求の範囲第１項記載の配線の形成方
法。(2) The method for forming wiring according to claim 1, characterized in that an Al or Al alloy film is used as the first film to be etched, and a TiN film is used as the second film to be etched.
融点金属化合物膜を用いることを特徴とする特許請求の
範囲第２項記載の配線の形成方法。(3) The method for forming wiring according to claim 2, wherein a high melting point metal or a high melting point metal compound film is used as the second film to be etched.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31362689A JPH03173430A (en) | 1989-12-01 | 1989-12-01 | Formation of wiring |
| US07/855,459 US5204285A (en) | 1989-12-01 | 1992-03-19 | Method for patterning a metal layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31362689A JPH03173430A (en) | 1989-12-01 | 1989-12-01 | Formation of wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03173430A true JPH03173430A (en) | 1991-07-26 |
Family
ID=18043585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31362689A Pending JPH03173430A (en) | 1989-12-01 | 1989-12-01 | Formation of wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03173430A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58122750A (en) * | 1982-01-14 | 1983-07-21 | Toshiba Corp | Preparation of semiconductor device |
| JPS5984444A (en) * | 1982-11-05 | 1984-05-16 | Fujitsu Ltd | Pattern formation |
| JPS63119547A (en) * | 1986-11-07 | 1988-05-24 | Nippon Telegr & Teleph Corp <Ntt> | Formation of wiring structure |
| JPH01208842A (en) * | 1988-02-16 | 1989-08-22 | Nec Corp | Manufacture of semiconductor integrated circuit device |
| JPH01255247A (en) * | 1988-04-04 | 1989-10-12 | Matsushita Electric Ind Co Ltd | Metal wiring pattern forming method |
-
1989
- 1989-12-01 JP JP31362689A patent/JPH03173430A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58122750A (en) * | 1982-01-14 | 1983-07-21 | Toshiba Corp | Preparation of semiconductor device |
| JPS5984444A (en) * | 1982-11-05 | 1984-05-16 | Fujitsu Ltd | Pattern formation |
| JPS63119547A (en) * | 1986-11-07 | 1988-05-24 | Nippon Telegr & Teleph Corp <Ntt> | Formation of wiring structure |
| JPH01208842A (en) * | 1988-02-16 | 1989-08-22 | Nec Corp | Manufacture of semiconductor integrated circuit device |
| JPH01255247A (en) * | 1988-04-04 | 1989-10-12 | Matsushita Electric Ind Co Ltd | Metal wiring pattern forming method |
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