JPH03173225A - Satellite broadcast receiver - Google Patents

Abstract

PURPOSE:To prevent generation of an undersired spectrum by stopping the operation of a 2nd oscillator when the voice mode is the B mode, selecting the output signal of a 1st oscillator, and applying the signal to a PWM system D/A converter. CONSTITUTION:A bit stream 1 in a satellite broadcast receiver is inputted to a PCM demodulation block 2. A 1st oscillator 4 is oscillated at a frequency of 48kHzXn, recovers a bit clock, which is a main block of a PCM signal processing circuit 8. A 2nd oscillator 9 is oscillated at a frequency of 32kHzXn. When the voice mode is the B mode, a selector circuit 14 selects the output signal of the oscillator 4. In this case, a diode 16 is energized, the inverter input of the oscillator 9 is fixed to a low level to stop the oscillation. Thus, the invasion of an undersired spectrum component by the oscillator 9 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a satellite broadcast receiver, particularly to an oscillation circuit that supplies a clock to a processing section after PCM signal processing.

Conventional technologyIt has been a long time since equipment using digital technology was put into practical use, but analog quantities are converted into discrete values and digitally processed, and D/A converters are used in the process of converting into analog quantities. As a D/A conversion method, a resistance ladder type as typified by the R-2R type has conventionally been used, but in order to reduce costs, ICs have been used. However, in this case, as the number of quantizations increases, the accuracy of the resistance value that can be created inside the IC makes it impossible to maintain the conversion accuracy of the D/A converter. However, this had no choice but to increase costs. However, recently, it has become possible to ensure conversion accuracy regardless of the resistance value accuracy within the IC by using an IC-based D/A converter that utilizes PWM (pulse width variation).

Problems to be Solved by the Invention However, recently, as devices with three types of sampling frequencies [compact disc players (CDs), digital audio tape recorders (DATs), and BS tuners] have been put into practical use, This requires a clock that is a certain multiple of the input sampling frequency mentioned above, and it has become necessary to switch the clock frequency of the PWM system depending on the sampling frequency of the input signal to be D/A converted.

At this time, as shown in Figure 2, for the clock fundamental wave C,
Spectrum C of unnecessary components when frequency is divided in the switching circuit
I now appears in the output clock of the switching circuit, and due to the spectrum C1 of this unnecessary component, the PWM type D/
It has been found that this degrades the S/N (signal/noise) ratio of the A converter.

The state of this deterioration will be explained with reference to the following document.

Here, as a reference, "Acoustical Society of Japan Lecture Proceedings October 1986 p411. (1-6-13, Consideration of clock jitter in PWM type D/A converter) Tetsuhiko Kaneaki: Matsushita Electric Industrial ■, AV research The following explanation will be given below.

According to the reference literature, "Clock jitter increases the noise level, and the noise level and the amount of jitter are proportional." Here, as shown in Figure 2, PWM method D/
A component of the clock fundamental wave for the PWM type D/A converter divided by 1/n (n is an integer; in FIG. 2, the frequency is divided by 172) is added to the clock fundamental wave for the A converter. The spectrum diagram at this time is shown in Figure 2, and Figure 3 shows the waveform diagram in the time domain. Figure 3 (a) is the waveform diagram when only the fundamental wave is used for the PWM type D/A converter. Yes, Figure 3 ■)
is the waveform when the 172 frequency divided output is mixed into the fundamental wave,
This is the result when the frequency domain in FIG. 2 is changed to the time domain.

Let us now consider the case where the clock fundamental wave shown in FIG. 3a and the signal obtained by mixing the 172 frequency divided output into the clock fundamental wave shown in FIG. 3 are passed through amplifiers as shown in FIG. The amplifier shown in FIG. 4 is a type of amplifier in which feedback is applied to the input and output of an inverter in a logic circuit. Therefore, a threshold level exists. Figure 4 (c) is the third
When the signal in figure (a) is input to the amplifier in figure 4 (a),
Figure 4 (C) shows the waveform in the logic circuit when the signal in Figure 3 (■) is input to the amplifier in Figure 4 (a).
In Figure (C), it can be seen that jitter occurs. Therefore, as shown in the reference, jitter occurs and noise increases.

Next, when the input sampling frequency changes, for example, when the sampling frequency is fs, the clock of the PWM type D/A converter is fsXl (I is an integer, currently 128.1
92,256,384.768 is commonly used.

) is given by However, the sampling frequency fs is f
If it changes to s+ or fsl, it is necessary to change the clock of the PWM D/A converter to fs, .multidot.1fszl. At this time, selector circuits for fs+.1 and fst.1 are required.

Also, in actual circuits, as shown in Figures 5 and 6, when the impedance of the substrate is high as shown in Figure 6, the substrate voltage is Due to the slight change, a spectrum corresponding to the frequency of the current flowing through the substrate wraps around the selector circuit 24 and is superimposed on the spectrum of the output clock of the clock circuit.

There is also interference from the power supply voltage within the IC.

As a result of the above, an unnecessary spectrum is superimposed on the clock spectrum of the PWM system, causing deterioration of the S/N of the PWM system D/A converter. This deterioration in S/N becomes greater for a B-mode audio signal in which audio data is sent with 16-bit precision. Since A-mode audio data is compressed on the transmitting side and sent in 10 bits, it does not appear as much noise compared to 16-bits in B-mode. Furthermore, Figure 5,
In Fig. 6, 20 is the fslXI oscillator, 21 is fs
z×1 oscillator, 22, 23 is its output terminal, 25 is the output terminal of the selector circuit 24, 26 is a PWM type D/A converter, and 15 is the input terminal of the switching control signal of the selector circuit 24.

In view of the above-mentioned problems, the present invention provides a PWM-method D/A converter and a PWM-method D/A converter capable of suppressing the occurrence of the above-mentioned unnecessary spectrum when the audio mode is B mode.
The purpose of this invention is to provide a clock generation circuit for A converters.

Means for Solving the Problems To achieve this object, the satellite broadcasting receiver of the present invention comprises:
Two clock generation oscillators are provided to supply the D/A converter, one of which oscillates at an integer multiple of 48 KHz, and the other oscillates at an integer multiple of 32 KHz.
mode or B mode), and in B mode, 32Kl
(The z oscillator is “Low” in B mode through a diode.
A mode oscillator (32
By setting the inverter power of Kt (an integral multiple of z) to the "Low" level, oscillation is stopped and the generation of unnecessary spectrum is prevented.

Effect of the present invention With the above-described configuration, the generation of unnecessary spectrum can be prevented by stopping the operation of the oscillator of integral multiples of 32 KHz depending on the state of the mode display signal.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, reference numeral 1 indicates a focus stream within a satellite broadcasting receiver, which is input to a PCM demodulation block 2, where pit clock reproduction is performed.

At this time, it is composed of a phase detector 3, a loop filter 5, a varicap, a diode 6, a capacitor 7, and a first oscillation circuit 4. The first oscillator oscillates at 48K) (zXn (n is an integer), reproduces the pit clock, and
It is the main clock of the M signal processing circuit 8. In synchronization with this main clock, a second oscillator (second oscillation circuit 9, second capacitor 10, second varicap 11)
, a second loop filter 12, and a second phase detector 13) oscillates at 32 KHzXn. Each output signal of the first oscillator and the second oscillator is input to the selector circuit 14. In addition, the PCM signal processing circuit 8 outputs an A mode/B mode display output signal (“H4g
h” level, “Low” level output signal in B mode)
15 is output, and this output is used to switch the selector circuit 14. When the audio mode is B mode, the selector circuit 14 selects the output signal of the first oscillator. At this time, the diode 16 inserted between the second oscillator and the A-mode/B-mode display output signal line is "on" because the A-mode/B-mode display output signal 15 is at the "Low" level. The inverter power of the second oscillation circuit 9 in the second oscillator is “Lo”
w” level and stops oscillation.

Next, when A mode is received as the audio mode,
The A mode/B mode display output signal 15 becomes "H4gh" level, the diode 16 turns off, and the second
The oscillation circuit 9 starts oscillating. At this time, the selector circuit I4 selects the output of the second oscillator. In addition, 1
7 is a PWM type D/A converter, 18 is a master clock of the PWM type D/A converter 17, and 19 is a shift clock, data, and L channel/R channel identification signal.

In this way, according to this embodiment, the second oscillator that oscillates at zXn stops oscillating (32K in the B mode in which the audio data is sent in 16 bits). Spectrum components are not mixed into the first oscillator, and deterioration in S/ is prevented by that much.

Effects of the Invention As described above, according to the present invention, when inputting and selecting two types of clock signals from the outside to a PWM type D/A converter, it is possible to eliminate the factors that cause the deterioration of the S/to signal. Since the oscillation of one of the oscillators is stopped and the generation of unnecessary spectrum of the external input clock is reduced, the occurrence of sintering can be reduced, and the S/ can be improved, and its practical effects are significant.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a satellite broadcasting receiver according to an embodiment of the present invention, Figure 2 is a clock spectrum diagram when clock jitter occurs, and Figure 3a is a time domain waveform when only the clock fundamental wave is present. Figure 3 is a time-domain waveform diagram when frequency-divided waves are mixed in; Figure 4 a, b, and c are block diagrams of the amplifier configured with gates and waveform diagrams for explaining its operation; Figure 5 is a waveform diagram for explaining its operation. A block diagram in the case of causing clock jitter, FIG. 6 is a circuit diagram of the main part of FIG. 5. 1...Pit stream in the satellite broadcasting receiver,
2...PCM demodulation block, 3, 13...
...Phase detector, 4.9...First and second oscillators, 5,12...Loop filter, 6.11.
... Varicap, 7゜lO ... Capacitor, 8 ... PCM signal processing circuit, 14 ...
...Selector circuit, 15...A modero mode display output signal (selector switching signal), 16...
...Diode, 17...PWM type D/A
converter.

Claims (1)

[Claims] First and second oscillators for clock generation that oscillate at frequencies that are integral multiples of the first and second sampling frequencies, respectively, compatible with the audio mode of satellite broadcasting, and a PWM type D/A.
a converter, a selector circuit that selects either one of the output signals of the first or second oscillator and supplies it to the PWM D/A converter, and a selector circuit that selects one of the output signals of the first and second oscillators and supplies the same to the PWM D/A converter; means for generating a control signal, and when the audio mode is A mode, means for operating both the first and second oscillators and controlling the selector circuit to select the output signal of the second oscillator. and control means for stopping the operation of the second oscillator and selecting the output signal of the first oscillator and supplying it to the PWM D/A converter when the audio mode is B mode. Satellite receiver.