JPH03171794A - Manufacture of multilayer circuit board - Google Patents
Manufacture of multilayer circuit boardInfo
- Publication number
- JPH03171794A JPH03171794A JP30903289A JP30903289A JPH03171794A JP H03171794 A JPH03171794 A JP H03171794A JP 30903289 A JP30903289 A JP 30903289A JP 30903289 A JP30903289 A JP 30903289A JP H03171794 A JPH03171794 A JP H03171794A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- epoxy resin
- resin layer
- copper
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000003822 epoxy resin Substances 0.000 claims abstract description 47
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 47
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000002245 particle Substances 0.000 claims abstract description 23
- 239000011889 copper foil Substances 0.000 claims abstract description 20
- 238000007747 plating Methods 0.000 claims abstract description 17
- 229910052802 copper Inorganic materials 0.000 claims abstract description 16
- 239000010949 copper Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910001887 tin oxide Inorganic materials 0.000 claims abstract description 8
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 claims abstract 4
- 229910001870 ammonium persulfate Inorganic materials 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 abstract description 4
- 238000007650 screen-printing Methods 0.000 abstract description 2
- 238000002788 crimping Methods 0.000 description 12
- 239000011888 foil Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910000365 copper sulfate Inorganic materials 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、電気・電子部品を搭載する多層配線基板の
製造方法に関する．
〔従来の技術〕
一般に、電気・電子部品の実装を高密度化するため多層
配線基板が用いられている．従来、かかる多層配線基板
は、それぞれ所定の配線パターンを形成した複数枚のフ
レキシブル基板を、各基板間に絶縁性接着剤（プレプリ
グ）を挟んで重ね合わせ、圧着プレス機で圧着したのち
、所定部分に穴をあけて銅メッキを施し、各基板の所定
配線パターンを電気的に接続することによって作威され
ている．
〔発明が解決しようとする課題〕
ところで、多層配線基板を上記のように圧着プレス機を
用いて圧着により作威する場合には、圧着プレス工程時
の高温により基板が収縮し反りが生ずる．その反りを防
止するためには、ワークサイズ（作業のための外形）を
製品外形に対して上下左右にそれぞれ６０閣以上加える
必要があり、そのため無駄な部分が多くなってしまうと
いう問題点がある．また例えば６層の多層配線基板を作
或するには２回の圧着回数を必要とし、更に８層の場合
は３回というように暦数に比例して圧着回数を増す必要
があり、圧着工程毎に基板は収縮するため、暦数を増や
すにしたがって精度が低下し、したがって暦数には限度
があるという問題点があった．
更に圧着プレス法を用いる場合には、圧着プレス機が非
常に高価であるばかりでなく、圧着の前処理から圧着終
了までの工程が多く広い場所を必要とし、コストダウン
が困難であった。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a multilayer wiring board on which electrical/electronic components are mounted. [Prior Art] Generally, multilayer wiring boards are used to increase the density of electrical and electronic components. Conventionally, such multilayer wiring boards have been made by stacking a plurality of flexible boards, each with a predetermined wiring pattern formed thereon, with an insulating adhesive (prepreg) sandwiched between each board, crimping them with a crimping press, and then crimping them in a predetermined portion. It is made by drilling holes in the board, plating it with copper, and electrically connecting the predetermined wiring patterns on each board. [Problems to be Solved by the Invention] By the way, when a multilayer wiring board is crimped using a crimping press as described above, the board shrinks and warps due to the high temperature during the crimping press process. In order to prevent warping, it is necessary to add more than 60 dimensions to the work size (external shape for work) on the top, bottom, left, and right sides of the product external shape, resulting in a problem that there is a lot of wasted parts. ．． In addition, for example, to make a multilayer wiring board with 6 layers, it is necessary to perform crimping twice, and in the case of 8 layers, it is necessary to increase the number of times of crimping in proportion to the number of calendars, such as 3 times. Since the substrate shrinks each time, the accuracy decreases as the number of calendars increases, and therefore there is a problem that there is a limit to the number of calendars. Furthermore, when using the crimping press method, not only is the crimping press machine very expensive, but there are many steps from pretreatment to completion of crimping, which requires a large space, making it difficult to reduce costs.
このような問題点を解決するために、次のような多層配
線基板の製造方法が考えられる．すなわち第２図に示す
ように、例えば銅張基板１１を用いて、まず第１層目の
配線パターン１２を形成したのち、その配線パターン１
２の表面にエポキシ樹脂をシルク印刷などで塗布してエ
ポキシ樹脂層１３を形成し、次いでこのエポキシ樹脂層
１３に銅メッキを施して銅箔層ｌ４を形成したのち２Ｊ
ｉ１目の配線パターンを形或する．次いで図示は省略す
るが、２層目の配線パターン上に再びエポキシ樹脂を塗
布して、以下上記同一の工程を繰り返して最終層の銅メ
ッキの前に所定部分に穴をあけ、最終層の銅メッキを穴
部分にも施すことによって、各層の所定配線パターンを
接続して多層配線基板を作威するという製造方法が考え
られる．
この製造方法によれば、圧着プレス機を用いなくてもよ
く、工程数も減り広い場所も不要となる．そのためワー
クサイズを小さくでき、また層数を必要なだけ重ねるこ
とができるので大幅なコストダウンの可能性が考えられ
る．
しかしながら、この製造方法では、エポキシ樹脂層１３
と銅メッキによる銅箔層１４の密着力が弱く、配線パタ
ーンが容易に剥離してしまうという問題点がある．この
剥離を防止するため、第３図に示すようにエポキシ樹脂
層１３にブラシやサンドプラスト等で表面に傷を形成し
たのち銅メッキを施す方法が考えられるが、その表面傷
により形成される凹部１３ａは内部に向かって小さくな
る凹部にすぎないので、銅箔層１４とエポキシ樹脂層ｌ
３との接着力はあまり強化されず、エポキシ樹脂層内の
水分が気化する時の圧力で、やはり銅メッキが一部剥離
してしまう．また更にエポキシ樹脂層１３に飼メッキす
る代わりに導体ペーストを塗布して配線パターンを形戒
することも考えられるが、この導体ペーストを用いた場
合は導電性に問題があり、実用できない．
本発明は、従来の多層配線基板の製造方法における上記
問題点を解消するためになされたもので、工程数を低減
し低コストで容易に層数の多い高精度の多層配線基板の
製造方法を提供することを目的とする．
〔課題を解決するための手段及び作用〕上記問題点を解
決するため、本発明は、基板上にエッチングにより溶解
除去可能な不純物粒子を混入したエポキシ樹脂を塗布し
てエポキシ樹脂層を形成し、硬化したエポキシ樹脂層の
表面を研磨したのちエッチングを行い表面に露出した不
純物粒子を溶解除去してエポキシ樹脂層表面に多数の微
小口部を形成し、次いで該微小凹部を形成したエポキシ
樹脂層表面に銅メッキを行ってｍ箔層を形成したのち・
該ｔｉ４箔層に配線パターンを形成し、該配線パターン
上に再び上記エポキシ樹脂を塗布し上記一連の工程を繰
り返して多層配線基板を製造するものである．
このように不純物粒子を混入したエポキシ樹脂層をエッ
チングすることによって、エポキシ樹脂層表面には不純
物粒子の溶解除去による内部が広くなる形状の多数の微
小凹部が形成され、その表面に銅メッキによるｔｉ４箔
層を形戒することにより、銅箔層の一部が前記微小凹部
に入り込み、そのアンカー状作用によりエポキシ樹脂層
とｗ４箔層は極めて強固に接着される．したがってエポ
キシ樹脂層内の水分の気化時の圧力によっても配線パタ
ーンの剥離は全く生じない．モして本角明における製造
工程においては圧着処理を行わないので、工程数が低減
されると共に基板の収縮や反りが発生せず、高槽度で剥
離の生じない層数の多い多層配線基板を低コストで容易
に製造することが可能となる．
〔実施例〕
次に実施例について説明する。第１図八〜（５）は、本
発明に係る多層配線基板の製造方法の一実施例を示す製
造工程図である。まず第１図（ハ）に示すように、基板
として銅張ガラスエポキシ樹脂板１を用意し、通常のホ
トリソグラフィー法等にまり銅箔に１層目の配線パター
ン２を形戒する．次に第１図田）に示すように、前記配
線パターン２上に、酸化錫粒子３（粒径：２００メッシ
ュ）を重量比で１％混入したエポキシ樹脂を、スクリー
ン印刷法で塗布してエポキシ樹脂層４を形或する。In order to solve these problems, the following method of manufacturing a multilayer wiring board can be considered. That is, as shown in FIG. 2, first, a first layer wiring pattern 12 is formed using, for example, a copper-clad board 11, and then the wiring pattern 1 is
An epoxy resin layer 13 is formed by applying epoxy resin to the surface of 2J by silk printing or the like, and then this epoxy resin layer 13 is plated with copper to form a copper foil layer 14.
Shape the i1th wiring pattern. Next, although not shown, epoxy resin is applied again on the second layer wiring pattern, and the same process described above is repeated to make holes in predetermined areas before the final layer copper plating. A possible manufacturing method is to connect the predetermined wiring patterns of each layer to create a multilayer wiring board by applying plating to the holes as well. According to this manufacturing method, there is no need to use a crimping press, the number of steps is reduced, and a large space is not required. As a result, the work size can be reduced and the number of layers can be stacked as required, potentially leading to significant cost reductions. However, in this manufacturing method, the epoxy resin layer 13
There is a problem in that the adhesion of the copper foil layer 14 due to copper plating is weak and the wiring pattern easily peels off. In order to prevent this peeling, it is possible to form scratches on the surface of the epoxy resin layer 13 with a brush or sandplast, etc., as shown in Figure 3, and then apply copper plating. 13a is just a recess that becomes smaller toward the inside, so the copper foil layer 14 and the epoxy resin layer l
The adhesive strength with 3 was not strengthened very much, and the pressure when the moisture in the epoxy resin layer evaporated caused some of the copper plating to peel off. Furthermore, instead of plating the epoxy resin layer 13, it may be possible to apply a conductive paste to shape the wiring pattern, but if this conductive paste is used, there is a problem with conductivity and it is not practical. The present invention has been made in order to solve the above-mentioned problems in the conventional method for manufacturing multilayer wiring boards, and provides a method for manufacturing high-precision multilayer wiring boards with a large number of layers easily and at low cost by reducing the number of steps. The purpose is to provide [Means and effects for solving the problem] In order to solve the above problems, the present invention forms an epoxy resin layer by coating a substrate with an epoxy resin mixed with impurity particles that can be dissolved and removed by etching. After polishing the surface of the cured epoxy resin layer, etching is performed to dissolve and remove impurity particles exposed on the surface to form a large number of micro-holes on the surface of the epoxy resin layer, and then the surface of the epoxy resin layer with the micro-recesses formed therein. After copper plating and forming m foil layer.
A wiring pattern is formed on the TI4 foil layer, the epoxy resin is again applied onto the wiring pattern, and the series of steps described above are repeated to produce a multilayer wiring board. By etching the epoxy resin layer mixed with impurity particles in this way, a large number of micro-concavities are formed on the surface of the epoxy resin layer with the interior becoming wider due to the dissolution and removal of the impurity particles, and the surface of the epoxy resin layer is formed by copper plating. By shaping the foil layer, a portion of the copper foil layer enters the minute recess, and its anchor-like action causes the epoxy resin layer and the W4 foil layer to be extremely firmly bonded. Therefore, the wiring pattern does not peel off at all, even when the pressure is applied when the moisture in the epoxy resin layer evaporates. In addition, since no pressure bonding is performed in the manufacturing process at Honkakumei, the number of steps is reduced, the board does not shrink or warp, and the multilayer wiring board has a large number of layers that does not cause peeling due to high lamination resistance. can be easily manufactured at low cost. [Example] Next, an example will be described. 8-(5) of FIG. 1 are manufacturing process diagrams showing one embodiment of the method for manufacturing a multilayer wiring board according to the present invention. First, as shown in FIG. 1(c), a copper-clad glass epoxy resin plate 1 is prepared as a substrate, and a first layer wiring pattern 2 is formed on the copper foil using the usual photolithography method. Next, as shown in Figure 1, an epoxy resin mixed with 1% by weight of tin oxide particles 3 (particle size: 200 mesh) is applied onto the wiring pattern 2 using a screen printing method. The resin layer 4 is shaped.
次いで前記エポキシ樹脂層４が硬化したのちパフ研磨を
かけて、第１図（Ｃｌに示すように混入されている酸化
錫粒子の一部を露出させる．次に過硫酸アンモニウムを
用いてエポキシ樹脂層表面のエッチングを行って、露出
した酸化錫粒子を溶解除去し、第１図の）に示すように
、エポキシ樹脂層４の表面に多数の微小凹部５を形戒す
る．この微小凹部５の形状は、大部分が図示のように内
部部分の大きさが表面開口部の大きさより大きく形成さ
れる．
次に第１図Ｄに示すように、微小凹部５の形成されたエ
ポキシ樹脂Ｎ４の表面に、硫酸銅を用いて銅メッキを行
い、長さ３０ｔ！ｍの銅箔層６を形成し、この銅箔層６
に対して、同様にホトリソグラフィー法を用いて第２層
目の配線パターン７を形戒することにより、２層構戒の
多層配線基板が得られる．更に図示は省略するが、２層
目の配線パターン上に更に上記エポキシ樹脂を塗布し、
以下同一の工程を繰り返すことにより３層以上の多層配
線基板が得られる．なお穴あけや穴内部のメッキ処理等
は従来と同様に行われる。Next, after the epoxy resin layer 4 is hardened, it is subjected to puff polishing to expose a part of the tin oxide particles mixed in as shown in FIG. The exposed tin oxide particles are dissolved and removed, and a large number of minute recesses 5 are formed on the surface of the epoxy resin layer 4, as shown in Figure 1). As shown in the figure, most of the micro-concave portions 5 are shaped so that the size of the internal portion is larger than the size of the surface opening. Next, as shown in FIG. 1D, the surface of the epoxy resin N4 on which the minute recesses 5 were formed was plated with copper using copper sulfate, and the length was 30 tons! m copper foil layer 6 is formed, and this copper foil layer 6
On the other hand, by forming the second layer wiring pattern 7 using the same photolithography method, a multilayer wiring board with a two-layer structure can be obtained. Furthermore, although not shown, the above epoxy resin is further applied on the second layer wiring pattern,
By repeating the same steps below, a multilayer wiring board with three or more layers can be obtained. Note that drilling and plating inside the holes are performed in the same manner as before.
このような製造工程において、銅メッキを行って銅箔層
６を形成する際、銅箔層の一部がエポキシ樹脂層４の表
面に形成されている微小凹部５に入り込み、この微小凹
部５の形状は先に述べたとおり内部が大となっているの
で、微小凹部５に入り込んだ銅箔層部分６ａは、アンカ
ー状の働きをして、銅箔Ｎ６は極めて強固にエポキシ樹
脂層４に結合される．したがってエポキシ樹脂層４に含
まれている水分の気化時の圧力等によっても、銅箔層６
乃至は配線パターン７が剥離することは完全に阻止され
る．
上記実施例では、基板として、第１層の配線パターンを
形成した銅張ガラスエポキシ樹脂板を用いたものを示し
たが、基板としては、単なる絶縁板やあるいは金属板も
用いることができ、更には電気・電子装置の筐体部分等
を基板として用い、その表面に多層配線層を形戒するこ
とも可能である．また基板の片面のみならず、上下両面
上に同様な工程で多層配線層を形成して多層配線基板を
構戒することもできる．
また上記実施例では、エポキシ樹脂に混入する酸化錫粒
子の混入率は重量比で１％としたものを示したが、対比
のための２％の重量比としたエポキシ樹脂層を形成して
みたところ、表面に粒子の凹凸が出てしまい不適切であ
り、１％の方が凹凸がなく、より適切であることが判明
した．また銅箔層はピロ銅メッキでも形戒できるが、ビ
ロ銅メッキによるｗ４ｆ５層で形成した配線パターンに
は若干剥離がみられ、上記実施例のように硫酸銅メンキ
による銅箔層の方が適切であることが判明した．また上
記実施例では、エポキシ樹脂に混入する不純物粒子とし
て酸化錫粒子を用いたものを示したが、これに限らず例
えば酸化銅粒子等も用いることができ、それらの混合粒
子に対応したエッチング液を用いることにより、エポキ
シ樹脂層表面に同樺な微小凹部を形戒することができる
．〔発明の効果〕
以上実施例に基づいて説明したように、本発明によれば
、不純物粒子を混入したエポキシ樹脂層をエッチンダレ
て表面に微小凹部を形成したのち銅メッキによるｗ４箔
層を形戒する工程を繰り返すようにしている．ので、圧
着処理工程に伴う基板の収縮や反りが発生せず、またエ
ポキシ樹脂層と銅箔層は微小凹部を介して強固に結合さ
れ、したがって高精度で剥離の生じない多層配線基板を
低コストで容易に製造することができる．In such a manufacturing process, when copper plating is performed to form the copper foil layer 6, a part of the copper foil layer enters the minute recess 5 formed on the surface of the epoxy resin layer 4, and the minute recess 5 is Since the shape is large inside as described above, the copper foil layer portion 6a that has entered the minute recess 5 acts as an anchor, and the copper foil N6 is extremely firmly bonded to the epoxy resin layer 4. It will be done. Therefore, the copper foil layer 6 may
In other words, peeling of the wiring pattern 7 is completely prevented. In the above embodiment, a copper-clad glass epoxy resin plate on which a first layer wiring pattern is formed is used as the substrate, but a simple insulating plate or a metal plate can also be used as the substrate. It is also possible to use the casing of an electrical or electronic device as a substrate and form a multilayer wiring layer on its surface. Furthermore, it is also possible to form a multilayer wiring board by forming multilayer wiring layers not only on one side of the board but also on both the top and bottom sides in the same process. In addition, in the above example, the proportion of tin oxide particles mixed in the epoxy resin was set at 1% by weight, but for comparison, an epoxy resin layer was formed at a weight ratio of 2%. However, it was found that 1% was more suitable because it had no unevenness on the surface. In addition, the copper foil layer can be formed using pyro-copper plating, but the wiring pattern formed with the W4F5 layer using pyro-copper plating has some peeling, so a copper foil layer using copper sulfate coating as in the above example is more appropriate. It turned out to be. Further, in the above embodiment, tin oxide particles were used as impurity particles mixed into the epoxy resin, but the present invention is not limited to this, and for example, copper oxide particles can also be used, and an etching solution compatible with these mixed particles can be used. By using this method, it is possible to form microscopic depressions on the surface of the epoxy resin layer. [Effects of the Invention] As described above based on the embodiments, according to the present invention, after etching the epoxy resin layer mixed with impurity particles to form minute recesses on the surface, a W4 foil layer formed by copper plating is formed. I try to repeat the process. Therefore, shrinkage and warping of the board due to the crimping process does not occur, and the epoxy resin layer and copper foil layer are firmly bonded through minute recesses, making it possible to create a multilayer wiring board with high precision and no peeling at a low cost. It can be easily manufactured.
第１図（自）〜（ト）は、本発明に係る多層配線基板の
一実施例の製造工程を示す図、第２図及び第３図は、本
発明に至る過程において考慮された多層配線基板を示す
断面図である．
図において、１は銅張ガラスエポキシ樹脂板、２は１層
目配線パターン、３は酸化錫粒子、４はエポキシ樹脂層
、５は微小凹部、６は銅箔層、７は２層目配線パターン
を示す．FIGS. 1(A) to (G) are diagrams showing the manufacturing process of an embodiment of the multilayer wiring board according to the present invention, and FIGS. 2 and 3 show the multilayer wiring considered in the process leading to the present invention. FIG. 3 is a cross-sectional view showing the board. In the figure, 1 is a copper-clad glass epoxy resin board, 2 is a first layer wiring pattern, 3 is a tin oxide particle, 4 is an epoxy resin layer, 5 is a minute recess, 6 is a copper foil layer, and 7 is a second layer wiring pattern. is shown.
Claims (2)
子を混入したエポキシ樹脂を塗布してエポキシ樹脂層を
形成し、硬化したエポキシ樹脂層の表面を研磨したのち
エッチングを行い表面に露出した不純物粒子を溶解除去
してエポキシ樹脂層表面に多数の微小凹部を形成し、次
いで該微小凹部を形成したエポキシ樹脂層表面に銅メッ
キを行って銅箔層を形成したのち該銅箔層に配線パター
ンを形成し、該配線パターン上に再び上記エポキシ樹脂
を塗布して上記一連の工程を繰り返すことを特徴とする
多層配線基板の製造方法。1. An epoxy resin layer is formed by coating the substrate with epoxy resin mixed with impurity particles that can be dissolved and removed by etching, and the surface of the hardened epoxy resin layer is polished and then etched to dissolve and remove the impurity particles exposed on the surface. to form a large number of minute recesses on the surface of the epoxy resin layer, then perform copper plating on the surface of the epoxy resin layer on which the minute recesses have been formed to form a copper foil layer, and then form a wiring pattern on the copper foil layer, A method for manufacturing a multilayer wiring board, characterized in that the epoxy resin is applied again onto the wiring pattern and the series of steps described above are repeated.
ンモニウムを用いてエッチングを行うことを特徴とする
請求項１記載の多層配線基板の製造方法。2. 2. The method of manufacturing a multilayer wiring board according to claim 1, wherein tin oxide particles are used as the impurity particles and the etching is performed using ammonium persulfate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30903289A JPH03171794A (en) | 1989-11-30 | 1989-11-30 | Manufacture of multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30903289A JPH03171794A (en) | 1989-11-30 | 1989-11-30 | Manufacture of multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03171794A true JPH03171794A (en) | 1991-07-25 |
Family
ID=17988061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30903289A Pending JPH03171794A (en) | 1989-11-30 | 1989-11-30 | Manufacture of multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03171794A (en) |
-
1989
- 1989-11-30 JP JP30903289A patent/JPH03171794A/en active Pending
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