JPH03171630A - Semiconductor device and manufacture thereof as well as wiring film formation device - Google Patents

Abstract

PURPOSE:To enable a metallic wiring resistant to electromigration and stressmigration to be formed by a method wherein a metallic electrode or wiring is provided with a barrier film in specific thickness comprising a material not reactive to the material of the metallic electrode or wiring buried so as to separate the inside thereof either in the film thickness direction or in the axial direction. CONSTITUTION:A specific element is formed in a silicon substrate 1 and the surface of the element is covered with an insulating film 2 such as a silicon oxide film etc. A required contact hole is made in the insulating film 2 so as to form a metallic wiring 3 on the hole. The metallic wiring 3 is lamination-structured comprising the first layer metallic film 31 and the second layer metallic film 32 as well as a barrier film 33 buried between the two films 31 and 32. The first and second layer metallic films 31 and 32 are Al film or Al alloy film while the barrier film 33 is an Al oxide film. As for the barrier film 33, in addition to the Al oxide, the other material in low reactivity to Al e.g. Al nitride, carbide, boride, etc. are applicable. Furthermore, the preferable thickness D3 of the barrier film 33 is to be within the range of 1-50nm and more preferably 2-10nm.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a semiconductor device and a method for manufacturing the same, specifically a metal wiring structure of a semiconductor device and a method for forming the same, and further relates to a metal wiring structure for a semiconductor device and a method for forming the same. This invention relates to a wiring film type device.

(Prior Art) High-density integration and high-speed semiconductor integrated circuits have been achieved primarily through miniaturization of elements. One of the major issues that has become a problem with the miniaturization of device dimensions is the reliability of metal wiring. Failure occurrence modes in miniaturized metal wiring in semiconductor devices can be broadly divided into two types. One is electromigration and the other is stress migration. Electromigration is
This occurs due to the increased current density in the metal wiring.

In addition to miniaturization of wiring width, the current density in wiring tends to become higher due to high-speed operation of devices, which deteriorates electromigration resistance. Since the life of a wiring due to electromigration is inversely proportional to the current density, for example, if the wiring width is reduced to 1/2 and the current density is doubled, the wiring life will be reduced to 1/4. Stress migration is a creep rupture mode that occurs due to an increase in mechanical stress applied to wiring. This mechanical stress is caused by the difference in expansion coefficient between the wiring and the insulating film used to protect it, and tends to increase as the wiring width becomes finer. In the case of Aρ wiring, which is often used as wiring in semiconductor devices, when the wiring width is reduced to 1/2, the stress applied to the wiring becomes approximately twice as large. The life of the wiring due to this stress migration is n of the wiring width.
In proportion to the power of (n-3 to 4), the miniaturization of the wiring width causes a significant reduction in the wiring life.

Conventionally, Al films have been widely used for metal wiring in semiconductor devices, for reasons such as ease of film formation and processing, low resistance, and ease of forming contact with a silicon substrate. However, Afi wiring has low activation energy for atomic movement due to its low melting point, and has low resistance to the above-mentioned electromigration and stress migration. Several countermeasures have been proposed in the past to deal with such deterioration in reliability of fine wiring.

The first method is to use an Al alloy film to which metals such as Cu, Ti, and Pd are added as the Ap wiring.

The effectiveness of this has been confirmed on a practical level as well.

The reason why the An) alloy film is effective is that intermetallic compounds of All and other metals precipitate and are scattered at the grain boundaries that are always included in the wiring. That is, electromigration is the movement and diffusion of L atoms along grain boundaries at high current density, and the intermetallic compound precipitated at the grain boundaries functions as a barrier against the movement of Afl atoms. However, Ap alloy film wiring is not as effective against stress migration as electromigration. Stress migration resins mainly occur at bamboo node-shaped grain boundaries (bamboo grain boundaries) that cross the wiring layer. This is because the stress applied to bamboo grain boundaries is greater than that of grain boundaries with normal 3ffi points. Of course, intermetallic compounds precipitate at bamboo grain boundaries in 1-alloy wiring, but
The precipitation is not uniform, and the number of bamboo grain boundaries increases due to refinement, which is considered to be the reason why alloying does not have a sufficient effect on stress migration. In order to increase the effect on stress migration, it is conceivable to increase the concentration of the added metal, but this is not a realistic countermeasure. This is because if the added metal concentration is too high, workability will decrease, wiring resistance will increase, and precipitated particles will grow large, promoting non-uniformity of Ag atomic movement and making electromigration more likely to occur. .

The second method is to use an An) film and another metal film such as a W film. The method is to utilize a laminated structure with a Ti film or the like. For example, a structure is used in which another metal film is interposed in the middle part of the Al film in the film thickness direction. With such a wiring structure, even if voids occur, the Ag film is divided vertically, which reduces the probability that they will connect in the film thickness direction, improving resistance to electromigration. . Furthermore, since the bamboo grain boundaries are also separated by the intermediate metal layer, stress effects at the grain boundaries are alleviated. This, combined with the fact that the intermediate metal layer itself has the function of relieving stress, makes it resistant to stress migration. However, this method also has the following drawbacks: (1) The presence of the intermediate metal film increases wiring resistance.

In particular, when an intermetallic compound is formed between the intermediate metal film and the Ag film, the wiring resistance becomes even higher.

(2) The intermetallic compound between the intermediate metal film and the Al film may react with the silicon substrate and destroy the contact portion. This becomes a particularly serious problem when Tilli is used as the intermediate metal. That is, since there are stable ternary intermetallic compounds AN2Ti and Si7, A, IJ-St (1%)
Even if wiring is used, the St in the AI alone is not sufficient and reacts with the silicon in the contact portion, causing a defect called contact breakdown. ■Focusing only on the upper layer All film, we get
The presence of the intermediate metal film reduces the grain size, and the upper J
WIM1! The electromigration resistance of This reduces the reliability of the Afi wiring as a whole. (2) Volume shrinkage occurs when an intermetallic compound is formed between the AIM and the intermediate metal film, and minute defects are induced between the parent phase Al and the intermetallic compound film. As a result of accelerated atomic diffusion along this defect, resistance to electromigration is not as great. (2) A local battery is formed inside the wiring between the Afi film and the intermediate metal film, reducing corrosion resistance.

The third method is Al or A proposed by Abe et al.
This is a method in which an AI oxide film is interposed inside the 47 alloy film wiring (for example, Japanese Patent Application Laid-Open No. 1983-13740). Aj) After depositing the film, an AI oxide film is formed on the surface by exposing it to the atmosphere, heating it in the atmosphere, or washing it in pure water, and then depositing the Δρ film on it again. By depositing , the mechanical strength of the AJ wiring is strengthened. This method is certainly effective for electromigration. However, this method has the disadvantage that the wiring resistance becomes higher than that of the method using an intermediate metal film.

Further, contact resistance increases in the contact portion.

Furthermore, in the above-mentioned method of forming an Ap oxide film, in which the film is exposed to the atmosphere after forming the AI film, the thickness controllability of the Ap oxide film is not sufficient, and it is difficult to obtain an AI oxide film with a thin and uniform thickness. Have difficulty.

(Problem to be solved by the invention) As described above, in the metal wiring in the conventional semiconductor device,
Electromigration and stress migration have become serious problems as devices become smaller, but none of the countermeasures proposed so far have been sufficient.

An object of the present invention is to provide a semiconductor device having metal wiring that has excellent electromigration resistance and stress migration resistance.

Another object of the present invention is to provide a method for manufacturing a semiconductor device having a metal wiring formation process with excellent electromigration resistance and stress migration resistance.

Still another object of the present invention is to provide a wiring film forming apparatus capable of forming metal wiring of a semiconductor device with excellent electromigration resistance and stress migration resistance.

[Configuration of the Invention (Means for Solving the Problems)] A semiconductor device according to the present invention has a semiconductor device in which a metal electrode or wiring formed on a semiconductor substrate on which an element is formed with an insulating film interposed therebetween in the direction of its film thickness. Or a thickness of 1 made of material that does not react with the wiring material and is buried so as to divide the wiring in the width direction.
~50 nm (more preferably 2~10nff+)
It is characterized by having a barrier film of.

In the method for manufacturing a semiconductor device according to the present invention, when forming metal wiring via an insulating film on a semiconductor substrate on which an element is formed, a first layer metal film, a barrier film made of a material different from this metal film, The present invention is characterized in that at least three layers of the second layer metal film are successively laminated without exposing the hood board to the atmosphere, and then the laminated film is buttered.

In the wiring film forming apparatus for semiconductor devices according to the present invention, the first to third film forming chambers for forming the above-mentioned first layer metal film, #wall film, and second layer metal film respectively have a gate valve. These film forming chambers are connected to each other through the film forming chambers, and the substrates are sequentially transferred through these film forming chambers so that film formation can be performed continuously without exposing the substrates to the atmosphere.

(Function) In the semiconductor device according to the present invention, by interposing a very thin barrier film inside the metal wiring, the electromigration resistance and stress migration resistance of the gold 1tA wiring can be improved without increasing the wiring resistance or contact resistance. can be improved. Barrier film is 1na+
If it is thinner, the effect of suppressing the growth of voids generated in the wiring cannot be obtained sufficiently due to variations in film thickness. Therefore, to obtain the effect as a barrier film, Inffl
As mentioned above, a film thickness of preferably 2 nm or more is required. Furthermore, if the thickness of the barrier membrane exceeds 50 nta, the increase in wiring resistance cannot be ignored, so the thickness is set to 50 nm or less, particularly preferably 10111 nm or less. Further, the barrier film needs to be a stable substance that does not react with the wiring material [1], thereby preventing an increase in wiring resistance due to the formation of intermetallic compounds or the like.

? According to the method and wiring film forming apparatus of the invention, the laminated structure of metal film/barrier film/metal film is continuously formed without exposing the substrate to the atmosphere, so that the adhesion between the laminated films and the film thickness can be controlled. It is possible to create highly reliable metal wiring with excellent performance.

(Failure to practice) Hereinafter, a major embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a metal wiring structure of a semiconductor device according to one embodiment. Desired elements are formed on a silicon substrate 1, and its surface is covered with an insulating film 2 such as a silicon oxide film. Necessary contact holes are made in the insulating film 2, and metal wiring 3 is formed thereon. In this embodiment, the metal wiring 3 has a laminated structure in which a barrier film 3.3 is embedded between a first metal film 31 and a second metal film 3. 1st
Is the layer metal film 31 and the second layer metal film 3■ made of AI? film or Aρ alloy film, and the barrier film 33 is an AfI oxide film. In addition to AN oxide, other materials having low reactivity with AN, such as nitrides, carbides, borides, etc., can also be used as the barrier film 3. The thickness D of the barrier film 3 is 1 to 5
The range is 0 nm, more preferably 2 to 10 nI1.

The reason why the thickness of the barrier film is set within such a range will be explained with reference to FIG. Figure 12 shows that in this example 0.2μ
AfI20 is interposed between two layers of 1-1% Si-0.5% Cu, and the film thickness is varied in the range of 0.5 to 14 nm, and the via hole resistance with the underlying Al-Si-Cu wiring is measured. This is the result. Also, AI? Similar results were also shown when A47N was used instead of 203. The lower layer Aρ-Si-Cu is All-1X S
i-0.2% Cu or AI-1%Si-0.5
%Cu. The wiring width is 0.4 μm. Using ArF excimer laser phosphorography technology and oxidation MRIE technology on the plasma TEOS film on the wiring,
．． Inspect the 4 μm aperture and first insert a 0.2 μm A, l/
-1% Si -0.2% Cu film is sputtered. Next, move to the AfI20i formation chamber, flow oxygen by ISCCM, and adjust the exhaust capacity of the turbo molecular pump with a conductance valve to increase from IX10'Pa to 1.3X10-2Pa.
The temperature is maintained at room temperature to 300° C. for 5 to 100 seconds to form an AN20i film of 0.5 to 14 na. Substrate heating is used when forming an Ag203 film of 3 nm or more. For example, under a partial pressure of 1.3X10-'Pa at room temperature, A
l -IX S f - (3 nm on 1.5% Cu
of Ag20i grows during 90 sec. Next, move to the second layer Aρ-Si-Cu formation chamber, and
Spatter m of A,ill-1%Si-0.5%Cu. After this, using ArF excimer laser lithography technology and BCff3 CD2 He-based RIE technology, 0
6 Process to a width of 3 to 0.5 μm.

The resistance of 10,000 via holes obtained after teno-sintering at 450°C for 30 minutes in Nz -10% H2 is shown in terms of resistance per unit area. The wiring width of this data is 0.5 μm. Also, in the same figure, N2'+1,15
AN2 alone on Sin2 after 3000 hours at 0°C
0i laminated wiring resistance (wiring length III1) is also shown. From the figure, the via hole specific contact resistance shows an increase with the AR20i thickness, and for 1na+ IX10-8Ωcm2 (
0.9Ω per 0.4μm via hole) 10
In nm, it is 1×10 Ωcm2 (6.3 Ω per 0.4 μm via hole). Therefore, an Aρ203 thickness of 5 nm or less is preferred for very low resistance contacts.

However, depending on the sintering conditions, an A of 8 to 10 Il
Even with the II203 film, a via hole resistance of 10-' to 10-'ΩcnI2 was obtained, and it was found that there was no problem in practical use. On the other hand, 150℃. The wiring resistance after 3000 hours is AN
4 to 5 before stress application when the 203 film thickness is less than 1 nIm.
Increase more than twice. Therefore, the thickness of An2's has an upper limit and a lower limit.

Exactly the same thing can be done with AIN instead of Af)20iH
This also applies when membranes are used.

The fact that the metal wiring structure according to this embodiment has high mechanical reliability will be explained using FIGS. 3(a) and 3(b). In this case, there are bamboo grain boundaries 5 that cross the wiring in the film thickness direction as shown in the figure.On the other hand, Fig. 3<a) shows the wiring structure of this example. Since the barrier film divides the wiring layer vertically, the grain boundaries 4 are also divided vertically.

Furthermore, in this case, the presence of the barrier film 3 reduces the average grain size of each AI film and forms many grain boundaries. Therefore, considering the case where tensile stress is applied in the direction of the wiring length, in the structure shown in FIG. 3(b), this load is concentrated on the bamboo grain boundaries 5, and creep occurs at such grain boundaries 5. This is the original prisoner of stress migration. On the other hand, in the case of this embodiment, the stress is dispersed as shown in FIG. 3(a), so that the mechanical strength is improved.

This phenomenon in which stress is dispersed and mechanical strength is improved is similar to that expressed by the relationship between the strength of structural materials and grain boundaries, known as the Ball-Betts equation. The Paul-Petch equation is an empirical equation that states that the yield strength σ of a material and the grain size d of the material have a relationship of σ,−σo−kd−′·2.

Furthermore, since the wiring structure of this example eliminates bamboo grain boundaries as described above, it exhibits strong resistance to electromigration.

Further, in this embodiment, the barrier H3 is extremely thin, so that increases in wiring resistance and contact resistance due to the interposition of the wall film 33 are suppressed to a negligible level.

By the way, the barrier film 33. Regarding the position where the
It is desirable to select such that 2/W does not become 1. In the case of single-layer wiring, when examining the relationship between aspect ratio and stress, there is a relationship as shown in Figure 4, where the aspect ratio is 1.
This is because the wiring stress reaches its maximum value at the point. Therefore, when the aspect ratio of the wiring as a whole is 1 or a value close to this, by interposing a barrier film to shift the aspect ratio of the upper and lower layers from 1, the wiring stress can be reduced and the mechanical strength can be increased. can be raised.

Describe specific experimental data. Covered with oxide film? Ap-Si-Cu films were used as the first and second metal films 3, 3, and 3nI as the barrier film 3 on the silicon substrate.
The overall film thickness is 400 by using 1 A and Q oxide films.
A wiring with a wiring width of 1 μm and a wiring length of 6 m was formed.

A stress test was conducted in which this sample was left in an atmosphere at 150° C. for 5000 hours.

As a comparative example, a similar test was conducted using a sample in which wiring was formed using a single layer of A,77-Si-Cu film. Defective rate in comparative example: 80
%, whereas in this example, the defective rate was zero.

FIG. 2 shows the wiring structure of another embodiment. Portions corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. In the embodiment shown in FIG. 1, a barrier film 33 is interposed so as to divide the metal wiring in the thickness direction, whereas in this embodiment, a barrier film 33 is interposed so as to divide it in the width direction. In this embodiment as well, the thickness W of the barrier film 3 (measured in the lateral direction) is 1 to 50 nI, preferably 2 to 10 nI1.

Moreover, the position of the barrier film 3 is also determined by the aspect ratio of the two wiring films to be divided: D/W +D/W
It is preferable to choose so that 2 does not become 1.

This embodiment also provides the same effects as the previous embodiment.

In the above embodiments, A and Q-based wiring materials were used, but the present invention is also effective for wiring made of other metals such as Cu, W, and Au. In addition, in the example, an example was shown in which one barrier film is provided in the wiring, but it may also be formed in the contact electrode that contacts the impurity layer formed on the substrate surface, or two or more layers may be formed depending on the wiring film thickness, etc. It may be provided.

Figure 13 shows Aj! FIG. 2 is a schematic cross-sectional view of a case where a 203 laminated wiring and an AgN laminated wiring are applied to a multilayer wiring.

An insulating film 102 is formed on an St substrate 101, a contact hole is opened to form an impurity diffusion layer 103, a first plug electrode (for example, W) 104 is formed by CVD,
Then the first All/An) 203/AI
? CAD is made of pure Afi or alloy) wiring 105 is formed, and an insulating film 106 is deposited. After opening the via hole, the second
The plug electrodes 107 and 108 are shaped, and then the second plug electrodes 107 and 108 are formed.
Ag/Aj? 203/Ail wiring is formed. In exactly the same way, instead of AI+203, one using A,9N is formed. When laminated wiring is used in a multilayer structure, it is possible to create long wiring that is extremely resistant to stress from interlayer films.

Next, an embodiment of a method for forming metal wiring in a semiconductor device according to the present invention and a wiring film forming apparatus used in the method will be described.

FIG. 5 shows the basic layout of the wiring film forming apparatus used in the example. A gate valve 12a partitions into a first film-shaped chamber 11a, a second film-forming chamber 1lb, and a third film-forming chamber 11C.
．． 12b. Each film forming chamber 11a~
11C is a mutually independent exhaust system H, and a pump 14a is connected to the pump 14a through gate valves 13, 13b, 13c as shown in the figure.
, 14b, 14c are connected. Bomb 14a~1
4C Haya turbo molecular pump (cryobomb may also be used)
It is. First film forming chamber 11a and third film forming chamber 1
In this embodiment, 1C is a sputtering chamber for the AI film, and each chamber is provided with 15.18 inert gas rods such as A'. The second film forming chamber is an oxygen plasma treatment chamber for forming an Al oxide film on the surface of the Al film, and is provided with an inert gas inlet 16 and an oxidizing gas inlet 17 such as oxygen or water vapor. It is being The substrate on which a film is to be formed can be moved between each film forming chamber by a conveyor belt without being exposed to the atmosphere.

FIG. 6 shows a more specific configuration of the film forming apparatus. Fifth
In the basic configuration shown in the figure, a substrate introduction chamber 11d is provided in the first film forming chamber 11a via a gate valve 12c, and a substrate unloading chamber 11e is provided in the third film forming chamber 11c via a gate valve 12d. is provided. By providing the substrate introducing chamber 11d and the substrate unloading chamber 1'le in this manner, the film forming chamber is not exposed to the atmosphere when substrates are taken in and out, and a high vacuum can be maintained. Bumps 14d and 14e are also provided in the substrate introduction chamber lid and the substrate removal chamber 11e via gate valves 13d and 13e, respectively. Also, in FIG. 6, a roughing pump 20a consisting of a rotary bomb/mechanical booster bomb is shown.
~20e has gate valves 21a~21e in each chamber
It shows that it is provided through. The roughing bombs 20a-20e are also connected to pumps 14a-14e, respectively, via gate valves 19a-19e.

Specifically, Ap alloy film/A
A structure consisting of a laminated structure of l oxide film/AD alloy film! ! 9! The case of forming a film will be explained. A silicon substrate on which an element has been formed, an oxide film formed on its surface, and a contact hole formed therein is prepared, and this is installed in the plate introduction chamber lid, the valve 21d is opened, and the roughing bomb 20d is used. The inside of this substrate introduction chamber 11d is evacuated to approximately IPa. Thereafter, the valve 21d is closed, the valve 19d is opened, and the substrate introduction chamber 1 is moved by the turbo molecular pump 14d.
Reduce the pressure inside d to about IXIO-'Pa. Thereafter, the valve 12c is opened and the substrate is transferred to the ml film forming chamber 11a. By this time, the first to third film forming chambers 11a to ll
c and the substrate unloading chamber 11e have already been reduced to about 1xlO-5Pa. Then, 30 to 403 CCM of Ar gas is introduced into the first film forming chamber 11a, and a pressure of about 0.5 Pa is applied to the L, DC magnetron sputtering method (5ooV
, 3A) of 200 nm All-Si
(1%)-C u (0.5%) film is formed. The purity of the target was 99.9991%, and the film deposition rate was 1.
0 to 15 ni/sec.

The substrate on which the A and Q alloy films were formed in this way was then transported to the second film formation chamber 1lb, where oxygen gas was introduced into the IOOSC.
CM is introduced and the pressure is set to 15 Pa, and oxygen plasma is generated by RF discharge of 500 W. The substrate is exposed to this oxygen plasma for 60 seconds and the supply of oxygen gas is stopped. This results in approximately 3 nm of AI on the A,9 alloy film! Oxide M (A
, 9 2 0 3 films) are formed.

Next, the substrate is transferred to the third film forming chamber 11c, and Ap-Si-Cu is coated under the same conditions as in the first film forming chamber 11a.
Deposit 200 films.

By such a sequence, A I S s I C
u (200nm)/Al) 2 0* (3n
A three-layer structure of m)/AfI-S i -C u (200 nm) is obtained. By patterning this laminated film through a PEP process, a desired gold-flex wire can be obtained.

FIG. 7 is a sectional view showing the obtained horizontal wiring. A first layer is formed on a silicon substrate 31 covered with an oxide film 32.
An alloy film 33, an A, Q 203 film 34, and a second layer Ag alloy film 35 are laminated. The surface of the second layer All alloy film 35 is exposed to 2 to 6 nII by taking it out into the atmosphere.
Aj)203 film 36 of 1 is formed. The uniformity of the Al)20s film 34 as a barrier film was ±0.3 nwfM degree, and even in the case of 24 films formed in succession, the uniformity was about ±0.5 nm. Upper and lower Al alloy films 35.
33 is completely separated by the AD203 membrane 34,
Grain boundaries 37 are also divided as shown. As a result of this, a wiring resistant to stress migration and electromigration was obtained. A1203 which is a barrier membrane 34
In the range of 2.5 to 3.5 n■, the upper and lower A47 alloy films 35.33 are electrically connected with low resistance, and the sheet resistance of the wiring as a whole is as low as 0.0075 Ω/hole. Ta. When forming such a laminated wiring structure on a large number of substrates, 7J■, in which one substrate is placed in each of the first to third film forming chambers, is preferable in order to increase throughput. The time required to form the film on one substrate was about 1 hour. By improving the gas introduction method and exhaust capacity, this time can be shortened to 30 to 40 minutes. Note that when film formation is performed in such a sequence, Ai)2
03 The oxygen in the second film forming chamber 1lb in which film formation is performed is the first.
It is necessary to prevent the particles from entering the third film forming chambers 11a and 11C, and thereby A and Q alloy films without cloudiness can be obtained.

After processing the laminated film obtained in this example into a wiring having a width of 0.3 to 2 μm, electromigration and stress migration tests were conducted. The results are shown in FIGS. 8 and 9.

FIG. 8 is a plot of electromigration (abbreviated as EM) average life versus interconnect width. The conventional example shown in the figure is an AI-St-Cu single layer <400
This is the case for wiring of 100 nm). The test conditions were 150℃, 2
MA/cm2. As is clear from the figure, the life of this embodiment is improved by more than one order of magnitude compared to the conventional example. FIG. 9 shows the stress migration (abbreviated as SM) test results, and the test conditions were 180° C. and standing in N2. In this stress test, this example was improved by more than one order of magnitude compared to the conventional example. Note that the average lifespan in this case is determined from the percentage of disconnections, not the result of direct measurement.

For comparison, samples A1 and Al - were prepared by spatter-forming an Al-Si-Cu film, then exposing it to the atmosphere to form an A1203 film on the surface, and then forming an Al-Si-Cu film again on top of it. After forming the Si-Cu film by spatter,
Once this is taken out, it is treated with Al2o using an oxygen plasma device.
, a film was formed thereon, and then an AI-Si-Cu film was formed again to prepare sample B.

The A120sH in sample A was 2 to 6 nm, and the A120 in sample B was 4 to 8 nflI. In both cases, the uniformity is poorer than in the above embodiments. Partially 1 in sample B
There were some areas where the film thickness was 0 nm or more, and when a fine pattern was formed, there were areas where the sheet resistance was extremely large. Furthermore, as a result of examining the chain contact resistance, a large contact resistance increase of 3 to 10 times was observed. From the above, it can be seen that continuous film formation without exposing the substrate to the atmosphere as in this example is extremely important in forming a thin and highly uniform barrier film.

Aβ20sH of barrier film can be improved by methods other than oxygen plasma oxidation.
can be formed. Some examples of such an A1203 film forming method will be described.

Although the basic configuration of the entire film forming apparatus is the same as that shown in FIGS. 5 and 6, the specific configuration of the second film forming chamber 1lb is different.

One method utilizes oxidation by lamb annealing.

The substrate on which the All alloy film has been formed in the first film forming chamber 11a is transferred to the second film forming chamber 1lb, where 1005 CCM of oxygen gas is introduced and the pressure is 15 Pa, and the substrate is heated at 300° C. for 1 minute by lamp heating. do. Thereafter, an Afi alloy film is formed again in the third film forming chamber 11c. The AN203 film as a barrier film formed by this method has a thickness of 3 to 4 nm.

The next method is ion beam oxidation. After the substrate is transferred to the second film forming chamber 1lb, the substrate is irradiated with an oxygen ion beam using a plasma ion gun using Ar gas as a carrier gas. The irradiation conditions are an ion current of 10 mA/mark 2, an acceleration voltage of 1 kV, and a duration of about 1 minute. This results in 2 to 2.5
A nanometer AI' 203 film is obtained.

The next method is to irradiate an oxygen ion beam at the same time as low-speed Ag sputtering. After the substrate is transferred to the second film forming chamber 1lb, 30 S CCM of A' gas is introduced, and an oxygen ion beam is irradiated while sputtering a 99.999% high purity Aρ target at a low speed. By setting the oxygen ion current to 1 to 5 mA/cm and the deposition rate of the 2AN film to about 1 to 2 ns/IIin, the thickness of the thin ANzOi film can be controlled by sputtering.

? The method is steam oxidation. Second film forming chamber 1lb
After transporting the substrate to the
0 steam is introduced at a small flow rate of about IOSCCM, and the pressure is 20
The substrate is heated to 50 to 100°C using Pa. Thereby, an AR203 film of 1.5 to 2.5 nm can be obtained with good controllability.

In addition to these methods, there is also a method of forming an A#20i film by sputtering one target with an Ar-0 mixed gas;
l) Use the zoi target to convert this to A'gas or A
A method of forming an AN20i film by sputtering with r-02 mixed gas, etc. can be used.

By applying the above-described All 2 03 film forming method to a continuous film forming method and apparatus for A, Q alloy/A 1) 2 0 3 / AI alloy, highly reliable wiring can be obtained. .

In the examples of continuous film formation so far, the case where Aρ alloy film was used as the wiring material was explained, but the same continuous film formation method and apparatus are also effective when using other metal films. . An example using a Cu film will be specifically described. The device structure is basically the same as that shown in FIGS. 5 and 6. A silicon substrate on which an element has been formed and covered with an oxide film is introduced into the first film forming chamber 11a, and a
Introducing CCM and setting the internal pressure to 0.5 Pa to 99.99
A 200n- Cu film is formed on the substrate by sputtering a 99% high purity Cu target using a DC magnetron sputter. Next, the substrate was transferred to the second film forming chamber 1lb, and a 99.99'99% high purity A#20i target was sputtered by RF magnetron sputtering.
A 2-3 ns AIl20* film is formed on the Cu film. Further, the substrate is transported to the third film forming chamber 11c, and the substrate is transferred to the first film forming chamber 1. A Cu film of 200 μm is formed in the same manner as in 1a. Cu/AN thus laminated on the substrate
The 20i/Cu laminated film is patterned to obtain desired wiring.

FIG. 10 shows the wiring structure obtained by this length embodiment. The surface of the silicon substrate 41 is covered with a silicon oxide film 42, on which an M1 layer Cu film 43, an A120i
A film 44 and a second layer Cu film 45 are laminated. As shown in the figure, the grain boundaries 46 are separated by the AN203 film, and the bamboo grain boundaries disappear.

The metal wiring obtained in this example is similar to A of the previous example.
l alloy/Aff20q/Aj) It is longer than the alloy laminated wiring, and the sheet resistance is 0.045 to 0.05Ω/
A low-resistance wiring called the mouth was obtained.

Cu is Al, AN-S i, AI-S i-Cu
It has a melting point 350 to 400°C higher than that of , and therefore has a small self-diffusion coefficient. Diffusion in the bulk is slow, but the surface diffusion coefficient is large, so intervening an A120* film as a barrier film to divide the grain boundaries effectively suppresses the surface-enhanced diffusion of Cu that accompanies grain length. It is effective for the upper body. Therefore 70
Stable wiring can be obtained even at high temperatures of 0 to 800°C.

Since Cu is more easily oxidized than Aρ, the method of the present invention in which an Al)zos film as a barrier film is interposed in the middle by continuous film formation without exposing it to the atmosphere is very effective in obtaining stable wiring. be.

Note that the wiring obtained in this example can be made even more reliable by covering the surface of the second layer Cu film and the side surface of the wiring with an A120s film.

In the embodiments of the continuous film forming method and apparatus described above, DC magnetron scattering was used to form the metal film, but other methods such as ECR plasma scattering, ion beam scattering, ion beam assisted scattering, RF
Subatta etc. can be used. It is also possible to use a film deposition method such as a CVD method.

In the above embodiments, the metal film, barrier film, and metal film are formed in separate film formation chambers without exposing the substrate to the atmosphere. It is also possible to perform this in a forming room. An example of such an embodiment using a CVD apparatus will be described below.

A silicon plate on which elements have been formed and whose surface is covered with an oxide film is set in a CVD equipment, the substrate is kept at 400°C, and Ar
Triisobutylaluminum diluted with gas at 250℃
Introduced into the equipment in a heated state to 20%
A first layer AI film having a thickness of several hundred nanometers is formed on the substrate while maintaining the pressure at 0 Pa. Then, the introduction of the raw material gas was stopped and oxygen gas was introduced instead, and several ■ AI20s were applied to the surface of the first layer AII film.
Forms a film. Thereafter, under the same conditions as in the formation of the first layer Aj7 film, several hundreds of second layer Aj7 films are formed. A. l! /AN20a
/Ai) The laminated film is patterned through a PEP process to obtain desired wiring.

This embodiment also makes it possible to obtain Ap wiring that is resistant to electromigration and stress migration.

Next, an example will be described in which a metal film is formed using a selective CVD method. FIGS. 11(a) to 11(d) are cross-sectional views showing the film forming process. First, as shown in FIG. 11(a), a silicon substrate 51 on which elements are formed and whose surface is covered with a silicon oxide film 52 is prepared, and a polycrystalline silicon film is deposited by CVD using monosilane as a source gas. This is patterned to form a wiring core 53 that will become the core of the next metal film deposition. Next, using the same CVD apparatus as in the above embodiment, a selective CVD method was performed using triisobutylaluminum as a raw material and setting growth conditions so that AII deposition occurred selectively on silicon, as shown in FIG. 11(b).
), a first layer Aj7 film 54 of several hundred nanometers is formed on the surface of the core 53.

Then, as shown in FIG. 11(e), the surface of this first layer (Al) 854 is coated with AI? zOi
A film 55 is formed. Thereafter, selective CV was performed again using triisobutylaluminum as a raw material and setting the growth conditions so that Aj) deposition occurred selectively on the A#20i film.
By the D method, AI! as shown in FIG. 11(d). zo
A second layer Aρ film 56 with a thickness of several hundred nm is formed on the surface of the i film 55. Further, an AR20i film 5 is provided on the surface of the second layer A9 film 56.
form 7.

This embodiment also makes it possible to obtain AM wiring that is resistant to electromigration and stress migration. Further, the entire surface of the wiring according to this embodiment is finally covered with an AR20a film 57, and it is possible to prevent short-circuit accidents between wirings due to whiskers.

[Effects of the Invention] As explained above, according to the present invention, it is possible to form a gold-flexible wiring that is resistant to electromigration and stress migration, thereby improving the reliability of semiconductor devices in which elements and wiring are miniaturized and highly integrated. can improve sex.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the wiring structure of one embodiment of the present invention, FIG. 2 is a diagram showing the wiring structure of another embodiment, and FIGS.
) is a diagram showing a comparison of the stress distribution in the wiring structure of Fig. 1 and the conventional wiring structure, Fig. 4 is a diagram showing the relationship between the aspect ratio of the wiring and the wiring stress, and Fig. 5 is a diagram showing the relationship between the wiring aspect ratio and the wiring stress of the present invention. A diagram showing the basic configuration of an embodiment of the film forming apparatus, FIG. 6 is a diagram showing a more specific side view of the film forming apparatus, and FIG.
A country that shows the structure of the country, and the 8th garden shows the electromigration of the wiring by its length example in comparison with the conventional example.)'59
The diagrams are II-, JU <Stress Migration Life compared with the conventional example, Mizu diagram, and As 10 diagram is another husband Si! Figures 11 (; I) to (d) are diagrams showing the wiring cross-sectional structure of one example; Figures 11 (; I) to (d) are diagrams showing the wiring formation structure of other examples in history; Diagram for explaining an example, No. 13
The figure is a cross-sectional view of a length embodiment of the present invention. ]...Silicon 2. (temporary, 2... insulating film, 3... metal bending wiring, 3,... ws 1 1-metal film, 32...
2nd layer metal film, 3, . . . barrier, lla . . . first film formation chamber, 11b . . . second film 1] 3 formation chamber, llc.
...Third film formation chamber, 11d...Substrate introduction chamber, lle
...Talk board extraction chamber, 12a-12e...Katehalb, 13a-13e...Gate valve, 14a-14
e...Turbo molecular pump, 19a~] Oe...Harb, 20a~2 L') e...Roughing pump, 31
... / Recon board, 32 ... silicon oxide film, 33.
...First layer Afi alloy film, 34...Al20, film (
35...Second layer A, Q alloy film, 37...
Grain elevation, 41...Silicon substrate, 42...Silicon oxide film, 4゛U...th]jψCt direct film, 44...A#
20i film (barrier film), 45... second layer Cu film, 51.
...Silicon removal plate, 52...Silicon oxide film, 5'3
... core (multiviscous silicone film), 54 ... first layer Al
l membrane, 55...AN, 0 3 1lκ (impaired saint)
, 56... second layer Ap film, 57... ADtOi film. One representative from the branch

Claims (5)

[Claims] (1) In a semiconductor device in which a metal electrode or wiring is formed on a semiconductor substrate on which an element is formed via an insulating film, the metal electrode or wiring divides the inside in the film thickness direction or width direction. A thickness of 2 to 1, made of a material that does not react with the material of the metal electrode or wiring buried in the
A semiconductor device characterized by having a barrier film of 0 nm. (2) In a method for manufacturing a semiconductor device, which includes a step of forming a metal wiring via an insulating film on a semiconductor substrate on which an element is formed, the step of forming the metal wiring includes a step of forming a first layer metal film, this metal film and the like. The method includes a step of continuously forming at least three layers of a barrier film and a second layer metal film made of different materials without exposing the substrate to the atmosphere, and a step of patterning the formed layered film into a desired shape. A method of manufacturing a semiconductor device, comprising: (3) In a method for manufacturing a semiconductor device, which includes a step of forming a metal wiring via an insulating film on a semiconductor substrate on which an element is formed, the step of forming the metal wiring includes depositing a metal film on a wiring formation area on the substrate. a step of patterning a material film that will become the core of the
a step of depositing a first layer metal film on the surface of the formed material film by selective CVD;
The present invention is characterized by comprising a step of forming a barrier film made of a different material on the surface of the layer metal film, and a step of forming a second layer metal film on the surface of the formed barrier film by selective CVD. A method for manufacturing a semiconductor device. (4) In a wiring film forming apparatus for forming metal wiring on a semiconductor substrate on which an element is formed and an insulating film is formed on the surface, a first film forming chamber for forming a first layer metal film on the substrate; , connected to this first film forming chamber via a gate valve,
a second film forming chamber for forming a barrier film made of a material different from the wiring material on the substrate on which the first layer metal film is formed and transported in the first film forming chamber; A third film forming chamber is connected to the chamber via a gate valve and forms a second layer metal film on the substrate on which the barrier film is formed in the second film forming chamber and is transported. Characteristic wiring film forming equipment. (5) A substrate introducing chamber connected to the first film forming chamber via a gate valve is provided, and a substrate unloading chamber is provided to the third film forming chamber via a gate valve. The wiring film forming apparatus described above.