JPH03167920A - Clock supply circuit - Google Patents

Abstract

PURPOSE:To obtain clock signals with a matched phase by detecting a phase difference between the plural clock signals and feeding back the information to adjust the delay of the clock signals. CONSTITUTION:When a phase difference is detected between clock signals T0 and T1-T3, phase difference detection circuits 115, 125, 135 output phase difference information, which is stored in storage circuit 116, 126, 136. The phase difference information is rewritten as required. The phase difference information is sent immediately to a selection circuit via the storage circuits 116, 126, 136 to control a phase adjustment circuit. When the phase is delayed than the phase of the signal T0, the phase is made to lead by controlling to decrease the delay of the phase adjustment circuit. Moreover, when the phase is leading than that of the signal T0, the delay in the phase adjustment circuit is controlled to be larger to delay the phase thereby matching the phase.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to clock supply circuits for microprocessors and microcontrollers.

[Prior Art] Conventional clock supply circuits for microprocessors and microcontrollers do not use a circuit to adjust the phase of the clock, as shown in Figure 2, but instead adjust the phase by adjusting the delay value of a timing adjustment circuit. Ta.

[Problems to be Solved by the Invention] Conventional clock supply circuits are configured as described above, so when multiple clocks are used, the simulation required for phase alignment becomes enormous. Until the semiconductor integrated circuit was manufactured and analyzed, it was not possible to confirm whether the clock phase was created as designed. Also, if the analysis of the semiconductor integrated circuit shows that the phase is out of alignment,
It was necessary to carry out simulations with corrections based on the analysis results, make mask corrections, and remanufacture the mask, which resulted in a major problem in that the development period was extended and the development costs were extremely high.

The present invention was made in order to solve the problem of lag, and by automatically correcting the phase difference of the clock signal, it is possible to reduce the simulation load and the number of manufacturing times, shorten the development period, and reduce the development cost. It is of great importance to provide a clock supply circuit that can reduce the number of clocks.

[Means for Solving the Problems] The clock supply circuit of the present invention is a microprocessor and a microcontroller that have a reference clock signal and a plurality of clock signals other than the reference clock. A phase difference detection means for detecting a phase difference, a storage means for storing information of the phase difference detection means, a selection means for generating selection information from the information of the phase difference detection means, and a phase adjustment based on the selection information of the selection means. It is characterized in that it has a phase adjustment means and automatically corrects the phase difference of the clock based on the information of the phase difference detection means.

[Operation] The clock supply circuit of the present invention detects the phase difference between multiple clock signals and feeds back the information.
By adjusting the delay value of the clock signal, a clock signal that is in phase can be obtained.

[Embodiment] FIG. 1 shows an embodiment of the present invention. In the figure, a reference clock input signal CKO is input to a timing matching circuit 101 and given a delay value commensurate with the phase adjustment circuits 113, 123, and 133 to drive the reference clock signal. The data is input to buffer 102.

In the initial state, the selection circuit 117 outputs a selection signal according to the state initialized in the storage circuit 116 to control the phase adjustment circuit. Similarly, the phase adjustment circuits 123 and 133 are also initialized, and the clock signal drive buffers 114 and 124 are initialized.
, 134 as clock signals TI, T2, T.

When a phase difference is detected between the clock signal To and Tl-73, the phase difference detection circuits 115, 125, 135 output phase difference information, and the phase difference information is stored in the storage circuits 116, 126.
, 136.

The phase difference information is rewritten as necessary.

The phase information is immediately transmitted to the selection circuit via the storage circuits 116, 126, 136 to control the phase adjustment circuit.

If the phase is behind To, the phase can be advanced by controlling the delay value of the phase adjustment circuit to be small.

Further, when the phase is ahead of TO, the phase can be adjusted by controlling the delay value of the phase adjustment circuit to be large to delay the phase.

In this embodiment, a case where three clock signals are used for one reference clock signal has been described, but the same applies regardless of how many clock signals there are.

[Effects of the Invention] As described above, according to the present invention, the phase difference of clock signals can be automatically corrected, the simulation load and the number of manufacturing times can be reduced, and the development period can be shortened and development costs can be significantly reduced. I can figure it out.

In addition, phase adjustment can be performed even against manufacturing variations and variations due to aging, and a great effect can be obtained in that stable operation of the semiconductor integrated circuit can be guaranteed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. In the figure, 101 is a timing matching circuit, 102
・114, 124, 134 are clock signal drive buffer circuits, 113, 123, 133 are phase adjustment circuits, 1
15, 125, 135 are phase difference detection circuits, 116, 1
26 and 136 are memory circuits, 117, 127, and 137 are selection circuits, 1, 11, 21, and 31 are timing matching circuits, 2, 12, 22, and 32 are clock drive buffers, and C
KO-CK3 is an input clock signal, and TO-T3 are clock signals. that's all

Claims (1)

[Claims] In microprocessors and microcontrollers having a reference clock signal and a plurality of clock signals in addition to the reference clock, a phase difference detection means for detecting a phase difference between the reference clock signal and another clock signal; A storage means for storing information, a selection means for generating selection information from the information of the phase difference detection means, and a phase adjustment means for performing phase adjustment from the selection information of the selection means, based on the information of the phase difference detection means. A clock supply circuit characterized by automatically correcting a clock phase difference.