JPH05102845A - Skew adjustment circuit - Google Patents

Abstract

PURPOSE:To provide the skew adjustment circuit in which a clock skew causing disturbance to high speed processing in a high speed LSI and compatible with a state of debugging important in the development of the LSI. CONSTITUTION:An oscillation circuit 130 is formed in the inside of an LSI. The phase of a clock inputted externally to an input terminal 191 and the phase of an output of the oscillation circuit 130 are compared by a phase comparator circuit 110 and the result of comparison is stored in a storage circuit 120. The clock from the input terminal 191 is outputted with a delay by a variable delay circuit 100 whose delay time is controlled by the storage content in the storage circuit 120 to compensate a phase fluctuation in the clock in the inside of the LSI.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a skew adjusting circuit, and more particularly to a skew adjusting circuit which suppresses clock skew which hinders high speed operation in a high speed LSI.

[0002]

2. Description of the Related Art An example of a conventional skew adjusting circuit of this type is shown in FIG. In FIG. 2, 200 is a frequency variable oscillation circuit, 201 is a first input terminal of the frequency variable oscillation circuit 200, 206 is a first output terminal of the frequency variable oscillation circuit 200, 210 is a phase comparison circuit, and 211 is a phase comparison circuit. Two
10 is a first input terminal, 212 is a second input terminal of the phase comparison circuit 210, 216 is a first output terminal of the phase comparison circuit 210, 220 is a clock distribution system inside the LSI including this conventional example, and 221 is Input terminal of clock distribution system 220,
226 is one of the output terminals of the clock distribution system 220, 29
Reference numeral 1 represents an input terminal of this conventional example.

The operation of this conventional example will be described.

As shown in FIG. 2, for example, a clock circuit is connected to the input terminal 291 from the outside, and the clock distribution system 2
The phase comparison circuit 210 detects the phase difference between the output of the output terminal 226 of 20 and the clock signal input from the input terminal 291. For example, the voltage value corresponding to the phase difference is output terminal 2
Output from 16. The voltage value is input from the input terminal 201, and the phase difference between the external clock signal and the output signal of the frequency oscillating circuit 200 is eliminated, or the oscillation frequency is changed to have a certain value.

The clock distribution system 220 changes from the input terminal 221 to the output terminal 2 due to device variations and temperature changes.
The delay time up to 26 changes significantly. Therefore, in order to adjust the phase of the clock with the external LSI, the phase comparison circuit 210 detects the phase difference between the output of the clock distribution system 220 and the clock input from the outside, and the frequency variable oscillation is performed so as to reduce the skew. Adjustments are made by varying the inputs to circuit 200. The phase comparison circuit 210 can also divide or double the input one signal, for example.

As described above, the conventional skew adjustment circuit uses the signal output from the frequency variable oscillation circuit 200, for example, the voltage controlled oscillation circuit, as the skew adjusted clock.

[0007]

In this conventional skew adjusting circuit, for example, when shifting from the normal operating state to the debug mode, it is necessary to stop the clock speed midway, but in this case, the phase comparing circuit is used. 210 indicates whether the speed of the clock from the outside has changed or not.
I cannot judge whether the frequency of 00 dropped. Therefore, even if the external clock stops, the internal variable frequency oscillation circuit 2
It is considered that 00 does not stop for several to several tens of clocks.
In this case, it is necessary to check how much extra clock is input each time the clock is stopped, which makes debugging extremely difficult. Further, even when the clock is input again for debugging, it is very difficult to determine the number of clocks required until the internal clock becomes stable. In such a situation, when a plurality of LSIs are provided, the situation becomes extremely difficult.

[0008]

The skew adjusting circuit of the present invention includes an oscillator circuit having a first output terminal, first and second oscillator circuits.
Delay circuit having a first input terminal and a first output terminal and adding a delay time controlled by a signal obtained from the second input terminal to a signal output from the first input terminal to the first output terminal And having a first and a second input terminal and a first output terminal, the phase difference between the signal input from the first input terminal and the signal input from the second input terminal is detected and the phase difference is detected. A first phase comparison circuit for outputting a signal from the first output terminal and a signal input from the first input terminal having the first and second input terminals and the first output terminal to the second input A storage circuit for storing the result according to a signal input from the terminal and outputting the result from the first output terminal, wherein the first output terminal of the oscillation circuit is the first output terminal.
Connected to the second input terminal of the phase comparison circuit, the first output terminal of the first phase comparison circuit is connected to the first input terminal of the storage circuit, and the first output terminal of the storage circuit is connected to the first output terminal of the storage circuit. Connecting to a second input terminal of the variable delay circuit, connecting the first input terminal of the variable delay circuit and the first input terminal of the first phase comparison circuit to form a first external input terminal, A second input terminal of the memory circuit is a second external input terminal, and a first output terminal of the variable delay circuit is a first external output terminal.

Further, the skew adjustment circuit of the present invention has a first input terminal and a first output terminal, and a frequency at which the frequency of the signal output from the first output terminal can be changed by the signal of the first input terminal. A variable oscillator circuit, which has first and second input terminals and a first output terminal, detects a phase difference between a signal input from the first input terminal and a signal input from the second input terminal, and detects the phase difference. A second phase comparison circuit that outputs a signal corresponding to the phase difference from the first output terminal, and has first, second and third input terminals and a first output terminal, and is input to the third input terminal. The signal output to the first output terminal by the signal and the signal input from the first input terminal to the second input terminal
A selection circuit for selecting one of a signal input from an input terminal of the second phase comparison circuit, and a first output terminal of the frequency variable oscillation circuit via an external circuit. The frequency variable oscillator circuit is connected to the first
The output terminal of is connected to the second input terminal of the selection circuit,
The first external output terminal is connected to a first input terminal of the selection circuit, the first external input terminal and the first input terminal of the second phase comparison circuit are connected, and the selection circuit May be configured as a third external input terminal, and the first output terminal of the selection circuit may be configured as a second external output terminal.

[0010]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, 100 is a variable delay circuit, 1
Reference numeral 01 is a first input terminal of the variable delay circuit 100, 102 is a second input terminal of the variable delay circuit 100, 106 is a first output terminal of the variable delay circuit 100, 110 is a phase comparison circuit, and 111 is a phase comparison circuit. 110 first input terminal, 1
12 is the second input terminal of the phase comparison circuit 110, 116 is the first output terminal of the phase comparison circuit 110, 120 is the storage circuit, 121 is the first input terminal of the storage circuit 120, 122
Is a second input terminal of the memory circuit 120, 126 is a first output terminal of the memory circuit 120, 130 is an oscillator circuit, 131 is a first output terminal of the oscillator circuit 130, and 191 is a first input of this embodiment. Terminal, 192 is the second input terminal of this embodiment,
Reference numeral 196 represents the first output terminal of this embodiment.

The operation of this embodiment will be described.

As shown in FIG. 1, for example, a clock circuit is externally connected to the input terminal 191, and the phase comparison circuit 110 detects the phase difference between the output of the oscillation circuit 130 and the clock signal input from the input terminal 191. Then, for example, a voltage value corresponding to the phase difference is output from the output terminal 116. The oscillator circuit 130 is configured by a device in the LSI including the present embodiment, such as a ring oscillator, and has a possibility that the frequency may change due to variations in the device. The voltage value output from the output terminal 116 of the phase comparison circuit 110 is held in the storage circuit 120 or converted, and then input to the variable delay circuit 100 from the input terminal 102.
The output terminal 1 eliminates the phase difference between the external clock signal and the output of the oscillator 130, or maintains a constant value.
The phase of the output signal of 06 is changed. Phase comparison circuit 11
With 0, for example, one input signal can be divided or doubled.

The operation principle of skew adjustment in the embodiment of FIG. 1 will be described below.

As described above, the cause of the skew is the variation of the devices such as the clock distribution system, and the variation causes the skew to a great extent.
Therefore, in order to adjust the skew, it is necessary to know the operating speed of the device inside the LSI including the skew adjusting circuit. Therefore, a deviation of the operating speed of the device from the design reference value can be detected by incorporating an oscillation circuit 130 such as a ring oscillator inside and detecting the frequency and phase difference from the clock signal input from the outside. It will be possible. Skew adjustment can be performed by calculating the operating speed of the clock distribution system from the detection result and changing the delay time of the variable delay circuit 100 so that it becomes a value determined by the design value. Until the calculation of the delay time is completed, for example, the entire LSI maintains a reset state or the like, and when the reset state is released, the calculation result at that time is stored in the memory circuit 120 until the next reset state. Therefore, once the required delay time is calculated, the data is extracted from the memory circuit 120 so that the normal operation can be performed. Since only the delay circuit is used here, once the delay control value is set in the memory circuit 120, it can be used with the skew reduced regardless of whether or not the clock stops. Further, if the memory circuit 120 also has a temperature correction function, it is possible to always maintain a constant skew.

A second embodiment of the present invention is shown in FIG.

In FIG. 3, 300 is the same skew adjustment circuit as that of the embodiment of FIG. 1, 310 is a frequency variable oscillation circuit, 3
11 is a first input terminal of the variable frequency oscillator circuit 310,
16 is the first output terminal of the frequency variable oscillation circuit 310, 3
20 is a second phase comparison circuit, 321 is a phase comparison circuit 32
0 is a first input terminal, 322 is a second input terminal of the phase comparison circuit 320, 326 is a first output terminal of the phase comparison circuit 320, 330 is a selection circuit, 331 is a first input terminal of the selection circuit 330. 332 is a second input terminal of the selection circuit 330, 333 is a third input terminal of the selection circuit 330, 33
6 is a first output terminal of the selection circuit 330, 340 is a clock distribution system, 341 is a first input terminal of the clock distribution system 340, 346 is a first output terminal of the clock distribution system 340, and 391 is of this embodiment. A first input terminal, 392 is a second input terminal of this embodiment, 393 is a third input terminal of this embodiment, and 396 is a first output terminal of this embodiment.

The operation of the embodiment shown in FIG. 3 will be described.

In the embodiment shown in FIG. 3, the skew adjusting circuit of the present invention shown in FIG. 1 and the conventional skew adjusting circuit shown in FIG. 2 are combined, and either circuit is selected under optimum conditions. It is designed to be selected. That is, the output of the skew adjustment circuit 300 is selected by the selection circuit 330 during debugging, and the output of the frequency variable oscillation circuit 310 is selected under normal circumstances.
This switching is controlled by a signal input to the third input terminal 393 of this embodiment, for example, a debug mode signal. The feature of this embodiment is that it provides the same skew as in the embodiment of FIG. 1 during debugging while maintaining the same precision as in the conventional skew adjusting circuit during normal operation.

[0021]

By using the skew adjusting circuit of the present invention, it is possible to easily stop the clock freely as at the time of debugging, and the skew can be reduced, which enables high-speed LSI and board design. Become.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional skew adjustment circuit.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 100 variable delay circuit 110, 320 phase comparison circuit 120 storage circuit 130 oscillation circuit 300 skew adjustment circuit 310 frequency variable oscillation circuit 330 selection circuit 340 clock distribution system

Claims (2)

[Claims] 1. An oscillator circuit having a first output terminal;
And a first input terminal having a second input terminal and a first output terminal
Variable delay circuit for adding a delay time controlled by a signal obtained from the second input terminal to a signal output from the signal obtained from the input terminal to the first output terminal, first and second input terminals, and a first And a phase difference between a signal input from the first input terminal and a signal input from the second input terminal, and a signal corresponding to the phase difference is output from the first output terminal. Having a first phase comparator circuit, first and second input terminals and a first output terminal, and storing a signal input from the first input terminal as a signal input from the second input terminal. A storage circuit for outputting the result from a terminal, the first output terminal of the oscillation circuit is connected to the second input terminal of the first phase comparison circuit, and the first output terminal of the first phase comparison circuit is connected. Output terminal to the first input terminal of the memory circuit Then, the first output terminal of the storage circuit is connected to the second input terminal of the variable delay circuit, and the first input terminal of the variable delay circuit and the first input terminal of the first phase comparison circuit are connected. Are connected to serve as a first external input terminal, the second input terminal of the storage circuit serves as a second external input terminal, and the first output terminal of the variable delay circuit serves as a first external output terminal. A skew adjustment circuit characterized by the above. 2. A variable frequency oscillating circuit having a first input terminal and a first output terminal, wherein the frequency of a signal output from the first output terminal can be changed by a signal from the first input terminal, and It has a second input terminal and a first output terminal, detects a phase difference between a signal input from the first input terminal and a signal input from the second input terminal, and outputs a signal corresponding to the phase difference as a first signal. The second phase comparison circuit for outputting from the output terminal of the first output terminal, the first, second and third input terminals and the first output terminal, and the signal input to the third input terminal A selection circuit for selecting a signal to be output as either a signal input from the first input terminal or a signal input from the second input terminal. Of the second phase comparison circuit via an external circuit A second input terminal is connected, and a first output terminal of the variable frequency oscillation circuit is connected to a second output terminal of the selection circuit.
Connected to the first input terminal of the selection circuit, the first external output terminal to the first input terminal of the selection circuit, and the first external input terminal and the first input terminal of the second phase comparison circuit. 2. The third input terminal of the selection circuit is used as a third external input terminal, and the first output terminal of the selection circuit is used as a second external output terminal. Skew adjustment circuit.