JPH0567394A - Semiconductor storing device - Google Patents

Abstract

PURPOSE:To suppress the lowering of yield with a malfunction and to reduce a cost by adjusting the pulse width and the timing control of a clock signal with a control signal in the case of the malfunction by the failure of the timing control. CONSTITUTION:A control signal 101 is fixed to two signals of high and low. Then, when the control signal 311 is selected, the signal 311 passes through a transistor 31, is inputted to an OR gate 30, is compared with an input signal 301 and a high pulse signal 302 is generated. Further, when the signal 313 is selected, the signal 313 passes through the transistor 33, is inputted to the OR gate 30. Then, between when the signal 311 is selected and when the signal 313 is selected, the high pulse signal of the different pulse width by 4 pieces of an inverter is generated. Thus, in the case of the malfunction due to the failure of the internal clock signal, by adjusting the pulse width and the timing control with the control signal, the lowering of the yield is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal clock generation circuit and timing control for a semiconductor memory device.

[0002]

2. Description of the Related Art In a conventional semiconductor memory device, when the pulse width of an internal clock signal is changed, the circuit is modified and remanufactured.

[0003]

Advances in semiconductor manufacturing technology have made it possible to miniaturize semiconductor elements and increase the speed of semiconductor devices. Further, there is an increasing demand for higher speed devices in the market. Against this background, especially ICs for specific applications
Semiconductor memory devices used in the field of ASIC (hereinafter referred to as ASIC) have various requirements for user configurations, and vendors must prepare semiconductor memory devices having a wide range of configurations.

In a general-purpose semiconductor memory device, the pulse width and timing control of the internal clock signal may be made according to the semiconductor memory device having a fixed structure, and the pulse width and timing of the internal clock signal can be evaluated by an actual model. Control adjustments can be made. But ASIC
In the evaluation of semiconductor memory devices, it is impossible to create and evaluate semiconductor memory devices of all possible configurations because of time and cost problems, and to create semiconductor memory devices of several typical configurations. Will be evaluated. Therefore, timing adjustment is not performed accurately in all configurations. This means that the higher the speed of the operation of the device, the higher the accuracy required for timing adjustment, and that the operation may stop if the timing shifts due to external factors, process fluctuations, power supply potential fluctuations, etc. ..

Conventionally, when a semiconductor memory device requires correction due to a timing control problem, it has been necessary to modify the circuit by changing the connection of elements and remanufacture. Remanufacturing increases product costs and delays delivery.

Therefore, an object of the present invention is to correct the defect of the timing control without remanufacturing by performing the timing control from the outside by the control signal so that it can correspond to the semiconductor memory devices of various configurations. ..

[0007]

In order to solve the above-mentioned problems, the present invention is characterized in that timing control is performed by a control signal in a semiconductor memory device.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an asynchronous semiconductor memory device (hereinafter referred to as RAM) using the present invention. The address signal 131-133, the data signal 121-123, the CS signal 102, the RW signal 103, and the timing control signal 111-113 are input to the input terminals of the RAM 2, and the output data terminals 141-143 output data. On the other hand RA
Timing control signal 1 input from the outside of M
01 is input to the selector 1 and the signals 111-113 selected by the selector are input to the timing control signal terminal of the RAM 2.

FIG. 2 shows an internal clock generation circuit of the asynchronous RAM. In the internal clock generation circuit, the input signal 201
And the signal obtained by delaying the input signal by the delay element 3 is compared by the comparator 4 to detect the change point of the input signal 201 and generate the internal clock signal 202. This internal clock is delayed or delayed and inverted to operate each internal circuit of the RAM. By changing the delay time in the delay element 3, the pulse width of the internal clock signal can be changed.

FIG. 3 shows an example of a concrete circuit for changing the timing of the internal clock signal. One of the timing control signals 101 is fixed to HIGH by the selector 1, and the remaining signals are fixed to LOW. When the timing control signal 311 is selected, the input signal passes through the Nch transistor 31 and is input to the input terminal of the exclusive OR gate 30. In the exclusive OR gate 30, the signal and the input signal 3
01 is compared and a HIGH pulse signal 302 is generated. On the other hand, when the timing control signal 313 is selected, the input signal passes through the Nch transistor 33 and is input to the input terminal of the exclusive OR gate 30. In this case, when the timing control signal 311 is selected and when the timing control signal 313 is selected, it is possible to generate a HIGH pulse signal having a pulse width different by four inverters.

In this way, the pulse width of the internal clock signal can be controlled from the outside of the semiconductor memory device by the control signal.

According to the present invention, since the pulse width of the internal clock signal can be controlled from the outside of the semiconductor memory device by the timing control signal, the semiconductor memory device is remanufactured when the semiconductor memory device does not operate due to a timing control defect. The timing can be corrected without doing so, and the semiconductor memory device can be operated normally.

Although the pulse width of the internal clock signal has been described in the embodiment, the internal clock signal is delayed,
Alternatively, the present invention can be used in a circuit in which delay inversion is performed and timing control is performed.

[0014]

As described above, according to the present invention, when the semiconductor memory device does not operate due to improper timing of the internal clock signal, the timing control signal causes the pulse width and delay time of the internal clock signal. Can be changed to an appropriate position to operate the semiconductor memory device. Therefore, it is possible to suppress a decrease in yield due to a malfunction of the semiconductor memory device, and it is possible to suppress cost.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a semiconductor memory device having a timing adjustment circuit of the present invention.

FIG. 2 is an explanatory diagram of an internal clock generation circuit of the asynchronous semiconductor device of the present invention.

FIG. 3 is an internal clock generation circuit diagram of the asynchronous semiconductor device of the present invention.

[Description of Reference Signs] 1 selector 2 asynchronous RAM 101 selector signal 102 CS signal 103 RW signal 111-113 timing control signal 121-123 input data signal 131-133 address signal 141-143 output data signal 3 delay element 4 comparator 202 Internal clock signal 30 Exclusive OR gate 31-34 Nch transistor 311-334 Timing control signal 302 Internal clock signal

Claims (1)

[Claims] 1. A semiconductor memory device characterized in that the pulse width and timing control of an internal clock signal are adjusted by a control signal.