JPH03167853A - Package for semiconductor-element - Google Patents

Package for semiconductor-element

Info

Publication number
JPH03167853A
JPH03167853A JP1308597A JP30859789A JPH03167853A JP H03167853 A JPH03167853 A JP H03167853A JP 1308597 A JP1308597 A JP 1308597A JP 30859789 A JP30859789 A JP 30859789A JP H03167853 A JPH03167853 A JP H03167853A
Authority
JP
Japan
Prior art keywords
external lead
lead terminal
lid
semiconductor element
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1308597A
Other languages
Japanese (ja)
Other versions
JP2736453B2 (en
Inventor
Hiroshi Matsumoto
弘 松本
Masaaki Iguchi
井口 公明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP1308597A priority Critical patent/JP2736453B2/en
Priority to US07/573,406 priority patent/US5057905A/en
Publication of JPH03167853A publication Critical patent/JPH03167853A/en
Application granted granted Critical
Publication of JP2736453B2 publication Critical patent/JP2736453B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To normally operate an inside semiconductor element by a method wherein an external lead terminal is constituted of a metal body in which copper sheets having a thickness of a specific % with reference to a thickness of a sheetlike body composed of an alloy of Ni, Co and Fe at respectively specific wt.% are bonded to the surface and the rear surface of the sheetlike body. CONSTITUTION:An insulating substrate 1 and a lid body 2 are formed of spinel or a steatite sintered substance. On the other hand, external lead terminal 5 are formed of a metal body in which copper sheets having a thickness of 60 to 80% with reference to a thickness of a sheetlike body composed of an alloy of 31.5 to 32.5wt.% of Ni, 16.5 to 17.5wt.% of Co and 50.0 to 52.0wt.% of Fe are bonded to the surface and the rear surface of the sheetlike body, whose magnetic permeability is about 93 (CGS), whose electric conductivity is 62.3% (IACS) and whose coefficient of thermal expansion is about 71X10<-7>/ deg.C. Thereby, even when an electric current flows to the terminals 5, a large self-inductance is not generated in the terminals, a noise by an electromotive force caused by the self-inductance is reduced to a minimum and a semiconductor inside can be always operated normally.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体素子を収容する半導体素子収納用パッケ
ージの改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a semiconductor element housing package that houses a semiconductor element.

(従来の技術) 従来、半導体素子を収容するためのパッケージ、特にガ
ラスの溶着によって封止するガラス封止型半導体素子収
納用パッケージは、絶縁基体と蓋体とから成り、内部に
半導体素子を収容する空所を有する絶縁容器と、該容器
内に収容される半導体素子を外部電気回路に電気的に接
続するための外部リード端子とから構威されており、絶
縁基体及び蓋体の相対向する主面に予め封止用のガラス
部材を被着形戒すると共に、絶縁基体主面に外部リード
端子を固定し、半導体素子の各電極と外部リード端子と
をワイヤボンド接続した後、絶縁基体及び蓋体のそれぞ
に被着させた封止用のガラス部材を熔融一体化させるこ
とによって内部に半導体素子を気密に封止している。
(Prior Art) Conventionally, a package for accommodating a semiconductor element, particularly a glass-sealed semiconductor element accommodating package sealed by glass welding, consists of an insulating base and a lid body, and the semiconductor element is housed inside. The structure consists of an insulating container having a cavity, and an external lead terminal for electrically connecting a semiconductor element housed in the container to an external electric circuit, and an insulating base and a lid facing each other. A glass member for sealing is applied on the main surface in advance, external lead terminals are fixed on the main surface of the insulating substrate, and each electrode of the semiconductor element and the external lead terminal are wire bonded, and then the insulating substrate and A semiconductor element is hermetically sealed inside by melting and integrating sealing glass members attached to each lid.

(発明が解決しようとする課題) しかしケら、この従来のガラス封止型半導体素子収納用
パッケージは通常、外部リード端子がコハ−ル(29 
WtX Ni−16 WtX Co−55 WtXFe
合金)や42AIloy(42 WtX Ni−58 
WtX Fe合金)の導電性材料から成っており、該コ
バールや42A I joy等は透磁率が高く、且つ導
電率が低いことから以下に述べる欠点を有する。
(Problem to be Solved by the Invention) However, in this conventional glass-sealed package for storing semiconductor elements, the external lead terminals are usually Kohar (29
WtX Ni-16 WtX Co-55 WtXFe
alloy) and 42AIloy (42 WtX Ni-58
Kovar, 42A I joy, and the like have high magnetic permeability and low conductivity, and therefore have the following disadvantages.

即ち、 ■コバールや42A 1 toyは鉄(Fe)、ニッケ
ル(Ni)、コバル} (Co)といった強磁性体金属
のみから戒っており、その透磁率は250〜700 (
CGS)と高い。そのためこのコバールや42A11o
y等から成る外部リード端子に電流が流れると外部リー
ド端子中に透磁率に比例した大きな自己インダクタンス
が発生し、これが逆起電力を誘発してノイズとなると共
に、該ノイズが半導体素子に入力されて半導体素子に誤
動作を生じさせる、 ■コバールや42八l joyはその導電率が3.0〜
3.5z(IACS)と低い。そのためこのコバールや
42A l toy等から或る外部リード端子に信号を
伝搬させた場合、信号の伝搬速度が極めて遅いものとな
り、高速駆動を行う半導体素子はその収容が不可となっ
てしまう、 ■半導体素子収納用パフケージの内部に収容する半導体
素子の高密度化、高集積化の進展に伴い、半導体素子の
電極数が大幅に増大しており、半導体素子の各電極を外
部電気回路に接続する外部リード端子の線幅も極めて細
くなってきている。そのため外部リード端子は上記■に
記載のコバールや42AIIoyの導電率が低いことと
相俊って電気抵抗が極めて大きなものになってきており
、外部リート端子に信号を伝搬させると、該外部リード
端子の電気抵抗に起因して信号が大きく減衰し、内部に
収容する半導体素子に信号を正確に人力することができ
ず、半導体素子に誤動作を生しさせてしまう、 等の欠点を有していた。
In other words, ■ Kovar and 42A 1 toy are prohibited from using only ferromagnetic metals such as iron (Fe), nickel (Ni), and cobal (Co), and their magnetic permeability is 250 to 700 (
CGS) and high. Therefore, this Kovar and 42A11o
When a current flows through the external lead terminals such as y, a large self-inductance proportional to the magnetic permeability is generated in the external lead terminals, which induces back electromotive force and becomes noise, and the noise is input to the semiconductor element. Kovar and 428L JOY have a conductivity of 3.0 to 3.0.
It is as low as 3.5z (IACS). Therefore, when a signal is propagated from this Kovar or 42Al toy to a certain external lead terminal, the signal propagation speed becomes extremely slow, making it impossible to accommodate semiconductor elements that drive at high speed. ■Semiconductor With the progress of higher density and higher integration of semiconductor devices housed inside puff cages for device storage, the number of electrodes on semiconductor devices has increased significantly. The line width of lead terminals is also becoming extremely thin. Therefore, the electrical resistance of the external lead terminal has become extremely large due to the low conductivity of Kovar and 42AIIoy described in (2) above, and when a signal is propagated to the external lead terminal, the external lead terminal The signal was greatly attenuated due to the electrical resistance of the device, making it impossible to accurately transmit the signal to the semiconductor device housed inside, which could cause the semiconductor device to malfunction. .

(発明の目的) 本発明は上記欠点に鑑み案出されたもので、その目的は
外部リード端子で発生するノイズ及び外部リード端子に
おける信号の減衰を極小となし、内部に収容する半導体
素子への信号の入出力を確実に行うことを可能として半
導体素子を長期間にわたり正常、且つ安定に作動させる
ことができる半導体素子収納用バッケージを提供するこ
とにある。
(Object of the Invention) The present invention was devised in view of the above drawbacks, and its purpose is to minimize the noise generated at the external lead terminal and the attenuation of the signal at the external lead terminal, and to minimize the noise generated at the external lead terminal and the attenuation of the signal at the external lead terminal. It is an object of the present invention to provide a package for storing a semiconductor element, which enables reliable input/output of signals and allows the semiconductor element to operate normally and stably for a long period of time.

また本発明の他の目的は高速駆動を行う半導体素子を収
容することができる半導体素子収納用パッケージを提供
することにある。
Another object of the present invention is to provide a semiconductor device storage package that can accommodate semiconductor devices that operate at high speed.

(課題を解決するこめの手段) 本発明は絶縁基体と蓋体とから戒り、内部に半導体素子
を収容するための空所を有する絶縁容器と、該容器内に
収容される半導体素子を外部電気回路に接続するための
外部リード端子とから或る半導体素子収納用パッケージ
において、前記絶縁基体及び蓋体をスピネルもしくはス
テアタイト質焼結体で、外部リード端子をニッケル31
.5乃至32.5WtX % :2ハ)L/トl6.5
乃至17.5WtX ,鉄50.0乃至52.0WtX
の合金から威る板状体の上下面に、該板状体の厚みに対
し60乃至80xの厚みの鋼板を接合させた金属体で形
成したことを特徴とするものである。
(Further Means for Solving the Problems) The present invention includes an insulating container having a cavity for accommodating a semiconductor element inside the insulating base body and a lid body, and an insulating container having a cavity for accommodating a semiconductor element inside the container, and a semiconductor element housed in the container. In a package for storing a semiconductor element, the insulating base and the lid are made of spinel or steatite sintered body, and the external lead terminal is made of nickel 31.
.. 5 to 32.5WtX%: 2c) L/tl6.5
~17.5WtX, iron 50.0~52.0WtX
It is characterized in that it is formed of a metal body made of a plate-shaped body made of an alloy, and steel plates having a thickness of 60 to 80 times the thickness of the plate-shaped body are bonded to the upper and lower surfaces of the plate-shaped body.

(実施例) 次に本発明を添付図面に基づき詳細に説明する.?1図
及び第2図は本発明の半導体素子収納用パフケージの一
実施例を示し、1は絶縁基体、2は蓋体である。この絶
縁基体1と蓋体2とにより絶縁容器3が構威される。
(Example) Next, the present invention will be explained in detail based on the attached drawings. ? 1 and 2 show an embodiment of a puff cage for storing semiconductor elements according to the present invention, where 1 is an insulating base and 2 is a lid. The insulating base 1 and the lid 2 constitute an insulating container 3.

前記絶縁基体l及び蓋体2はそれぞれの中央部に半導体
素子を収容する空所を形或するための凹部が設けてあり
、絶縁基体lの凹部底面には半導体素子4が樹脂、ガラ
ス、ロウ剤等の接着剤を介し取着固定される。
The insulating base 1 and the lid 2 each have a recess formed in the center thereof to form a cavity for accommodating a semiconductor element, and the semiconductor element 4 is placed on the bottom of the recess of the insulating base 1 with resin, glass, or wax. It is attached and fixed using an adhesive such as an adhesive.

前記絶縁基体l及び蓋体2はスビネルもしくはステアタ
イト質焼結体から戒り、第1図に示すような絶縁基体1
及び蓋体2に対応した形状を有するプレス型内に、スピ
ネルの場合はマグネシア(MgO)、アルミナ(^12
03 )等の原料粉末を、ステアタイト質焼結体の場合
はマグネシア(MgO) 、シリカ(SiO■)等の原
料粉末を充填させるとともに一定圧力を印加して成形し
、しかる後、成形品を約1200〜1700℃の温度で
焼戒することによって製作される。
The insulating base 1 and the lid 2 are made of Subinel or steatite sintered body, and are made of an insulating base 1 as shown in FIG.
In the case of spinel, magnesia (MgO) and alumina (^12
In the case of a steatite sintered body, raw material powder such as 03) is filled with raw material powder such as magnesia (MgO) or silica (SiO), and a constant pressure is applied to form the product. It is produced by firing at a temperature of about 1200 to 1700 degrees Celsius.

尚、前記絶縁基体1及び蓋体2を形戊するスピネルもし
くはステアタイト質焼結体はその熱膨張係数が70〜8
5xlO−’/ ”cであり、後述する封止用ガラス部
材の熱膨張係数との関係において絶縁基体1及び蓋体2
と封止用ガラス部材間に大きな熱膨張の差が生じること
はない。
The spinel or steatite sintered body forming the insulating base 1 and the lid 2 has a thermal expansion coefficient of 70 to 8.
5xlO-'/''c, and in relation to the thermal expansion coefficient of the sealing glass member described later, the insulating base 1 and the lid 2
A large difference in thermal expansion does not occur between the sealing glass member and the sealing glass member.

また前記絶縁基体1及び蓋体2にはその相対向する主面
に封止用のガラス部材6が予め被着形成されており、該
絶縁基体1及び蓋体2の各々に被着されている封止用ガ
ラス部材6を加熱溶融させ一体化させることにより絶縁
容器3内の半導体素子4を気密に封止する。
Further, a sealing glass member 6 is formed in advance on the opposing main surfaces of the insulating base 1 and the lid 2, and is adhered to each of the insulating base 1 and the lid 2. The semiconductor element 4 inside the insulating container 3 is hermetically sealed by heating and melting the sealing glass member 6 to integrate it.

前記8縁基体1及び蓋体2の相対向する主面に被着され
る封止用ガラス部材6は、例えばホウケイ酸鉛系ガラス
にフイラーを添加したものから成り、原料粉末としての
酸化鉛( PbO )70.0〜90.OWtX 、酸
化ホウ素( BzOi )12.0 〜13.OWtX
 、シ.lJ力(SiOt)0.5 〜3.O WtX
及びアルミナ(All(h)0.5〜3.O WtX 
ニ7 4ラーとしてチタン酸鉛(PbTiO3)、β−
ユークリプタイト(LiJ1zSizOs) 、コージ
ライト(MgJl4SisO+ a)、ジルコン(Zr
SiOn)、酸化スズ(’Snug)、ウイレマイト(
ZnzSiOn)等を15〜30Volχ添加混合する
と共に、該混合粉末を950〜1100℃の温度で加熱
溶融させることによって製作される。このホウケイ酸鉛
系のガラスはその熱膨張係数が60〜90xlO−’/
 ’cである。
The sealing glass member 6 adhered to the opposing main surfaces of the eight-edge base 1 and the lid 2 is made of, for example, lead borosilicate glass with a filler added, and is made of lead oxide (lead oxide) as a raw material powder. PbO ) 70.0-90. OWtX, boron oxide (BzOi) 12.0 to 13. OWtX
, C. lJ force (SiOt) 0.5 ~ 3. O WtX
and alumina (All(h)0.5~3.O WtX
7. Lead titanate (PbTiO3), β-
Eucryptite (LiJ1zSizOs), cordierite (MgJl4SisO+ a), zircon (Zr
SiOn), tin oxide ('Snug), willemite (
It is manufactured by adding and mixing 15 to 30 Vol. This lead borosilicate glass has a thermal expansion coefficient of 60 to 90xlO-'/
'c.

前記封止用ガラス部材6はその熱膨張係数が60〜90
xlO−’/ ”cであり、絶縁基体l及び蓋体2の各
々の熱膨張係数と近似することから絶縁基体1及び蓋体
2の各々に被着されている封止用ガラス部材6を加熱溶
融させ一体化させることにより絶縁容器3内の半導体素
子4を気密に封止する際、絶縁基体l及び蓋体2と封止
用ガラス部材6との間には両者の熱膨張係数の相違に起
因する熱応力が発生することは殆どなく、絶縁基体1と
蓋体2とを封止用ガラス部材6を介し強固に接合するこ
とが可能となる。
The sealing glass member 6 has a thermal expansion coefficient of 60 to 90.
xlO-'/''c, which approximates the coefficient of thermal expansion of each of the insulating base 1 and the lid 2, so the sealing glass member 6 attached to each of the insulating base 1 and the lid 2 is heated. When the semiconductor element 4 in the insulating container 3 is hermetically sealed by melting and integrating, there is a difference in thermal expansion coefficient between the insulating base l and the lid 2 and the sealing glass member 6. Almost no resulting thermal stress occurs, and it becomes possible to firmly join the insulating base 1 and the lid 2 via the sealing glass member 6.

尚、前記封止用ガラス部材6はフィラーを添加したホウ
ケイ酸鉛系ガラスの粉末に適当な有機溶剤、溶媒を添加
して得たガラスペーストを従来周知の厚膜手法を採用す
ることによって絶縁基体l及び蓋体2の相対向する゛主
面に被着形成される.また前記封止用ガラス部材6はフ
イラーを添加したホウケイ酸鉛系のガラスに限定される
ものではなく、熱膨張係数が60〜90X10−’/ 
℃の範囲のガラスであればいかなるものでも使用するこ
とができる。
The sealing glass member 6 is made by applying a well-known thick film method to a glass paste obtained by adding a suitable organic solvent to a filler-added lead borosilicate glass powder to form an insulating substrate. 1 and the lid body 2 are formed on the opposite main surfaces thereof. Further, the sealing glass member 6 is not limited to lead borosilicate glass added with a filler, and has a coefficient of thermal expansion of 60 to 90X10-'/
Any glass in the °C range can be used.

前記絶縁基体lと蓋体2との間には導電性材料から或る
外部リード端子5が配されており、該外部リード端子5
は半導体素子4の各電極がワイヤ7を介し電気的に接続
され、外部リード端子5を外部電気回路に接続すること
によって半導体素子4が外部電気回路に接続されること
となる。
An external lead terminal 5 made of a conductive material is disposed between the insulating base l and the lid 2, and the external lead terminal 5
Each electrode of the semiconductor element 4 is electrically connected via the wire 7, and the semiconductor element 4 is connected to the external electric circuit by connecting the external lead terminal 5 to the external electric circuit.

前記外部リード端子5は絶縁基体1と蓋体2の相対向す
る主面に被着させた封止用ガラス部材6を溶融一体化さ
せ、絶縁容器3を気密封止する際に同時に絶縁基体1と
蓋体2との間に取着される。
The external lead terminal 5 is formed by melting and integrating the sealing glass member 6 attached to the opposing main surfaces of the insulating base 1 and the lid 2, and simultaneously sealing the insulating base 1 when the insulating container 3 is hermetically sealed. and the lid body 2.

前記外部リード端子5はニソケル31.5乃至32.5
Wt% 、DハJL/トl6.5乃至17.5WtX 
、鉄50.0乃至52. oIIItxの合金から威る
板状体の上下面に、該板状体の厚みに対し60乃至8o
zの厚みの鋼板を接合させた金属体から成り、その透磁
率は約93 (CGS)、導電率は62.32(IAC
S) 、熱膨張係数は約71 x 10−’/℃である
The external lead terminal 5 is made of Nisokel 31.5 to 32.5
Wt%, DhaJL/Tol6.5 to 17.5WtX
, iron 50.0 to 52. The upper and lower surfaces of the plate made of oIIItx alloy have a thickness of 60 to 8 degrees relative to the thickness of the plate.
It consists of a metal body made by joining steel plates with a thickness of
S), the coefficient of thermal expansion is approximately 71 x 10-'/°C.

尚、前記外部リード端子5はニソケルーコバルトー鉄合
金(Ni−Co−Fe合金)の板状体の上下面に銅(C
u)板を圧接し、しかる後、これを圧延することによっ
て形成される。
The external lead terminals 5 are made of copper (C) on the upper and lower surfaces of a Ni-Co-Fe alloy plate.
u) Formed by pressing plates together and then rolling them.

また前記外部リード端子5はニッケル(Ni)、コバル
ト(co)、鉄(Fe)の量及び板状体と鋼板の厚みが
上述の範囲から外れると外部リード端子5の透磁率が所
望する低い値に、導電率が高い値にならなくなり、また
熱膨張係数も絶縁基体及び蓋体の熱膨張係数と合わなく
なる。そのため外部リード端子5はニッケル31.5乃
至32.5WtX , コハルトl65乃至17.5W
tX 、鉄50.0乃至52.OWtX 171合金か
ら成る板状体の上下面に、該板状体の厚みに対し60乃
至802の厚みの鋼板を接合させた金属体で形或するこ
とに限定される。
In addition, if the amount of nickel (Ni), cobalt (co), iron (Fe) and the thickness of the plate-shaped body and the steel plate of the external lead terminal 5 are out of the above-mentioned range, the magnetic permeability of the external lead terminal 5 will be a desired low value. In addition, the electrical conductivity does not reach a high value, and the thermal expansion coefficient does not match that of the insulating base and the lid. Therefore, the external lead terminal 5 is nickel 31.5 to 32.5WtX, Kohart l65 to 17.5W.
tX, iron 50.0 to 52. The metal body is limited to a metal body in which steel plates having a thickness of 60 to 80 mm are bonded to the upper and lower surfaces of a plate body made of OWtX 171 alloy.

前記外部リード端子5はその透磁率が93 (CGS)
であり、透磁率が低いことから外部リード端子5に電流
が流れたとしても外部リード端子5中には大きな自己イ
ン・ダクタンスが発生することはなくその結果、前記自
己インダクタンスにより誘発される逆起電力に起因した
ノイズを極小となし、内部に収容する半導体素子4を常
に正常に作動させることができる。
The external lead terminal 5 has a magnetic permeability of 93 (CGS)
Since the magnetic permeability is low, even if a current flows through the external lead terminal 5, a large self-inductance is not generated in the external lead terminal 5, and as a result, the back electromotive force induced by the self-inductance is Noise caused by electric power can be minimized, and the semiconductor element 4 housed inside can always operate normally.

また前記外部リード端子5はその導電率が62.32(
I^CS)以上であり、電気を流し易いことから外部リ
ード端子5の信号伝搬速度を極めて速いものとなすこと
ができ、絶縁容器3内に収容した半導体素子4を高速駆
動させたとしても半導体素子4と外部電気回路との間に
おける信号の出し入れは常に安定、且つ確実となすこと
ができる。
Further, the conductivity of the external lead terminal 5 is 62.32 (
I^CS), and since electricity can flow easily, the signal propagation speed of the external lead terminal 5 can be made extremely fast, and even if the semiconductor element 4 housed in the insulating container 3 is driven at high speed, the semiconductor Signal input and output between the element 4 and the external electric circuit can always be carried out stably and reliably.

また同時に外部リード端子5の導電率が高いことから外
部リード端子5の線幅が細くなったとしても外部リード
端子5の電気抵抗を低く抑えることができ、その結果、
外部リード端子5における信号の減衰を極小として内部
に収容する半導体素子4に外部電気回路から供給される
電気信号を正確に入力することができる。
At the same time, since the conductivity of the external lead terminal 5 is high, even if the line width of the external lead terminal 5 becomes thin, the electrical resistance of the external lead terminal 5 can be kept low, and as a result,
By minimizing the attenuation of the signal at the external lead terminal 5, it is possible to accurately input the electrical signal supplied from the external electrical circuit to the semiconductor element 4 housed inside.

また更に前記外部リード端子5はその熱膨張係数が約7
1xlO−’/ ”cであり、封止用ガラス部材6の熱
膨張係数と近似することから外部リード端子5を絶縁基
体1と蓋体2の間に封止用ガラス部材6を用いて固定す
る際、外部リード端子5と封止用ガラス部材6との間に
は両者の熱膨張係数の相違に起因する熱応力が発生する
ことはなく、外部リード端子5を封止用ガラス部材6で
強固に固定することも可能となる。
Furthermore, the external lead terminal 5 has a coefficient of thermal expansion of approximately 7.
1xlO-'/''c, which approximates the coefficient of thermal expansion of the sealing glass member 6, so the external lead terminal 5 is fixed between the insulating base 1 and the lid 2 using the sealing glass member 6. At this time, no thermal stress is generated between the external lead terminal 5 and the sealing glass member 6 due to the difference in coefficient of thermal expansion between the two, and the external lead terminal 5 is firmly secured by the sealing glass member 6. It is also possible to fix it.

かくして、この半導体素子収納用バ・7ケージによれば
絶縁基体1の凹部底面に半導体素子4を取着固定すると
ともに該半導体素子4の各電極をボンディングヮイヤ7
により外部リード端子5に接続させ、しかる後、絶縁基
体1と蓋体2とを該絶縁基体1及び蓋体2の相対向する
主面に予め被着させておいた封止用ガラス部材6を溶融
一体化させることによって接合させ、これによって最終
製品としての半導体装置が完成する。
Thus, according to this semiconductor element housing bar 7, the semiconductor element 4 is fixedly attached to the bottom surface of the recess of the insulating base 1, and each electrode of the semiconductor element 4 is connected to the bonding wire 7.
After that, the sealing glass member 6, in which the insulating base 1 and the lid 2 have been previously attached to the opposing main surfaces of the insulating base 1 and the lid 2, is connected to the external lead terminal 5. They are joined by melting and integrating, thereby completing a semiconductor device as a final product.

(発明の効果) 本発明の半導体素子収納用バッケージによれば、半導体
素子を収容するための絶縁容器を構成する絶縁基体及び
蓋体をスビネルもしくはステアタイト質焼結体で、外部
リード端子をニッケル3165乃至32.5Wt$ ,
コバルト16.5乃至17.5Wtχ、鉄50.0乃至
52.0WtXの合金から成る板状体の上下面に、該板
状体の厚みに対し60乃至802の厚みの鋼板を接合さ
せた透磁率が約93(CGS) 、導電率が62.32
(IACS) 、熱膨張係数が約71xlO−7/ ℃
の金属体で形成したことから外部リード端子に電流を流
したとしても該外部リード端子中に大きな自己インダク
タンスが発生することはなく、その結果、前記自己イン
ダクタンスにより誘発される逆起電力に起因したノイズ
を極小となし、内部に収容する半導体素子を常に正常に
作動させることが可能となる。
(Effects of the Invention) According to the semiconductor device storage package of the present invention, the insulating base and the lid constituting the insulating container for accommodating the semiconductor devices are made of Subinel or steatite sintered body, and the external lead terminals are made of nickel. 3165~32.5Wt$,
The magnetic permeability is obtained by joining steel plates with a thickness of 60 to 802 mm with respect to the thickness of the plate body to the upper and lower surfaces of a plate body made of an alloy of cobalt 16.5 to 17.5 Wtχ and iron 50.0 to 52.0 WtX. is approximately 93 (CGS) and conductivity is 62.32.
(IACS), the coefficient of thermal expansion is approximately 71xlO-7/℃
Since the external lead terminal is made of a metal body, even if a current is passed through the external lead terminal, a large self-inductance is not generated in the external lead terminal, and as a result, a large self-inductance is not generated in the external lead terminal, resulting in a back electromotive force induced by the self-inductance. It is possible to minimize noise and to always operate normally the semiconductor element housed inside.

また外部リード端子の信号伝搬速度を極めて速いものと
なすことができ、絶縁容器内に収容した半導体素子を高
速駆動させたとしても半導体素子と外部電気回路との間
における信号の出し入れを常に安定、且つ確実となすこ
とが可能となる。
In addition, the signal propagation speed of the external lead terminal can be made extremely fast, so that even if the semiconductor element housed in the insulating container is driven at high speed, the signal input and output between the semiconductor element and the external electric circuit is always stable. Moreover, it becomes possible to do so reliably and reliably.

更に外部リード端子の線幅が細くなったとしても外部リ
ード端子の電気抵抗を低く抑えることができ、その結果
、外部リード端子における信号の減衰を極小として内部
に収容する半導体素子に外部電気回路から供給される電
気信号を正確に入力することが可能となる。
Furthermore, even if the line width of the external lead terminal becomes thinner, the electrical resistance of the external lead terminal can be kept low, and as a result, the attenuation of the signal at the external lead terminal is minimized, and the external electrical circuit is connected to the semiconductor element housed inside. It becomes possible to accurately input the supplied electrical signal.

また更に外部リード端子はその熱膨張係数が絶縁基体、
蓋体及び封止用ガラス部材の各々の熱膨張係数と近似し
、絶縁基体と蓋体との間に外部リード端子を挟み、各々
を封止用ガラス部材で取着接合したとしても絶縁基体及
び蓋体と封止用ガラス部材との間、外部リード端子と封
止用ガラス部材との間のいずれにも熱膨張係数の相違に
起因する熱応力は発生せず、すべてを強固に取着接合す
ることも可能となる。
Furthermore, the coefficient of thermal expansion of the external lead terminal is
The coefficient of thermal expansion is similar to that of each of the lid body and the sealing glass member, and even if an external lead terminal is sandwiched between the insulating base body and the lid body and each is attached and bonded with the sealing glass member, the insulating base and No thermal stress is generated between the lid and the sealing glass member, nor between the external lead terminal and the sealing glass member due to differences in thermal expansion coefficients, and all are firmly attached and bonded. It is also possible to do so.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体素子収納用バンケージの一実施
例を示す断面図、第2図は第1図に示すパノケージの絶
縁基体上面より見た平面図である。 1 ・・絶縁基体  2 ・・蓋体 3 ・・絶縁容器 5 ・・外部リード端子 6 ・・封止用ガラス部材
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device storage bunkage of the present invention, and FIG. 2 is a plan view of the pano-cage shown in FIG. 1, viewed from the top surface of an insulating base. 1...Insulating base 2...Lid 3...Insulating container 5...External lead terminal 6...Glass member for sealing

Claims (1)

【特許請求の範囲】[Claims]  絶縁基体と蓋体とから成り、内部に半導体素子を収容
するための空所を有する絶縁容器と、該容器内に収容さ
れる半導体素子を外部電気回路に接続するための外部リ
ード端子とから成る半導体素子収納用パッケージにおい
て、前記絶縁基体及び蓋体をスピネルもしくはステアタ
イト質焼結体で、外部リード端子をニッケル31.5乃
至32.5Wt%、コバルト16.5乃至17.5Wt
%、鉄50.0乃至52.0Wt%の合金から成る板状
体の上下面に、該板状体の厚みに対し60乃至80%の
厚みの鋼板を接合させた金属体で形成したことを特徴と
する半導体素子収納用パッケージ。
An insulating container consisting of an insulating base and a lid and having a cavity for accommodating a semiconductor element therein, and an external lead terminal for connecting the semiconductor element housed in the container to an external electric circuit. In the package for storing semiconductor elements, the insulating base and the lid are made of spinel or steatite sintered body, and the external lead terminal is made of 31.5 to 32.5 Wt% of nickel and 16.5 to 17.5 Wt of cobalt.
%, iron is 50.0 to 52.0 Wt% alloy, and the metal body is formed by joining steel plates with a thickness of 60 to 80% of the thickness of the plate to the upper and lower surfaces of the plate. Features: A package for storing semiconductor elements.
JP1308597A 1989-08-25 1989-11-27 Package for storing semiconductor elements Expired - Lifetime JP2736453B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1308597A JP2736453B2 (en) 1989-11-27 1989-11-27 Package for storing semiconductor elements
US07/573,406 US5057905A (en) 1989-08-25 1990-08-24 Container package for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1308597A JP2736453B2 (en) 1989-11-27 1989-11-27 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH03167853A true JPH03167853A (en) 1991-07-19
JP2736453B2 JP2736453B2 (en) 1998-04-02

Family

ID=17982956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1308597A Expired - Lifetime JP2736453B2 (en) 1989-08-25 1989-11-27 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP2736453B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5711847A (en) * 1978-02-06 1982-01-21 Ibm Nonporous glass-ceramic body
JPS6043851A (en) * 1983-07-27 1985-03-08 オリン コ−ポレ−シヨン Coated metal lead frame substrate
JPS6232631A (en) * 1985-08-05 1987-02-12 Hitachi Ltd Integrated circuit package
JPS63291834A (en) * 1987-04-27 1988-11-29 コーニング グラス ワークス Glass ceramics for electronic packing, thermally crystalline glass and substrate therefrom

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5711847A (en) * 1978-02-06 1982-01-21 Ibm Nonporous glass-ceramic body
JPS6043851A (en) * 1983-07-27 1985-03-08 オリン コ−ポレ−シヨン Coated metal lead frame substrate
JPS6232631A (en) * 1985-08-05 1987-02-12 Hitachi Ltd Integrated circuit package
JPS63291834A (en) * 1987-04-27 1988-11-29 コーニング グラス ワークス Glass ceramics for electronic packing, thermally crystalline glass and substrate therefrom

Also Published As

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JP2736453B2 (en) 1998-04-02

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