JPH03166729A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03166729A JPH03166729A JP30731789A JP30731789A JPH03166729A JP H03166729 A JPH03166729 A JP H03166729A JP 30731789 A JP30731789 A JP 30731789A JP 30731789 A JP30731789 A JP 30731789A JP H03166729 A JPH03166729 A JP H03166729A
- Authority
- JP
- Japan
- Prior art keywords
- electrode wiring
- wiring layer
- contact window
- insulator
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010410 layer Substances 0.000 claims abstract description 50
- 239000012212 insulator Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電極配線層と半導体基板中の拡散層のコンタ
クト窓部分での電極配線層の平坦化を図った半導体装置
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which an electrode wiring layer is flattened at a contact window portion of a diffusion layer in a semiconductor substrate.
従来の技術
従来、第２図（ａ）〜（ｄ）に示すように半導体基板１
１の一生面上に不純物の拡散による拡散層領域１２を設
け（ａ）、その上に眉間絶縁膜１３としてＢＰＳＧ （
ホウ素−リンケイ酸ガラス）を形或し（ｂ）、続いてコ
ンタクト窓１４を開孔した後（Ｃ）、その上にアルミニ
ウム蒸着等により第１の電極配線層ｌ５を形或している
（ｄ）。2. Related Art Conventionally, as shown in FIGS. 2(a) to 2(d), a semiconductor substrate 1 is
1 (a), a diffusion layer region 12 is formed by diffusion of impurities on the surface of the film 1 (a), and a BPSG (
After forming a contact window 14 (C), a first electrode wiring layer 15 is formed thereon by aluminum evaporation or the like (d). ).
発明が解決しようとする課題
従来、第２図に示すように電極配線層１５として使われ
ているアルミニウム配線層は蒸着により形成されるため
，、段差のあるコンタクト窓では底部の周辺部の角で薄
くなる部分１６と底部の中央部で厚くなる部分１７とが
存在する。そのため、電極配線抵抗が高くなったり、時
には底部周辺部の角で薄くなる部分１６の電極配線が断
線することも見られる。またコンタクト窓１４付近で半
導体装置の段差が大きくなるなどの課題があった。Problems to be Solved by the Invention Conventionally, as shown in FIG. 2, the aluminum wiring layer used as the electrode wiring layer 15 is formed by vapor deposition. There is a thinner part 16 and a thicker part 17 at the center of the bottom. As a result, the resistance of the electrode wiring increases, and sometimes the electrode wiring in the thinner portion 16 at the corners of the bottom periphery is broken. Further, there is a problem that the difference in level of the semiconductor device becomes large near the contact window 14.
本発明はこのような課題を解決するものであり、コンタ
クト窓１４底部周辺部での電極配線抵抗値の増加または
その部分での断線をなくする半導体装置の製造方法を提
供することを目的とするものである。The present invention solves these problems, and aims to provide a method for manufacturing a semiconductor device that eliminates the increase in electrode wiring resistance around the bottom of the contact window 14 or the disconnection at that part. It is something.
課題を解決するための手段
本発明は前記課題を解決するために、半導体基板上の所
定領域に拡散層領域を形戚する工程と、それらの上に層
間絶縁膜を被着する工程と、前記層間絶縁膜にコンタク
ト窓を開孔する工程と、前記コンタクト窓部分に露出し
た前記半導体基板の拡散層領域上に第１の電極配線層を
被着する工程と、前記コンタクト窓部分で前記第１の電
極配線層の凹部に絶縁物を埋め込む工程と、前記第１の
電極配線層およびコンタクト窓の凹部に埋め込まれた絶
縁物上に第２の電極配線層を被着する工程とを有する半
導体装置の製造方法である。Means for Solving the Problems In order to solve the above problems, the present invention includes a step of forming a diffusion layer region in a predetermined region on a semiconductor substrate, a step of depositing an interlayer insulating film thereon, and a step of forming a diffusion layer region in a predetermined region on a semiconductor substrate. forming a contact window in an interlayer insulating film; depositing a first electrode wiring layer on the diffusion layer region of the semiconductor substrate exposed in the contact window; A semiconductor device comprising the steps of: embedding an insulator in the recess of the electrode wiring layer; and depositing a second electrode wiring layer on the insulator embedded in the first electrode wiring layer and the recess of the contact window. This is a manufacturing method.
作用
この半導体装置の製造方法によって、コンタクト窓の電
極配線層の平坦化が図られるとともに、電極配線抵抗を
低減することができる。Function: By this method of manufacturing a semiconductor device, the electrode wiring layer of the contact window can be planarized and the electrode wiring resistance can be reduced.
またコンタクト窓底部での第１の電極配線の断線は上部
の第２の電極配線層によって救済される。Further, a break in the first electrode wiring at the bottom of the contact window is relieved by the upper second electrode wiring layer.
実施例
以下に、第１図を参照して本発明の半導体装置の製造方
法について詳しく説明する。EXAMPLES Below, a method for manufacturing a semiconductor device according to the present invention will be explained in detail with reference to FIG.
第１図（ａ）〜（ｇ）は本発明の半導体装置の製造方法
を説明するための図である。第２図における部分と同一
部分には同一番号を付している。また第１図（ａ）から
（イ）までは第２図（ａ）から（ｄ）までと同じである
。すなわち半導体基板１１上に眉間絶縁膜１３としてＢ
ＰＳＧ （ホウ素一リンケイ酸ガラス〉を形成し（ロ）
、エッチングにより所定の個所にコンタクト窓１４を開
孔した後（Ｃ）、前記コンタクト窓１４部分に露出した
前記半導体基板の拡散層領域１２上にアルミニウム蒸着
等により第１の電極配線層１５を被着する（イ）。１６
は第１の電極配線層１５の底部周辺部の角で薄くなる部
分、１７は同じく底部中央部で厚くなる部分である。次
に前記第１の電極配線層１５の上部に絶縁物１８として
例えばポリイミドをスビンナーにより塗布した後（ｅ）
、上から全面に一様にエッチングして行く、いわゆるエ
ッチバック法により第１の電極配線層１５の凹部以外の
絶縁物（ポリイミド）を除去し、凹部に埋め込まれた絶
縁物１８−ａを残して、全面を面一になるようにした後
（ｆ）、前記第１の電極配線層１５とその第１の電極配
線層１５の凹部に埋め込まれた絶縁物１８−ａ上に第２
の電極配線層ｌ９を被着する（ｇ）。FIGS. 1(a) to 1(g) are diagrams for explaining the method of manufacturing a semiconductor device of the present invention. The same parts as those in FIG. 2 are given the same numbers. Moreover, FIGS. 1(a) to (b) are the same as FIGS. 2(a) to (d). That is, B is formed on the semiconductor substrate 11 as the glabella insulating film 13.
Forming PSG (boron monophosphosilicate glass) (b)
After opening the contact window 14 at a predetermined location by etching (C), the first electrode wiring layer 15 is covered by aluminum vapor deposition or the like on the diffusion layer region 12 of the semiconductor substrate exposed in the contact window 14 portion. put on (a). 16
17 is a portion that becomes thin at the corner of the bottom peripheral portion of the first electrode wiring layer 15, and 17 is a portion that becomes thick at the center of the bottom. Next, after applying, for example, polyimide as an insulator 18 on the upper part of the first electrode wiring layer 15 using a swinner, (e)
, the insulator (polyimide) other than the concave portion of the first electrode wiring layer 15 is removed by a so-called etch-back method in which the entire surface is uniformly etched from above, leaving the insulator 18-a embedded in the concave portion. After (f), a second layer is formed on the first electrode wiring layer 15 and the insulator 18-a embedded in the recessed portion of the first electrode wiring layer 15.
(g).
この実施例によれば、コンタクト窓１４底部での第１の
電極配線層１５が断線しても上部の′Ｎ４．２の電極配
線層１９によって救済される。According to this embodiment, even if the first electrode wiring layer 15 at the bottom of the contact window 14 is disconnected, it can be repaired by the upper electrode wiring layer 19 of 'N4.2.
なお、実施例ではコンタクト窓凹部に絶縁物としてポリ
イミドを埋め込んだが、ＳＯＧ （Ｓｐ ｉｎＯｎ Ｇ
ｌａｓｓ）を埋め込んでもよく、その他の絶縁物を用い
ることもできる。また電極配線層の材料としてアルミニ
ウム以外の材料を用いてもよい。In the example, polyimide was embedded as an insulator in the contact window recess, but SOG (SpinOn G
lass) may be embedded, or other insulators may also be used. Further, materials other than aluminum may be used as the material of the electrode wiring layer.
発明の効果
本発明の半導体装置の製造方法によれば、コンタクト窓
において、第１の電極配線層の凹部に絶縁物を埋め込み
、その上に第２の電極配線層を形成するので、コンタク
ト窓付近での半導体装置の平坦化を図ることができ、電
極配線抵抗を低減するとともに、断線もなくすことがで
きる。Effects of the Invention According to the method for manufacturing a semiconductor device of the present invention, in the contact window, an insulator is buried in the recess of the first electrode wiring layer, and the second electrode wiring layer is formed thereon. This makes it possible to planarize the semiconductor device, reduce electrode wiring resistance, and eliminate wire breakage.
この結果、電極配線層の信頼性を向上させることができ
る。As a result, the reliability of the electrode wiring layer can be improved.
【図面の簡単な説明】
の製造方法を説明するための図である。
ｌ１・・・・・・半導体基板、１２・・・・・・拡散層
領域、１３・・・・・・層間絶縁膜、１４・・・・・・
コンタクト窓、１５・・・・・・第１の電極配線層、１
８−ａ・・・・・・埋め込まれた絶縁物、１９・・・・
・・第２の電極配線層。
第７図
／ｂ
郭２図
第７図
７品己・・・理纜偉れた絶緑物[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram for explaining the manufacturing method. l1... Semiconductor substrate, 12... Diffusion layer region, 13... Interlayer insulating film, 14...
Contact window, 15...First electrode wiring layer, 1
8-a...Embedded insulator, 19...
...Second electrode wiring layer. Fig. 7/b Guo 2 Fig. 7 Fig. 7 Elegance...Refined and excellent greenery
Claims (3)
工程と、それらの上に層間絶縁膜を被着する工程と、前
記層間絶縁膜にコンタクト窓を開孔する工程と、前記コ
ンタクト窓部分に露出した前記半導体基板の拡散層領域
上に第１の電極配線層を被着する工程と、前記コンタク
ト窓部分で前記第１の電極配線層の凹部に絶縁物を埋め
込む工程と、前記第１の電極配線層およびコンタクト窓
の凹部に埋め込まれた絶縁物上に第２の電極配線層を被
着する工程とを有する半導体装置の製造方法。(1) A step of forming a diffusion layer region in a predetermined region on a semiconductor substrate, a step of depositing an interlayer insulating film thereon, a step of opening a contact window in the interlayer insulating film, and a step of forming a contact window in the interlayer insulating film. a step of depositing a first electrode wiring layer on the partially exposed diffusion layer region of the semiconductor substrate; a step of embedding an insulator in a recessed portion of the first electrode wiring layer in the contact window portion; 1. A method of manufacturing a semiconductor device, comprising the step of depositing a second electrode wiring layer on the first electrode wiring layer and an insulator embedded in the recess of the contact window.
イミドである請求項１記載の半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the insulator buried in the recessed portion of the first electrode wiring layer is polyimide.
Ｇ（Ｓｐｉｎ Ｏｎ Ｇｌａｓｓ）である請求項１記載
の半導体装置の製造方法。(3) The insulator buried in the recess of the first electrode wiring layer is SO
2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is G (Spin On Glass).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30731789A JPH03166729A (en) | 1989-11-27 | 1989-11-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30731789A JPH03166729A (en) | 1989-11-27 | 1989-11-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03166729A true JPH03166729A (en) | 1991-07-18 |
Family
ID=17967693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30731789A Pending JPH03166729A (en) | 1989-11-27 | 1989-11-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03166729A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5427980A (en) * | 1992-12-02 | 1995-06-27 | Hyundai Electronics Industries Co., Ltd. | Method of making a contact of a semiconductor memory device |
| CN1047566C (en) * | 1993-07-19 | 1999-12-22 | 施乐公司 | Auto paper size sensing mechanism for an adjustable cassette |
| JP2015142013A (en) * | 2014-01-29 | 2015-08-03 | 新日本無線株式会社 | semiconductor device |
| JP2015185792A (en) * | 2014-03-26 | 2015-10-22 | セイコーエプソン株式会社 | Wiring structure and manufacturing method therefor |
-
1989
- 1989-11-27 JP JP30731789A patent/JPH03166729A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5427980A (en) * | 1992-12-02 | 1995-06-27 | Hyundai Electronics Industries Co., Ltd. | Method of making a contact of a semiconductor memory device |
| CN1047566C (en) * | 1993-07-19 | 1999-12-22 | 施乐公司 | Auto paper size sensing mechanism for an adjustable cassette |
| JP2015142013A (en) * | 2014-01-29 | 2015-08-03 | 新日本無線株式会社 | semiconductor device |
| JP2015185792A (en) * | 2014-03-26 | 2015-10-22 | セイコーエプソン株式会社 | Wiring structure and manufacturing method therefor |
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