JPH03165059A - Static-electricity protecting circuit - Google Patents
Static-electricity protecting circuitInfo
- Publication number
- JPH03165059A JPH03165059A JP30550589A JP30550589A JPH03165059A JP H03165059 A JPH03165059 A JP H03165059A JP 30550589 A JP30550589 A JP 30550589A JP 30550589 A JP30550589 A JP 30550589A JP H03165059 A JPH03165059 A JP H03165059A
- Authority
- JP
- Japan
- Prior art keywords
- type mos
- bipolar transistor
- mos element
- parasitic bipolar
- length
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 230000003321 amplification Effects 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 230000005611 electricity Effects 0.000 abstract description 3
- 230000003068 static effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 2
- 102000003712 Complement factor B Human genes 0.000 description 1
- 108090000056 Complement factor B Proteins 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路における静電保護回路に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrostatic protection circuit in a semiconductor integrated circuit.
［従来の技術１
一般的にＬＤＤ構造もしくはＤＤＤ構造をとるＭＯＳ素
子は静電破壊に弱く、従来半導体集積回路の静電保護回
路として特開昭６０−１３６３７４号、特開昭６２−７
６６７６号に示されるように、内部回路に２重拡散ドレ
イン構造のＭＯＳ素子を使用する場合においても、静電
保護回路には１重拡散トレイン構造としたＮ型ＭＯＳ素
子を使用していた。[Prior art 1 MOS elements that generally have an LDD structure or a DDD structure are susceptible to electrostatic damage, and conventional electrostatic protection circuits for semiconductor integrated circuits have been proposed in Japanese Patent Laid-Open Nos. 60-136374 and 62-7.
As shown in No. 6676, even when a MOS element with a double diffusion drain structure was used in the internal circuit, an N-type MOS element with a single diffusion train structure was used in the electrostatic protection circuit.
［発明が解決しようとする課題〕
従来の静電保護回路は、上記のように構成されているた
め、静電保護回路と内部回路とのＮ型ＭＯ８素子の構造
が違うため製造工程数が増加してしまうという大きな問
題点があった。[Problem to be solved by the invention] Since the conventional electrostatic protection circuit is configured as described above, the number of manufacturing steps increases because the structures of the N-type MO8 elements in the electrostatic protection circuit and the internal circuit are different. There was a big problem with this.
本発明は、かかる問題点を解決するためになされたもの
であり、製造工程の増加無しに半導体集積装置の保護回
路を得ることを目的とする。The present invention was made to solve these problems, and an object of the present invention is to obtain a protection circuit for a semiconductor integrated device without increasing the number of manufacturing steps.
〔課題を解決するための手段１
本発明の静電保護回路は、Ｎ型ＭＯＳ素子に低不純物密
度ドレイン（ＬＤＤと称する）構造もしくは、２重拡散
ドレイン（ＤＤＤと称する）構造をとる静電保護回路に
於て、接地線に接続されたＰ型ＭＯＳ素子を静電保護回
路に有することを特徴とする特
［作 用］
本発明における静電保護回路は、ドレイン領域、半導体
基板、ソース領域、とによて形成される寄生バイポーラ
トランジスタを動作させ電流を流すことにより静電保護
するものである。[Means for Solving the Problems 1] The electrostatic protection circuit of the present invention provides electrostatic protection in which an N-type MOS element has a low impurity density drain (referred to as LDD) structure or a double diffusion drain (referred to as DDD) structure. In the circuit, the electrostatic protection circuit is characterized in that the electrostatic protection circuit includes a P-type MOS element connected to a ground line.[Function] The electrostatic protection circuit of the present invention includes a drain region, a semiconductor substrate, a source region, Electrostatic protection is provided by operating the parasitic bipolar transistor formed by the transistors and causing a current to flow.
［実 施 例］
第１図は本発明の一実施例を示す回路図であり、Ｍｌは
１重拡散ドレイン構造のＰ型ＭＯＳ素子、Ｍ２はＬＤＤ
構造もしくはＤＤＤ構造のＮ型ＭＯＳ素子、Ｍ３は１重
拡散トレイン構造のＰ型ＭＯＳ素子、Ｔｒｉ−Ｔｒ３は
各ＭＯＳ素子のドレイン領域、半導体基板またはＰＷＥ
ＬＬ領域、及びソース領域とによて形成される寄生バイ
ｇ −ラトランジスタ、Ａは半導体集積回路の外へ信号
を接続するためのパッドである。Ｐ型ＭＯ８素子Ｍ１及
びＮ型ＭＯＳ素子Ｍ２は半導体集積回路の出力バッファ
ーを構成している。[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention, where Ml is a P-type MOS element with a single diffused drain structure, and M2 is an LDD.
M3 is a P-type MOS element with single diffusion train structure, Tri-Tr3 is the drain region of each MOS element, semiconductor substrate or PWE
A parasitic bilayer transistor formed by the LL region and the source region, A is a pad for connecting a signal to the outside of the semiconductor integrated circuit. The P-type MO8 element M1 and the N-type MOS element M2 constitute an output buffer of the semiconductor integrated circuit.
Ｐ型ＭＯＳ素子Ｍ３のドレインはパッドＡに接続された
ノードＢに接続されゲートはＶｃｃに接続され、ソース
はＧＮＤに接続されオフ状態にある。Ｐ型ＭＯＳ素子の
ソースをＧＮＤに接続しているため、寄生バイポーラト
ランジスタＴｒ３のコレクタはＧＮＤに接続される。従
って寄生バイポーラトランジスタＴｒ３を流れる電流は
速やかにＧＮＤへ吸収される。The drain of the P-type MOS element M3 is connected to the node B connected to the pad A, the gate is connected to Vcc, and the source is connected to GND and is in an off state. Since the source of the P-type MOS element is connected to GND, the collector of the parasitic bipolar transistor Tr3 is connected to GND. Therefore, the current flowing through the parasitic bipolar transistor Tr3 is quickly absorbed into GND.
本実施例では、Ｎ型ＭＯＳ素子Ｍ２のチャンネル長つま
り寄生バイポーラトランジスタＴｒ２のベース長より、
Ｐ型ＭＯＳ素子Ｍ３のチャンネル長つまり寄生バイポー
ラトランジスタＴｒ３のベース長を短く調整する事によ
り、寄生バイポーラトランジスタＴｒ３の電流増幅率β
３を寄生バイポーラトランジスタＴｒ２の電流増幅率Ｂ
２より大きくし、静電気の印加による電流を寄生バイポ
ーラトランジスタＴｒ３により多（流し、静電気の印加
に弱いＬＤＤ構造もしくわＤＤＤ構造のＮ型ＭＯＳ素子
のドレイン領域に大きな接合電流が流れないようにする
。In this embodiment, from the channel length of the N-type MOS element M2, that is, the base length of the parasitic bipolar transistor Tr2,
By adjusting the channel length of the P-type MOS element M3, that is, the base length of the parasitic bipolar transistor Tr3, to shorten it, the current amplification factor β of the parasitic bipolar transistor Tr3 can be reduced.
3 is the current amplification factor B of the parasitic bipolar transistor Tr2
2, a large amount of current due to the application of static electricity is caused to flow through the parasitic bipolar transistor Tr3, and a large junction current is prevented from flowing into the drain region of the N-type MOS element having the LDD structure or the DDD structure, which is susceptible to the application of static electricity.
ｒ発明の効果〕
以上のように本発明によれば、通常使われる１重拡散ド
レイン構造のＰ型ＭＯＳ素子を静電保護回路に使用する
事により製造行程数の増加なしに保護効果を高める事が
出来る。r Effects of the Invention] As described above, according to the present invention, by using a commonly used P-type MOS element with a single diffused drain structure in an electrostatic protection circuit, the protection effect can be enhanced without increasing the number of manufacturing steps. I can do it.
第１図は本発明の実施例を示す静電保護回路の回路図、
第２図は従来の静電保護回路の回路図である０図におい
て、
Ｍｌ、Ｍ３・・・Ｐ型ＭＯＳ素子
Ｍ２・・・・・・Ｎ型ＭＯＳ素子
Ｔｒｉ〜Ｔｒ３・寄生バイポーラトランジスタ
Ａ・・・・・・・パッド
以
上FIG. 1 is a circuit diagram of an electrostatic protection circuit showing an embodiment of the present invention,
Fig. 2 is a circuit diagram of a conventional electrostatic protection circuit.・・・・・・More than pad
Claims (1)
する）構造もしくは、２重拡散ドレイン（ＤＤＤと称す
る）構造をとる静電保護回路に於て、接地線に接続され
たＰ型ＭＯＳ素子を有することを特徴とする静電保護回
路。In an electrostatic protection circuit that has a low impurity density drain (referred to as LDD) structure or a double diffused drain (referred to as DDD) structure in an N-type MOS element, it has a P-type MOS element connected to a ground line. An electrostatic protection circuit featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30550589A JPH03165059A (en) | 1989-11-24 | 1989-11-24 | Static-electricity protecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30550589A JPH03165059A (en) | 1989-11-24 | 1989-11-24 | Static-electricity protecting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03165059A true JPH03165059A (en) | 1991-07-17 |
Family
ID=17945965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30550589A Pending JPH03165059A (en) | 1989-11-24 | 1989-11-24 | Static-electricity protecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03165059A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5539233A (en) * | 1993-07-22 | 1996-07-23 | Texas Instruments Incorporated | Controlled low collector breakdown voltage vertical transistor for ESD protection circuits |
| EP0772238A3 (en) * | 1995-10-31 | 1999-11-24 | Texas Instruments Incorporated | Semiconductor device with protecting means |
| JP2011071327A (en) * | 2009-09-25 | 2011-04-07 | Seiko Instruments Inc | Semiconductor device |
-
1989
- 1989-11-24 JP JP30550589A patent/JPH03165059A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5539233A (en) * | 1993-07-22 | 1996-07-23 | Texas Instruments Incorporated | Controlled low collector breakdown voltage vertical transistor for ESD protection circuits |
| EP0772238A3 (en) * | 1995-10-31 | 1999-11-24 | Texas Instruments Incorporated | Semiconductor device with protecting means |
| JP2011071327A (en) * | 2009-09-25 | 2011-04-07 | Seiko Instruments Inc | Semiconductor device |
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