JPH03164848A - I/o access system - Google Patents

Abstract

PURPOSE:To increase the I/O access speed by holding data from a central processing unit (CPU) and continuously writing data in a register in an I/O device with one access from the CPU to the I/O device. CONSTITUTION:After data A is outputted to a data bus 31, an I/O control signal generating circuit 201 outputs an I/O write signal (IOWC1) 22 to write data A in an I/O device LSI 17. The I/O control signal generating circuit 201 outputs the I/O write signal (IOWC1) 22 while data B is outputted to a data bus 31, and data B is written in the I/O device LSI 17. In the same manner, the I/O control signal generating circuit 201 outputs the I/O write signal (IOWC1) 22 while data C is outputted to the data bus 31, and data C is written in the I/O device LSI 17. Thus, data is written in the I/O device LSI 17 three times with one access of a CPU 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to information processing devices such as personal combinators and terminals, and particularly relates to universal I/O access using a high-performance CPU.

[Conventional technology]

In recent years, the performance and functionality of engineering/output devices have improved, and a wide variety of LSIs have been developed. These LSIs are
For high functionality, it has a large number of internal registers.For example, Hitachi's LSI for image processing@HD1
53/O9 (color palette LSI with built-in 3-channel 6-bit DA converter) can display 256 out of 260,000 colors simultaneously. This expresses each color of red, green, and blue with 6 bits each, and has 256 built-in 18-bit (6 bits x 3) registers, allowing 256 out of 260,000 colors to be displayed simultaneously.

[Problem to be solved by the invention]

In the above LSI, in order to reduce the number of pins on the package,
The data bus width is often 8 bits. Also,
In order to set all internal registers of the LSI, as shown in Figure 5, I/O accesses such as setting red data, setting green data, and setting back data must be performed as shown in Figure 5.
It is necessary to transfer data to the internal registers of the CPU by repeating Miro's processing six times in total, 256 times. This is LS
This is because the data bus width of I is 8 bits, so red, green, and blue data cannot be set in -times of I/O access.

Therefore, there is a problem in that the data setting processing time for the LSI is almost the same even when using the CPTJ or the high-performance 32-bit CPt1 shown in FIG. 3.

The purpose of the present invention is to provide I/O to I/O devices such as LSI.
The purpose is to provide high-speed access.

[Means to solve the problem]

In order to achieve the above object, the present invention provides an information processing apparatus that has a central processing unit and a plurality of I/O devices and that exchanges data between the central processing unit and the I/O devices. a holding means for holding data from the apparatus; a selection means for selecting data held by the holding means; and a control means for controlling access to the holding means, the selection means, and the I/O device; One access from the device to the I/O device allows data to be continuously loaded into the registers in the I/O device.

[Effect]

In the construction/O access universal type according to the present invention, the holding means is the CP
Holds write data from U to I/O devices I and II. Further, the selection means selects data to be given to the E/O device LSI from among the data held by the holding means. Seriously, what is the control method?

The data holding operation of the holding means and the data selection operation of the selection means are controlled. At the same time, it also controls access to the I/O device LSI. Finally, when writing from the CPU to the I/O device LSI is performed, the holding means is controlled to hold the write data from the CPU.

At the same time, the I/O write signal (xowc signal)
When the control means outputs a wait signal (WAI'l' signal) to the CPU, the access is postponed. The control means controls the selection means and the I/O device LSI so that writing of data to the I/O device LSI is performed continuously as shown in the time chart of FIG. That is, data A, B, and C are successively written to the I/O device LSI with one access from CPt1.

Therefore, multiple pieces of data can be written to the x/O device with one access from the CPU.

In addition, data can be written to the I/O device at a higher speed than in the prior art. Moreover, the writing processing program is also about 10% lower than the conventional one, as shown in Figure 4.
It can be reduced to 15.

〔Example〕

An embodiment of the present invention will be explained below with reference to FIGS. 1, 2, and 6. 1G is a CPU. 11゜'2115.1
4 is a data bus, and 15 is an address bus. 16 is c
I/O write signal (IOwc) output from ptz o
). 17 is an I/O device LSI. Reference numeral 20 denotes a control means, which is composed of an I/O control control generation circuit 201, a latch signal generation circuit 202, and a % selection means control circuit 203. 21 is a wait signal (WAIT
), 22 is the I/O device LS117.
This is an O write signal (Iowcl).

23 is a latch signal to the holding means 25.

24 is a selection control signal of the selection means 26. 51 is a bus for data output from the selection means 26. Also,
Reference numeral 204 in FIG. 2 is a control number 4M to the latch signal generation circuit 202 and the selection means control circuit 203, which is output from the I/O control control generation circuit 201.

Next, the operation of this embodiment will be explained. This converts the 32-bit cpalo to the 8-bit I/O device LS11
7, a case where it is necessary to import data continuously will be explained.

First, the CPU/O performs write access to the I/O device LS117. When an access is started, CPTJlo outputs the address and data to the address bus 15 and data bus 11, 12, 15, and 14, respectively, and also outputs an I/O write signal (xowc) t-. Output work/O light signal (IOWC) 16
is input to the control means 20, the internal I/O control signal generation port 201 outputs a wait signal (WA11') 21 to postpone access to CPt1/O.
At the same time, the control signal 204 is transmitted to the latch signal generation circuit 2.
Output to 02. The latch signal generation circuit 202 generates a latch signal 23 to the 1 holding means 25 based on this control signal 204. The holding means 25 uses this latch signal 23 to hold data A, B, and C (FIG. 6) on the data buses 11, 12, and 13. Additionally, the selection means control circuit 205 outputs the control signal 24 and controls the selection means 26 so that the data A is outputted to the data bus 31. Data A is data bus 3
1, the I/O control generation circuit 201
I/O write signal (Iowct) 22f: Output and write data A to the I/O device LS117. Next, the 1 selection means control circuit 203 outputs the control signal 24 so that the selection means 26t-
Control. While the data B is being output to the data bus 31, the F0 control signal generation circuit 201 outputs the I/O write signal (IOWCl) 22, and the data Bt-I/O
Write to device LS117. Similarly, the 1 selection means control circuit 203 outputs a control signal 24 and controls the selection means 26 so that data C is output to the data bus 31.

While data C is being output to the data bus 31,
The O control control generation circuit 201 generates an I/O write signal (IO
WCl) 22 and writes the data Ct-I/O device LS117. When the writing of data C is completed, the I/O control control generation circuit 201 releases the wait signal (WAIte) to CPTJlo and accesses end. In this way, with one access to CPTJlo,
Data can be written to the I/O device LS117 three times.

The same effect can be obtained by using a 16-bit CPU% or a 64-bit CPU for CPTJlo.

It goes without saying that the present invention can also be applied to an I/O device 17 that requires data to be written three or four times or more consecutively, such as a DMA controller.

Next, the effects of this example will be explained at 70 in FIGS. 4 and 5.
-Explain using a chart. FIG. 4 is a 70-chart when data is continuously written to the X/O device LSI using the present invention. FIG. 5 is a 70-chart when data is continuously written into the I/O device LSI using the conventional technique.

In the conventional technology shown in Fig. 5, when writing data to the I/O device LSI, it is necessary to transfer data to the register inside the CPTJ three times. There is.

On the other hand, in the present invention shown in FIG.
When writing data to the SI, all data needs to be transferred to the registers inside the CPU, and the data is transferred from the CPU to the I
Writing data to the /O device LSI appears to be -
Therefore, compared to the conventional technology, the data transfer command to the register inside the CPU is executed three times, and the X/O device LS
Since it is not necessary to execute the data write command to I three times, data t- can be written to the I/O device LSI at high speed.

In addition, the writing program is also different from conventional technology.
It can be reduced to about 173.

, [Effects of the Invention] According to the present invention, when data is continuously written to the I/O device LSI, it can be performed with one access from the CPU, and high-speed access is possible. Also, the number of writing programs can be significantly reduced compared to the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of the control means in FIG. 1, FIG. 3 is a block diagram showing the prior art, and FIGS. 4 and 5 are block diagrams. Flowchart explaining the effect of the embodiment of FIG. 1, No. 6
The figure is a timing chart of the operation of FIG. 1. /O... CPU, 201... I/O control signal generation circuit, 20... Control means, 202... Latch signal generation circuit, 21... Wait signal, 203... Selection means control circuit , 25... Holding means, 26... Selection means.

Claims (1)

[Claims] 1. In an information processing apparatus that includes a central processing unit and a plurality of I/O devices and that exchanges data between the central processing unit and the I/O devices, a holding unit that holds data from the central processing unit. a selection means for selecting data held by the holding means; a control means for controlling access to the holding means, the selection means, and the I/O device; An I/O access method characterized in that data is continuously written to a register in the I/O device by one access to the device.