JPH0316139A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH0316139A
JPH0316139A JP2038757A JP3875790A JPH0316139A JP H0316139 A JPH0316139 A JP H0316139A JP 2038757 A JP2038757 A JP 2038757A JP 3875790 A JP3875790 A JP 3875790A JP H0316139 A JPH0316139 A JP H0316139A
Authority
JP
Japan
Prior art keywords
gate electrode
conductive film
film
conductivity type
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2038757A
Other languages
Japanese (ja)
Other versions
JP2926833B2 (en
Inventor
Masahiro Takeuchi
正浩 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to KR1019900004032A priority Critical patent/KR0179656B1/en
Priority to US07/500,200 priority patent/US5097300A/en
Priority to EP90303269A priority patent/EP0390509B1/en
Priority to DE69032446T priority patent/DE69032446T2/en
Publication of JPH0316139A publication Critical patent/JPH0316139A/en
Priority to US07/733,643 priority patent/US5147814A/en
Priority to HK98109971A priority patent/HK1009308A1/en
Application granted granted Critical
Publication of JP2926833B2 publication Critical patent/JP2926833B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode

Abstract

PURPOSE:To reduce an irregularity in a characteristic by a method wherein a second gate electrode length is made shorter than a first gate electrode length and a first source region and a first drain region are situated so as to be faced by sandwiching a first gate electrode and a first insulating film. CONSTITUTION:A second gate electrode length is made shorter than a first gate electrode length; a first source region and a first drain region which have been installed on a semiconductor substrate on both sides of a second gate electrode are situated so as to be faced by sandwiching a first gate electrode and a first insulating film. That is to say, the gate electrode by a polycrystalline silicon film 103 is overlapped with a low-concentration n-type impurity layer 106; when a voltage is applied to the gate, an apparent resistance of the low- concentration n-type impurity layer 106 is lowered by its electric field; an electric field in a transverse direction inside the low-concentration n-type impurity layer 106 is relaxed. Thereby, an irregularity in a characteristic is reduced.

Description

【発明の詳細な説明】[Detailed description of the invention] 【産業上の利用分野】[Industrial application field]

本発明は半導体装置、特にＭＯＳ型またはＭＩＳ型半導
体装置の製造方法に関する． ［従来の技術］ 半導体装置の微細化、高集積化にともないＭＯＳ型トラ
ンジスタら微細化されてきている．しかし、素子寸法を
微細化することによりホットキャリアによる特性劣化と
いう問題が生じてきている。この問題を解決するためＬ
ＤＤ（Ｌｉｇｈｔｌｙ　　Ｄｏｐｅｄ　　Ｌｒａｉｎ）
という構造が提案されているが、このＬＤＤをさらに改
良した構造が次の文献に掲載されている，（Ｒ．ＩＺＡ
ＷＡ，Ｔ．ＫＵＲＥ，Ｅ．ＴＡＫＥＤＡ，”ＴＨＥＩＭ
ＰＡＣＴ　　ＯＦ　　ＧＡＴＥ−ＤＲＡＩＮ　　ＯＶＥ
ＲＬＡＰＰＥＤ　　ＬＤＤ　（ＧＯＬＤ）　　ＦＯＲ　
　ＤＥＥＰ　　ＳＵＢＭＩＣＲＯＮ　　ＶＬＳＩ’Ｓ”
　　ＩＥＤＭ　　Ｔｅｃｈ　　Ｄｉｇ．　ＰＰ３８−Ｐ
Ｐ４１１９８７．）この文献による製造方法を第２図を
用いて説明する．第２図において２０１はＰ型半導体基
板、２０２はゲート酸化膜、２０３は多結晶シリコン膿
、２０４は自然酸化膜、２０５は多結晶シリコン月莫、
２０６｛まシリコン酸化月莫，２０７は不純物濃度の濃
いｎ型不純物層、２０８は酸化膜によるサイドウ才一ル
、２０９は不純物濃度の濃いｎ型不純物層、２１０は酸
化膜である．まずＰ型半導体基板２０１を熱酸化するこ
とでゲート酸化膜２０２を形成する．次にＣＶＤ法によ
り多結晶シリコン膜２０３を薄く形成した後、空気中に
放置して５〜１０人の自然酸化１ｌＪ１２０４を形成す
る。続いてＣＶＤ法により多結晶シリコンＩＩ！　２　
０　５、シリコン酸化ＩＩ＠２　０　６を順次形成する
．次に第２図（ａ）のようにシリコン酸化膜２０６の不
要部分を写真触刻法により除去する．次に第２図（ｂ）
のように酸化膜２０６をマスクにドライエッチングを行
なうことによって、多結晶シリコン膜２０５の不要部分
を除去する．次にシリコン酸化膜２０６および多結晶シ
リコン膜２０５をマスクにｎ型不純物であるリンをイオ
ン注入することによりｎ型不純物層２０７を形成する．
次にＣＶＤ法によりシリコン酸化１！２０８を形成後ド
ライエッチングを行なうことにより第２図（Ｃ）のよう
にシリコン酸化膜によるサイドウ才一ル絶縁Ｍ２０８を
形成する．次に第２図（ｄ）のようにウェット雰囲気中
で８００℃の酸化を行なうことにより酸化膜２１０を形
成する．次にゲート電極２０３、２０５、酸化膜２０６
、サイドウ才一ル絶縁膜２０８をマスクにｎ型不純物で
あるヒ素をイオン注入することによりｎ型不純物層２０
９を形或する． ［発明が解決しようとする課題］ しかし、前述の従来技術では酸化膜２１０の横方向の長
さによりＭＯＳ型トランジスタの特性が大きく変化する
が、この横方向の長さは多結晶シリコン膜２０３の膜厚
と、ウエット雰囲気中の酸化条件により決定されるので
寸法制御がむずかしく、特にＭＯＳ型トランジスタのゲ
ート長がサブミクロン領域まで微細化されていると、酸
化１１ｉ２１０の横方向の長さの寸法バラツキによりト
ランジスタ特性が大きく変化してしまうという課題を有
する。 さらに前述の従来技術ではＣＶＤ法でシリコン酸化Ｉｔ
＠２　０　８を形成する際、ゲート電極２０３、２０５
上の酸化ＩＩＭ２　０　６がオーバーハングになってい
るため、第３図のように、この部分の酸化膜のつきまわ
りが悪くなり空洞３１１ができてしまう。その結果ＭＯ
Ｓ型トランジスタの耐湿性が悪くなるという課題を有す
る． さらに前述の従来技術では、ＭＯＳ型トランジスタを形
成するとチャンネル上の合計の膿厚はゲート酸化膜２０
２と、多結晶シリコン膜２０３と、自然酸化膜２０４と
、多結晶シリコン膜２０５と、シリコン酸化ＩＩ！　２
　０　６の合計の膜厚となるため段差が大きくなってし
まう．その結果ゲート電極上にさらに配線層を形成して
、その配線層がゲート電極を横切ると前記段差のため前
記ゲート電極上の配線層に断線が生じたり、前記ゲート
電極上の配線層を形成するときにエッチング残りによる
配線ショートが生じたりする． そこで本発明はこのような課題を解決するもので、その
目的とするところはトランジスタの特性のばらつきの少
ない、しかも耐湿性のよい、ゲート電極上の配線層に断
線，ショートのない半導体装置を提供するところにある
． ［課題を解決するための手段］ 本発明の半導体装置の構造は、第１導電型の半導体基板
上に設けられた第１の絶縁膜と、前記第１の絶縁膜上に
設けられた第１の導電膜による第１のゲート電極と、前
記第１のゲート電極上に設けられた第２の導電膜による
第２のゲート電極と，前記第２のゲート電極の両側の前
記半導体基板に設けられた第２導電型の不純物を有する
第１のソース領域およびドレイン領域と、前記第１のゲ
ート電極の両側の前記半導体基板に設けられた第２導電
型の不純物を有する第２のソース領域およびドレイン領
域からなる半導体装置において、前記第２のゲート電極
長が前記第１のゲート電極長より短く、前記第２のゲー
ト電極の両側の前記半導体基板に設けられた前記第１の
ソース領域およびドレイン領域が、前記第１のゲート電
極と、前記第１の絶縁膿をはさんで対向して位置してい
ることを特徴とする． また、本発明の半導体装置の製造方法は、第１導電型の
半導体基板に第１の絶縁膜を形戊する工程と、前記第１
の絶縁膿上に餉１の導電膜を、前記第１の導電膜上に第
２の導電膜を順次形成する工程と、前記第１の導電膜お
よび前記第２の導電膜によりＭＯＳ型トランジスタのゲ
ート電極を形成する工程と、熱アニールを加える工程と
、前記ゲート電極をマスクに前記半導体基板に第２導電
型の第１の不純物をイオン注入する工程と、前記半導体
基板および前記ゲート電極に第２の絶縁膜を形成した後
、異方性イオンエッチングを行ない前記ゲート電極に第
２の絶縁膿によるサイドウォール絶縁膜を形成する工程
と、前記ゲート電極と前記サイドウォール絶縁膿をマス
クに第２導電型の第２の不純物を導入する工程からなる
ことを特徴とする．The present invention relates to a method for manufacturing a semiconductor device, particularly a MOS type or MIS type semiconductor device. [Prior Art] As semiconductor devices become smaller and more highly integrated, MOS transistors and other devices are becoming smaller. However, miniaturization of element dimensions has led to the problem of deterioration of characteristics due to hot carriers. To solve this problem L
DD (Lightly Doped Lrain)
However, a further improved structure of this LDD is published in the following document (R. IZA
WA, T. KURE, E. TAKEDA,” THEIM
PACT OF GATE-DRAIN OVE
RLAPPED LDD (GOLD) FOR
DEEP SUBMICRON VLSI’S”
IEDM Tech Dig. PP38-P
P411987. ) The manufacturing method according to this document will be explained using Figure 2. In FIG. 2, 201 is a P-type semiconductor substrate, 202 is a gate oxide film, 203 is a polycrystalline silicon film, 204 is a natural oxide film, 205 is a polycrystalline silicon film,
206 is a silicon oxide layer, 207 is an n-type impurity layer with a high impurity concentration, 208 is a side layer formed by an oxide film, 209 is an n-type impurity layer with a high impurity concentration, and 210 is an oxide film. First, a gate oxide film 202 is formed by thermally oxidizing a P-type semiconductor substrate 201. Next, after forming a thin polycrystalline silicon film 203 by the CVD method, it is left in the air to form 5 to 10 natural oxide layers. Next, polycrystalline silicon II! was made using the CVD method. 2
0 5, silicon oxide II@2 0 6 are formed in sequence. Next, as shown in FIG. 2(a), unnecessary portions of the silicon oxide film 206 are removed by photolithography. Next, Figure 2(b)
By performing dry etching using the oxide film 206 as a mask, unnecessary portions of the polycrystalline silicon film 205 are removed. Next, an n-type impurity layer 207 is formed by ion-implanting phosphorus, which is an n-type impurity, using the silicon oxide film 206 and the polycrystalline silicon film 205 as masks.
Next, a silicon oxide layer 1208 is formed by the CVD method, and then dry etching is performed to form a sidewall insulation layer M208 made of silicon oxide film, as shown in FIG. 2(C). Next, as shown in FIG. 2(d), oxidation is performed at 800° C. in a wet atmosphere to form an oxide film 210. Next, gate electrodes 203, 205, oxide film 206
The n-type impurity layer 20 is formed by ion-implanting arsenic, which is an n-type impurity, using the sidewall insulating film 208 as a mask.
Shape 9. [Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, the characteristics of the MOS transistor vary greatly depending on the lateral length of the oxide film 210; Dimensional control is difficult because it is determined by the film thickness and the oxidation conditions in the wet atmosphere, and especially when the gate length of a MOS transistor is miniaturized to the submicron region, the lateral length of the 11i210 oxide will vary. However, there is a problem in that the transistor characteristics change significantly. Furthermore, in the prior art described above, silicon oxidation It is
When forming @208, gate electrodes 203 and 205
Since the upper oxidized IIM 2 0 6 has an overhang, the coverage of the oxide film in this area becomes poor and a cavity 311 is formed as shown in FIG. As a result, M.O.
The problem is that the moisture resistance of the S-type transistor deteriorates. Furthermore, in the above-mentioned conventional technology, when a MOS transistor is formed, the total thickness of the layer on the channel is equal to or smaller than the gate oxide film 20.
2, polycrystalline silicon film 203, natural oxide film 204, polycrystalline silicon film 205, and silicon oxide II! 2
Since the total film thickness is 0.6, the difference in level becomes large. As a result, if a wiring layer is further formed on the gate electrode and the wiring layer crosses the gate electrode, the wiring layer on the gate electrode may be disconnected due to the step, or the wiring layer on the gate electrode may be formed. Sometimes, wiring shorts may occur due to etching residue. The present invention is intended to solve these problems, and its purpose is to provide a semiconductor device with less variation in transistor characteristics, good moisture resistance, and no disconnections or short circuits in the wiring layer above the gate electrode. It's there. [Means for Solving the Problems] The structure of the semiconductor device of the present invention includes a first insulating film provided on a semiconductor substrate of a first conductivity type, and a first insulating film provided on the first insulating film. a first gate electrode made of a conductive film, a second gate electrode made of a second conductive film provided on the first gate electrode, and a second gate electrode provided on the semiconductor substrate on both sides of the second gate electrode. a first source region and a drain region having impurities of a second conductivity type, and a second source region and a drain region having impurities of a second conductivity type provided in the semiconductor substrate on both sides of the first gate electrode; In the semiconductor device, the second gate electrode length is shorter than the first gate electrode length, and the first source region and drain region are provided in the semiconductor substrate on both sides of the second gate electrode. are located opposite to the first gate electrode with the first insulating layer sandwiched therebetween. Further, the method for manufacturing a semiconductor device of the present invention includes a step of forming a first insulating film on a semiconductor substrate of a first conductivity type;
A step of sequentially forming a first conductive film on the insulating film and a second conductive film on the first conductive film, and forming a MOS transistor using the first conductive film and the second conductive film. a step of forming a gate electrode; a step of applying thermal annealing; a step of ion-implanting a first impurity of a second conductivity type into the semiconductor substrate using the gate electrode as a mask; After forming the second insulating film, anisotropic ion etching is performed to form a second sidewall insulating film on the gate electrode using the gate electrode and the sidewall insulating film as a mask. It is characterized by a step of introducing a second impurity of conductivity type.

【実　施　例】【Example】

本発明の実施例を第１図を用いて説明する．まず第１図
（ａ）のように第１導電型半導体基板、ここではボロン
を拡散したＰ型シリコン基板１０ｌを酸化性雰囲気中で
１０００℃の酸化を行ない、１５０人のゲート酸化１１
１１　０２を形成し、続いてＣＶＤ法により多結晶シリ
コン１１１０３を１０００人〜３０００人形成し、熱拡
散によりリンを１０”ｃｍ−”以上ドーピングした後、
続いてスパッタ法により高融点金属、ここではモリブデ
ン膜１０４を１　５００人〜４０００人形成する．次に
第１図（ｂ）のように写真触刻法により前記多結晶シリ
コン膜１０３および前記モリブデン膜ｌＯ４の不要部分
を除去してＭＯＳ型トランジスタのゲート電極を形成す
る．次に８５０℃〜１１００℃の熱アニールを加えると
、前記モリブデン膜１０４が下層の多結晶シリコン膜１
０３と反応し、モリブデンシリサイド膜１０５になる．
このとき、このモリブデンシリサイド膜１０５の体積は
前記モリブデン膜１０４の体積よりも小さくなる．この
体積減少率は一般には、モリブデンシリサイドＭ　ｏ　
Ｓ　ｉ　ｍで２７％、タングステンシリサイドＷ　Ｓ　
ｉ　＊で２７％、タンタルシリサイドＴａＳｉｔで２５
％、チタンシリサイドＴ　ｉ　Ｓ　ｉ　＊で２３％であ
る．そこで本実施例のようなモリブデンポリサイドによ
るゲート電極では第１図（Ｃ）のように前記ゲート電極
のモリブデンシリサイドＩｆ！　ｌ　Ｏ　５のみがとり
わけ横方向に収縮する．この収縮量は本実施例の範囲で
、ＭＯＳ型トランジスタのエッチング後のゲート長を０
．８ｕｍとすると，ゲート電極の両側の合計で０．０５
μｍ〜０．２μｍになる．よって熱アニール後の多結晶
シリコン上のモリブデンシリサイド膜の寸法は０．６μ
ｍ〜０．７５μｍになる．そして、この収縮量は多結晶
シリコン膜１０３の膜厚、モリブデン膜１０４の膜厚、
ゲート電極形成後の熱アニールの温度を変えれば、容易
に、しかも精度よく制御できる．次に第１図（ｄ）のよ
うにｎ型不純物、ここではリンを加速電圧８０ＫｅＶ〜
２００ＫｅＶ、ドーズ量５×１０目〜５Ｘ　Ｉ　Ｏ”ｃ
ｍ−”でイオン注入すると、多結晶シリコンＩｌｌ　ｌ
　Ｏ　３とモリブデンシリサイド膜１０５によるゲート
電極乍のシリコン基板にはリンは注入されず、モリブデ
ンシリサイド膜の収縮した部分の多結晶シリコンｌＩＩ
１０３によるゲート電極下のシリコン基板にはリンが浅
く注入され、またゲート電極の存在しないソース、ドレ
イン領域にはシリコン基板に深くリンが注入されて不純
物濃度の薄いｎ型不純物層１０６が形成される．このと
きの不純物プロファイルを第１図（ｄ）の実施例で示す
と、ゲート酸化ＩｌｌＩＩＯ２の膜厚を１５０人、多結
晶シリコンＩｌｌ　１　０　３の膿厚を２０００＾、モ
リブデン膜１０４の膿厚を２５００人形成し．ＭＯＳ型
トランジスタのゲート電極長を０　８μｍとなるよう異
方性エッチングを行ない、１　０００℃の熱アニールを
加えると、モリブデンシリサイドＩｌｌ　１　０　５が
形成される．このときモリブデンシリサイド膜は横方向
に片側約０．ｌｕｍずつ収縮し、その長さは約０．６μ
ｍになる．次にリンを加速電圧１６０ＫｅＶ、ドーズ量
３ｘ　１　０”ｃｍ−”でイオン注入すると、多結晶シ
リコンＩＩＩ　１　０　３とモリブデンシリサイドＩｔ
！１　０５によるゲート電極下のシリコン基板のチャン
ネル領域にはリンは注入されず、モリブデンシリサイド
膜の収縮した部分の多結晶シリコン膜１０３によるゲー
ト電極下のシリコン基板にはリンが浅く注入され、その
ジャンクションの深さＡは約０　２μｍ、リンの不純物
濃度分布のピークの深さは約０．０５ｕｍ、その濃度は
約Ｉ　Ｘ　１　０”ａｍ−”となる．またゲート電極の
存在しないソース、ドレイン領域にはシリコン基板に深
くリンが注入され、そのジャンクションの深さＢは約０
．４ｕｍ、リンの不純物濃度分布のピークの深さは約０
５２５μｍ，その濃度は約ＩＸＩＯ”ｃｍ−”となる．
なおこれらの不純物プロファイルのデータは後に加える
９５０℃２０分のアニール後のデータであることを付け
加えておく．以上のように第１図（ｄ）までの実施例に
おいてもトランジスタは動作するが、ソース、ドレイン
領域のシート抵抗を下げるため次のような工程を引き続
き行なう．第１図（ｅ）のように、ゲート電極およびシ
リコン基板上にＣＶＤ法によりシリコン酸化膜を４００
０Ａ〜ｓｏｏｏ入形成した後、反応性イオンエッチング
を行ないサイドゥオール酸化１１＠Ｌ　Ｏ　７を形成す
る．次に第１図（ｆ）のようにｎ型不純物、ここではヒ
素を加速電圧５０ＫｅＶ〜ｌ５０ＫｅＶ、Ｆ−スＪｌ　
Ｉ　Ｘ　１　０　”　〜ｌ　ｘ１０”ａｍ””でイオン
注入した後、９ｏｏ℃〜１０００℃で熱アニールを行な
い不純物濃度の濃いｎ型不純物層１０Ｂを形成する．な
おサイドゥオール酸化１ｌ１１０７を形成せずにｎ型不
純物層１０８を同様に形成してちょい． 以上のような工程により形成されたＭＯＳ型トランジス
タでは、低濃度ｎ型不純物層１０６上に多結晶シリコン
膜１０３によるゲート電極がオーバーラップしているの
でゲートに電圧を加えると、その電界により低濃度ｎ型
不純物層１０６の見かけ上の抵抗が下がり、また低濃度
ｎ型不純物層１０６内の横方向電界が緩和される．その
結果トランジスタのドレイン電流が増加し、ホットキャ
リアによるコンダクタンスの劣化が避けられる． また、本実施例によれば低濃度ｎ型不純物層１０６上の
多結晶シリコン膜によるゲート電極のオーバーラップし
た長さによりＭＯＳ型トランジスタの特性が大きく変化
するが、この幅は多結晶シリコン膜１０３の膜厚、モリ
ブデン膜１０４の膿厚、ゲート電極形成後の熱アニール
の温度を変えれば容易に、しかも精度よく制御できる．
従ってＭＯＳ型トランジスタの特性のばらつきが少なく
なる． また、本実施例ではオーバーハングになるところがない
ため空洞ができずトランジスタの耐湿性が悪くなること
はない． さらに、本実施例ではチャンネル上の合計の膜厚は、ゲ
ート酸化膜１０２と、多結晶シリコン膜１０３と、モリ
ブデンシリサイドＩｌｌ　１　０　５の合計の膜厚とな
るため、ゲート電極上にさらに配線層を形成した場合そ
の配綿層がゲート電極を横切っても、段差が小さいため
前記ゲート電極上の配線層を形成するときにエッチング
残りによる配線ショートが生じることはない． 本実施例では多結晶シリコン膜上の高融点金属膜として
モリブデンを使用したが、タングステン、チタン、プラ
チナ、コバルト、ニッケル、タンタルを使用しても同様
な効果が期待できる。またこれら高融点金属シリサイド
膜を使用してもよい。 また本実施例では低濃度ｎ型不純物層のｎ型不純物とし
てリンを使用したが、ヒ素、アンチモンを使用してもよ
いし、リンとヒ素のようにこれらの不純物を組み合わせ
て導入してもよい．また本実施例では高濃度ｎ型不純物
層のｎ型不純物としてヒ素を使用したが、リン、アンチ
モンを使用してちよいし、リンとヒ素のようにこれらの
不純物を組み合わせて導入してもよい．さらに本実施例
ではＰ型半導体基板の不純物としてボロンを使用したが
、ガリウム、アルミニウム、インジウムを使用してもよ
い． 本実施例ではｎチャンネルＭＯＳ型トランジスタについ
て述べたが、ＰチャンネルＭＯＳ型トランジスクに応用
しても同様な効果があることは言うまでもない． 【発明の効果］ 本発明によれば、ＭＯＳ型トランジスタのドレイン電流
が増加し、しかもホットキャリアによるコンダクタンス
の劣化が避けられる．従って高速でかつ高信頼性のＭＯ
Ｓ型トランジスタを提供できる． また、本発明によればＭＯＳ型トランジスタの特性を左
右する、低濃度不純物層によるソース、ドレイン領域と
ゲート電極の才一パーラップの長さを精度よく、ばらつ
きを少なく加工できるのでＭＯＳ型トランジスタのドレ
イン電流、コンダクタンスのばらつきを小さくできる。 また、本発明によればＭＯＳ型トランジスタの耐湿性は
悪くならない． また、本発明によればゲート電極上の配線層の断緯、シ
ョートが少なくなる． 以上のことから本発明による半導体装置によれば、高速
，高品質、高信頼性、高歩留まりの半導体装置を提供で
きる効果がある．An embodiment of the present invention will be explained using FIG. First, as shown in FIG. 1(a), 10 liters of a first conductivity type semiconductor substrate, here a P-type silicon substrate with boron diffused therein, was oxidized at 1000°C in an oxidizing atmosphere.
1102 is formed, followed by forming 1000 to 3000 polycrystalline silicon 11103 by CVD method, and doping 10 cm or more of phosphorus by thermal diffusion.
Subsequently, a film 104 of a high melting point metal, in this case molybdenum, is formed by 1,500 to 4,000 layers by sputtering. Next, as shown in FIG. 1(b), unnecessary portions of the polycrystalline silicon film 103 and the molybdenum film 1O4 are removed by photolithography to form a gate electrode of a MOS type transistor. Next, when thermal annealing is applied at 850°C to 1100°C, the molybdenum film 104 is removed from the underlying polycrystalline silicon film 1.
03 to form a molybdenum silicide film 105.
At this time, the volume of this molybdenum silicide film 105 becomes smaller than the volume of the molybdenum film 104. This volume reduction rate is generally determined by molybdenum silicide M o
27% in S i m, tungsten silicide W S
27% for i*, 25% for tantalum silicide TaSit
%, titanium silicide T i S i * is 23%. Therefore, in the gate electrode made of molybdenum polycide as in this embodiment, as shown in FIG. 1(C), the molybdenum silicide If! Only l O 5 specifically contracts laterally. This amount of shrinkage is within the range of this example, and the gate length after etching of the MOS transistor is 0.
．． If it is 8um, the total on both sides of the gate electrode is 0.05
It becomes μm to 0.2 μm. Therefore, the dimension of the molybdenum silicide film on polycrystalline silicon after thermal annealing is 0.6μ.
m to 0.75 μm. The amount of shrinkage is determined by the thickness of the polycrystalline silicon film 103, the thickness of the molybdenum film 104,
This can be easily and precisely controlled by changing the temperature of thermal annealing after gate electrode formation. Next, as shown in Fig. 1(d), an n-type impurity, here phosphorus, is added at an acceleration voltage of 80 KeV ~
200KeV, dose amount 5×10th ~ 5X I O”c
When ion implantation is performed with m-”, polycrystalline silicon Ill l
Phosphorus is not implanted into the silicon substrate with the gate electrode made of O 3 and the molybdenum silicide film 105, and the polycrystalline silicon III in the contracted portion of the molybdenum silicide film is
103, phosphorus is shallowly implanted into the silicon substrate under the gate electrode, and phosphorus is deeply implanted into the silicon substrate in the source and drain regions where the gate electrode does not exist, forming an n-type impurity layer 106 with a thin impurity concentration. ．． The impurity profile at this time is shown in the example shown in FIG. 1(d). The thickness of the gate oxide IllIIO2 is 150, the thickness of the polycrystalline silicon Ill103 is 2000^, and the thickness of the molybdenum film 104 is 2000^. 2500 people formed. When anisotropic etching is performed to make the gate electrode length of the MOS transistor 08 μm and thermal annealing is applied at 1000° C., molybdenum silicide Ill105 is formed. At this time, the molybdenum silicide film is approximately 0.0 mm on one side in the lateral direction. It shrinks by lum, and its length is about 0.6μ.
It becomes m. Next, ion implantation of phosphorus at an acceleration voltage of 160 KeV and a dose of 3x10"cm-" results in polycrystalline silicon III 103 and molybdenum silicide It.
! Phosphorus is not implanted into the channel region of the silicon substrate under the gate electrode by 105, but phosphorus is shallowly implanted into the silicon substrate under the gate electrode by the polycrystalline silicon film 103 in the contracted portion of the molybdenum silicide film, and the junction The depth A of the phosphorus impurity concentration distribution is about 0.02 μm, the depth of the peak of the phosphorus impurity concentration distribution is about 0.05 μm, and the concentration is about I×10”am−”. In addition, phosphorus is deeply implanted into the silicon substrate in the source and drain regions where there is no gate electrode, and the junction depth B is approximately 0.
．． 4um, the depth of the peak of the phosphorus impurity concentration distribution is approximately 0
525 μm, and its concentration is approximately IXIO"cm-".
It should be noted that these impurity profile data are after annealing at 950°C for 20 minutes, which will be added later. As described above, the transistor operates in the embodiments up to FIG. 1(d), but the following process is continued to lower the sheet resistance of the source and drain regions. As shown in FIG. 1(e), a silicon oxide film with a thickness of 400 nm is deposited on the gate electrode and silicon substrate by CVD.
After forming 0A to sooo, reactive ion etching is performed to form sideol oxide 11@L O 7. Next, as shown in FIG. 1(f), an n-type impurity, here arsenic, is added at an accelerating voltage of 50 KeV to 150 KeV,
After ion implantation at Ix10" to lx10"am", thermal annealing is performed at 90°C to 1000°C to form an n-type impurity layer 10B with a high impurity concentration. Note that the n-type impurity layer 108 may be formed in the same manner without forming the sideol oxide 1l1107. In the MOS transistor formed by the above process, the gate electrode made of the polycrystalline silicon film 103 overlaps the low concentration n-type impurity layer 106, so when a voltage is applied to the gate, the low concentration The apparent resistance of the n-type impurity layer 106 is reduced, and the lateral electric field within the lightly doped n-type impurity layer 106 is relaxed. As a result, the drain current of the transistor increases and conductance deterioration due to hot carriers is avoided. Furthermore, according to this embodiment, the characteristics of the MOS transistor vary greatly depending on the overlapping length of the gate electrode formed by the polycrystalline silicon film on the low concentration n-type impurity layer 106; This can be easily and precisely controlled by changing the film thickness of the molybdenum film 104, the thickness of the molybdenum film 104, and the temperature of thermal annealing after forming the gate electrode.
Therefore, variations in the characteristics of MOS transistors are reduced. Further, in this embodiment, since there is no overhang, no cavity is formed and the moisture resistance of the transistor is not deteriorated. Furthermore, in this example, since the total film thickness on the channel is the sum of the film thickness of the gate oxide film 102, polycrystalline silicon film 103, and molybdenum silicide Ill 1 0 5, an additional wiring layer is added on the gate electrode. When forming a wiring layer on the gate electrode, even if the cotton distribution layer crosses the gate electrode, a wiring short due to etching residue will not occur when forming a wiring layer on the gate electrode because the level difference is small. Although molybdenum was used as the refractory metal film on the polycrystalline silicon film in this embodiment, similar effects can be expected by using tungsten, titanium, platinum, cobalt, nickel, or tantalum. Further, these high melting point metal silicide films may also be used. Further, in this example, phosphorus was used as the n-type impurity in the low concentration n-type impurity layer, but arsenic or antimony may also be used, or a combination of these impurities such as phosphorus and arsenic may be introduced. ．． Furthermore, in this embodiment, arsenic was used as the n-type impurity in the high-concentration n-type impurity layer, but phosphorus or antimony may also be used, or a combination of these impurities such as phosphorus and arsenic may be introduced. ．． Furthermore, although boron was used as an impurity in the P-type semiconductor substrate in this embodiment, gallium, aluminum, or indium may also be used. In this embodiment, an n-channel MOS type transistor has been described, but it goes without saying that similar effects can be obtained when applied to a p-channel MOS type transistor. [Effects of the Invention] According to the present invention, the drain current of a MOS transistor increases, and deterioration of conductance due to hot carriers can be avoided. Therefore, high-speed and highly reliable MO
We can provide S-type transistors. Furthermore, according to the present invention, the length of the par-lap of the source and drain regions and gate electrodes formed by the low concentration impurity layer, which influences the characteristics of the MOS transistor, can be processed with high precision and with little variation. Variations in current and conductance can be reduced. Furthermore, according to the present invention, the moisture resistance of the MOS transistor does not deteriorate. Further, according to the present invention, there are fewer disconnections and short circuits in the wiring layer on the gate electrode. From the above, the semiconductor device according to the present invention has the effect of providing a high-speed, high-quality, high-reliability, and high-yield semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）〜（ｆ）は本発明の半導体装置の製造方法
の一実施例を示す工程順断面図．第２図（ａ）〜（ｄ）
は従来例による半導体装置の断面図である． 第３図はＬＤＤ構造を有するトランジスタの断面図． １０１，２０１・・第１導電型のシリコン基板１０２、
２０２・・ゲート酸化膜 １０３，２０３、 ２０５・・・・・・多結晶シリコン膜 １０５・・・・・・高融点金属シリサイド膜１０６、２
０７、 ３０７・・・・・・シリコン基板と反対導電型の低濃度
不純物層 １０７、２０４、２０６、 ２０８、２１０・・シリコン酸化膜 １０８、２０９・・シリコン基板と反対導電型の高濃度
不純物層 以上FIGS. 1(a) to 1(f) are cross-sectional views in the order of steps showing an embodiment of the method for manufacturing a semiconductor device of the present invention. Figure 2 (a) to (d)
is a cross-sectional view of a conventional semiconductor device. Figure 3 is a cross-sectional view of a transistor with an LDD structure. 101, 201...first conductivity type silicon substrate 102,
202... Gate oxide film 103, 203, 205... Polycrystalline silicon film 105... High melting point metal silicide film 106, 2
07, 307...Low concentration impurity layer of the opposite conductivity type to the silicon substrate 107, 204, 206, 208, 210...Silicon oxide film 108, 209...High concentration impurity layer of the opposite conductivity type to the silicon substrate that's all

Claims (10)

【特許請求の範囲】[Claims] （１）第１導電型の半導体基板上に設けられた第１の絶
縁膜と、前記第１の絶縁膜上に設けられた第１の導電膜
による第１のゲート電極と、前記第１のゲート電極上に
設けられた第２の導電膜による第２のゲート電極と、前
記第２のゲート電極の両側の前記半導体基板に設けられ
た第２導電型の不純物を有する第１のソース領域および
ドレイン領域と、前記第１のゲート電極の両側の前記半
導体基板に設けられた第２導電型の不純物を有する第２
のソース領域およびドレイン領域からなる半導体装置に
おいて、前記第２のゲート電極長が前記第１のゲート電
極長より短く、前記第２のゲート電極の両側の前記半導
体基板に設けられた前記第１のソース領域およびドレイ
ン領域が、前記第１のゲート電極と、前記第１の絶縁膜
をはさんで対向して位置していることを特徴とする半導
体装置。(1) a first insulating film provided on a semiconductor substrate of a first conductivity type; a first gate electrode formed of a first conductive film provided on the first insulating film; a second gate electrode formed of a second conductive film provided on the gate electrode; a first source region having impurities of a second conductivity type provided in the semiconductor substrate on both sides of the second gate electrode; a drain region and a second conductivity type impurity provided in the semiconductor substrate on both sides of the first gate electrode;
In the semiconductor device comprising a source region and a drain region, the second gate electrode length is shorter than the first gate electrode length, and the first gate electrode provided on the semiconductor substrate on both sides of the second gate electrode. A semiconductor device characterized in that a source region and a drain region are located opposite to the first gate electrode with the first insulating film interposed therebetween. （２）第１導電型の半導体基板上に設けられた第１の絶
縁膜と、前記第１の絶縁膜上に設けられた第１の導電膜
による第１のゲート電極と、前記第１のゲート電極上に
設けられた第２の導電膜による第２のゲート電極と、前
記第１のゲート電極および前記第２のゲート電極の両側
に設けられた第２の絶縁膜によるサイドウォール絶縁膜
と、前記第２のゲート電極の両側の前記半導体基板に設
けられた第２導電型の不純物を有する第１のソース領域
およびドレイン領域と、前記サイドウォールの両側に設
けられた第２導電型の不純物を有する第２のソース領域
およびドレイン領域からなる半導体装置において、前記
第２のゲート電極長が前記第１のゲート電極長より短く
、前記第２のゲート電極の両側の前記半導体基板に設け
られた前記第１のソース領域およびドレイン領域が、前
記第１のゲート電極と、前記第１の絶縁膜をはさんで対
向して位置していることを特徴とする半導体装置。(2) a first insulating film provided on a semiconductor substrate of a first conductivity type; a first gate electrode formed of a first conductive film provided on the first insulating film; a second gate electrode formed by a second conductive film provided on the gate electrode; and a sidewall insulating film formed by a second insulating film provided on both sides of the first gate electrode and the second gate electrode. , first source and drain regions having second conductivity type impurities provided in the semiconductor substrate on both sides of the second gate electrode, and second conductivity type impurities provided on both sides of the sidewalls. In a semiconductor device comprising a second source region and a drain region, the second gate electrode length is shorter than the first gate electrode length, and the second gate electrode is provided on the semiconductor substrate on both sides of the second gate electrode. A semiconductor device, wherein the first source region and drain region are located opposite to the first gate electrode with the first insulating film interposed therebetween. （３）第２のゲート電極の両側の半導体基板に設けられ
た第１のソース領域およびドレイン領域の深さが第１の
ゲート電極の両側の前記半導体基板に設けられた前記第
１のソース領域およびドレイン領域の深さよりも浅いこ
とを特徴とする請求項１及び請求項２記載の半導体装置
。(3) the first source region provided in the semiconductor substrate on both sides of the first gate electrode; the depth of the first source region and drain region provided in the semiconductor substrate on both sides of the second gate electrode; 3. The semiconductor device according to claim 1, wherein the depth is shallower than the depth of the drain region. （４）第２のソース領域およびドレイン領域の深さが、
第１のゲート電極の両側の前記半導体基板に設けられた
第１のソース領域およびドレイン領域の深さよりも浅い
ことを特徴とする請求項１及び請求項２及び請求項３記
載の半導体装置。(4) The depth of the second source region and drain region is
4. The semiconductor device according to claim 1, wherein the depth is shallower than the depth of the first source region and drain region provided in the semiconductor substrate on both sides of the first gate electrode. （５）第１の導電膜が多結晶シリコン膜であり、第２の
導電膜が高融点金属膜あるいは高融点金属シリサイド膜
であることを特徴とする請求項１、請求項２及び請求項
３及び請求項４記載の半導体装置。(5) Claims 1, 2, and 3, wherein the first conductive film is a polycrystalline silicon film, and the second conductive film is a high melting point metal film or a high melting point metal silicide film. and a semiconductor device according to claim 4. （６）第１導電型の半導体基板に第１の絶縁膜を形成す
る工程と、前記第１の絶縁膜上に第１の導電膜を、前記
第１の導電膜上に第２の導電膜を順次形成する工程と、
前記第１の導電膜および前記第２の導電膜によりＭＯＳ
型トランジスタのゲート電極を形成する工程と、熱アニ
ールを加える工程と、前記ゲート電極をマスクに前記半
導体基板に第２導電型の第１の不純物をイオン注入する
工程と、前記ゲート電極をマスクに前記半導体基板に第
２導電型の第２の不純物をイオン注入する工程からなる
ことを特徴とする半導体装置の製造方法。(6) forming a first insulating film on a semiconductor substrate of a first conductivity type; a first conductive film on the first insulating film; and a second conductive film on the first conductive film. a step of sequentially forming
The first conductive film and the second conductive film form a MOS
a step of forming a gate electrode of a type transistor, a step of applying thermal annealing, a step of ion-implanting a first impurity of a second conductivity type into the semiconductor substrate using the gate electrode as a mask, and a step of ion-implanting a first impurity of a second conductivity type into the semiconductor substrate using the gate electrode as a mask. A method for manufacturing a semiconductor device, comprising the step of ion-implanting a second impurity of a second conductivity type into the semiconductor substrate. （７）第１導電型の半導体基板に第１の絶縁膜を形成す
る工程と、前記第１の絶縁膜上に第１の導電膜を、前記
第１の導電膜上に第２の導電膜を順次形成する工程と、
前記第１の導電膜および前記第２の導電膜によりＭＯＳ
型トランジスタのゲート電極を形成する工程と、熱アニ
ールを加える工程と、前記ゲート電極をマスクに前記半
導体基板に第２導電型の第１の不純物をイオン注入する
工程と、前記半導体基板および前記ゲート電極に第２の
絶縁膜を形成した後、異方性イオンエッチングを行ない
前記ゲート電極に第２の絶縁膜によるサイドウォール絶
縁膜を形成する工程と、前記ゲート電極と前記サイドウ
ォール絶縁膜をマスクに第２導電型の第２の不純物を導
入する工程からなることを特徴とする半導体装置の製造
方法。(7) forming a first insulating film on a semiconductor substrate of a first conductivity type; forming a first conductive film on the first insulating film; and forming a second conductive film on the first conductive film; a step of sequentially forming
The first conductive film and the second conductive film form a MOS
a step of forming a gate electrode of a type transistor, a step of applying thermal annealing, a step of ion-implanting a first impurity of a second conductivity type into the semiconductor substrate using the gate electrode as a mask, and a step of ion-implanting a first impurity of a second conductivity type into the semiconductor substrate and the gate After forming a second insulating film on the electrode, performing anisotropic ion etching to form a sidewall insulating film of the second insulating film on the gate electrode, and masking the gate electrode and the sidewall insulating film. 1. A method for manufacturing a semiconductor device, comprising the step of introducing a second impurity of a second conductivity type into the semiconductor device. （８）第２導電型の第１の不純物をイオン注入する際、
注入したイオンが、第１の導電膜厚と第２の導電膜厚の
和の膜厚は透過せず、第１の導電膜厚は透過するような
イオン種、イオン注入加速電圧であることを特徴とする
請求項６及び請求項７記載の半導体装置の製造方法。(8) When ion-implanting the first impurity of the second conductivity type,
The ion species and ion implantation acceleration voltage are such that the implanted ions do not pass through the sum of the first conductive film thickness and the second conductive film thickness, but pass through the first conductive film thickness. A method for manufacturing a semiconductor device according to claim 6 or claim 7. （９）イオン注入した第２導電型の第２の不純物領域の
深さが、第２導電型の第１の不純物領域の深さよりも浅
いことを特徴とする請求項６及び請求項７及び請求項８
記載の半導体装置の製造方法。(9) The depth of the ion-implanted second impurity region of the second conductivity type is shallower than the depth of the first impurity region of the second conductivity type. Section 8
A method of manufacturing the semiconductor device described above. （１０）第１の導電膜が多結晶シリコン膜であり、第２
の導電膜が高融点金属膜あるいは高融点金属シリサイド
膜であることを特徴とする請求項６及び請求項７及び請
求項８及び請求項９記載の半導体装置の製造方法。(10) The first conductive film is a polycrystalline silicon film, and the second conductive film is a polycrystalline silicon film.
10. The method of manufacturing a semiconductor device according to claim 6, 7, 8, or 9, wherein the conductive film is a high melting point metal film or a high melting point metal silicide film.
JP2038757A 1989-03-28 1990-02-20 Method for manufacturing semiconductor device Expired - Lifetime JP2926833B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019900004032A KR0179656B1 (en) 1989-03-28 1990-03-26 Semiconductor device and method of manufacturing the same
US07/500,200 US5097300A (en) 1989-03-28 1990-03-27 Semiconductor device and manufacturing method thereof
EP90303269A EP0390509B1 (en) 1989-03-28 1990-03-28 Semi-conductor device and method of manufacturing the same
DE69032446T DE69032446T2 (en) 1989-03-28 1990-03-28 Semiconductor component and method for its production
US07/733,643 US5147814A (en) 1989-03-28 1991-07-22 Method of manufacturing an lddfet having an inverted-t shaped gate electrode
HK98109971A HK1009308A1 (en) 1989-03-28 1998-08-18 Semi-conductor device and method of manufacturing the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP7610889 1989-03-28
JP7610989 1989-03-28
JP1-76108 1989-03-28
JP1-76109 1989-03-28

Publications (2)

Publication Number Publication Date
JPH0316139A true JPH0316139A (en) 1991-01-24
JP2926833B2 JP2926833B2 (en) 1999-07-28

Family

ID=26417257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2038757A Expired - Lifetime JP2926833B2 (en) 1989-03-28 1990-02-20 Method for manufacturing semiconductor device

Country Status (2)

Country Link
JP (1) JP2926833B2 (en)
KR (1) KR0179656B1 (en)

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KR900015343A (en) 1990-10-26
KR0179656B1 (en) 1999-03-20
JP2926833B2 (en) 1999-07-28

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