JPH03154456A - Pulse detection circuit - Google Patents

Abstract

PURPOSE:To surely detect production of a pulse to be detected by avoiding duplicate of generating timing when a generating timing of a pulse to be detected and a generating timing of a detection timing pulse are in duplicate and detecting each timing. CONSTITUTION:The time axis of the system is corrected so that a bit error pulse BEP is synchronized for a period of a clock signal CK being at a logical L and an alarm collection pulse ACP is synchronized for a period of the clock signal CK being at a logical H. Thus, the logical H period of a bit error pulse CBEP after the correction and that of an alarm collection pulse CACP are not overlapped. Thus, the bit error pulse BEP is surely converted into a bit error alarm BEA and outputted.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a pulse detection circuit that detects the occurrence of a pulse to be detected based on the timing of a detection timing pulse. This can be applied to a bit error detection circuit.

[Prior Art] Conventionally, pulse detection circuits that detect the occurrence of a certain pulse at the timing of another pulse have been used in various circuits and devices. For example, it is used in failure and error monitoring devices. In such a monitoring device, there are often multiple objects to be monitored. Therefore, if a pulse indicating the occurrence of a failure or error is sent from a monitoring target where a failure or error has occurred to the monitoring device itself, regardless of the processing status of the monitoring device itself, the detected pulse may not be received. This often causes inconveniences such as disrupting the processing that the monitoring device itself is currently doing. For this reason, many monitoring devices use a method that retains the generation of pulses that indicate failures or errors, and then sends pulses that indicate failures or errors to the monitoring device itself when collection pulses are given from the monitoring device itself. has been done.

FIG. 2 shows a transmission signal bit error detection circuit that employs such a monitoring method. In FIG. 2, this bit error detection circuit is composed of a transmission signal processing circuit 1 and a pulse detection circuit 2.

The transmission signal processing circuit 1 processes the received transmission signal as appropriate, and also detects bit errors in the transmission signal based on parity pits, for example. When a bit error is detected, a bit error pulse BEP is sent to the pulse detection circuit 2. Output to.

The pulse detection circuit 2 consists of an RSS flipflop 1 circuit 3 and a D flipflop 9 circuit 4. The bit error pulse BEP is applied to the set terminal of the RSS flip-flop circuit 1 circuit 3 to set the flip-flop circuit 3. The Q output terminal of the RSS flipflop 1 circuit 3 is connected to the data input terminal of the D flipflop 9 circuit 4. The clock input terminal of this D flip-flop circuit 4 receives an alarm collection pulse A from the monitoring device main body (not shown).
CP is given. D flip flop 7 times 128
The Q output terminal 4 is a terminal for outputting a bit error alarm.

Note that the alarm collection pulse ACP is also applied to the reset input terminal of the RSS flip flow 1 circuit 3, and the set operation can be performed again by the hit error pulse BEP that occurs before the next alarm collection pulse ACP is generated. It is made possible to do so.

FIG. 3 is a timing chart showing the operation of this pulse detection circuit 2. Bit error pulse BEP at time t1
When this occurs, the Q output Q3 of the RS flip-flop 1 circuit 3 becomes logic H at the time t1. After that, at time t2, the alarm collection pulse ACP becomes logic H to instruct collection. At this time t2, the Q output signal Q3 of the RSS flip-flop 1 circuit 3 is logic H, so the D flip-flop 9 circuit 4 The bit error alarm BEA, which is a Q output signal, also becomes logic H and outputs the occurrence of a bit error. Also, at this point t2, flip-flop 91 times FI!
43 is reset and becomes ready to accept the next bit error pulse BEP.

Thereafter, before the bit error pulse BEP occurs, at time t3, the alarm collection pulse ACP becomes logic H again to indicate collection, and the bit error alarm BEA also becomes logic logic and returns to the monitoring standby state.

In this way, the generation of the bit error pulse BEP causes the period t2 to t between the preceding and succeeding alarm collection pulses ACP to
A bit error alarm BEA expanded to 3 is output.

[Problems to be Solved by the Invention] However, as described above, the bit error pulse BEP and the alarm collection pulse ACP are generated asynchronously and independently. Therefore, as shown in Figure 4,
It also happens that the period of occurrence of the bit error pulse BEP overlaps with the logic H period of the alarm collection pulse ACP. In this case, the operating state of the RSS flip flow 1 circuit 3 is not uniquely determined, so it operates unstablely, and as shown in FIG. There were times when the logic H was not achieved. In other words, it has sometimes been impossible to accurately report the occurrence of a bit error.

This problem is not a problem that occurs when a pulse detection circuit is applied to a hit error detection circuit, but a problem that occurs in the pulse detection circuit itself.

The present invention has been made in consideration of the above points, and it is an object of the present invention to provide a pulse detection circuit that can reliably detect the occurrence of a pulse to be detected, regardless of the timing of occurrence of the detection timing pulse. 9 [Means for Solving the Problem] In order to solve the problem, in the present invention, the generation of the detected pulse is held in a holding circuit, and the held detected pulse is output at the timing of the detection timing pulse. At the same time, the following circuit was installed in the pulse detection circuit that clears the held state of the holding circuit.

That is, in order to eliminate the overlap between the period of the detected pulse and the detected timing pulse, a pulse duplication removal circuit that corrects at least one of the detected pulse or the detected timing pulse is provided upstream of the holding circuit.

[Function] A pulse detection circuit that holds the generation of the detected pulse in a holding circuit, outputs the held detected pulse at the timing of the detection timing pulse, and clears the held state of the holding circuit. The problem is that the periods of the detection pulse and the detection timing pulse overlap.

If so, the overlapping period should be eliminated at the stage of applying these pulses to the components after the holding circuit.

Therefore, a pulse duplication removal circuit is provided before the holding circuit.
At least one of the detected pulse and the detected timing pulse is modified so as to eliminate the overlap between the period of the detected pulse and the detected timing pulse.

[Embodiment] First, a first embodiment of the present invention will be described with reference to the drawings. Note that this first embodiment will be described as being applied to a pulse detection circuit in a bit error detection circuit.

Here, FIG. 1 is a block diagram showing this first embodiment, and FIG. 5 is a timing chart of each part of the first embodiment.

In this first embodiment, regardless of the overlap between the generation period of the bit error pulse BEP and the logic H period of the alarm collection pulse ACP, the corrected bit corrects the position of these periods on the time axis to avoid the overlap of the periods. A pulse time base correction circuit 10 is provided which forms an error pulse CBEP and a corrected alarm acquisition pulse CACP.

The pulse time axis correction circuit 10 includes a D flip 70 tube circuit 11, a NOR circuit 12, a D flip Flora 1 circuit 13, an inverter circuit 14, and an AND circuit 15.

A bit error pulse BEP is directly applied to the data input terminal of the D flip-flop circuit 11. A clock signal CK output from a clock generation circuit (not shown) is applied to a clock input terminal of the D flip-flop circuit 11. An inverted output signal for the Q output signal from the D flip-flop circuit 11 (hereinafter referred to as the QN output signal>QNII
is applied to the NOR circuit 12. This NOR circuit 12 is also supplied with the above-mentioned tally clock signal CK. This Noah circuit 1
The output signal from 2 is output as the bit error pulse CBEP whose time axis has been corrected. Note that the corrected bit error pulse CBEP is the clock signal CK
The logic level is set to H within the logic period of , and this will be explained in detail in the explanation of the operation.

Note that the clock signal CK is generated asynchronously with the bit error pulse BEP and the alarm collection pulse ACP, which will be described later, and at a predetermined period.

The alarm collection pulse ACP is directly applied to the data input terminal of the other D-flip Flora 1 circuit 13. The above-mentioned clock signal CK is inverted via the inverter circuit 1.4 and applied to the clock input terminal of the D flip processor 1 circuit 13. Q output signal Q13 from D flip-flop circuit 11 is applied to AND circuit 15. This AND circuit 15 is also supplied with the above-mentioned tally clock signal CK, and the output signal from this AND circuit 15 is outputted as the above-mentioned alarm collection pulse CACP whose time axis has been corrected. In addition, the modified alarm collection pulse C
ACP takes the logic H level within the logic H period of the clock signal CK, and this will be explained in detail in the explanation of the operation.

Based on the bit error pulse CBEP and alarm collection pulse CACP with such logic H period modified,
The configuration for detecting the bit error pulse BEP and generating an alarm is the same as the conventional one.

That is, the flip-flop circuit 20 includes an RS flip-flop circuit 20 and a D flip-flop circuit 21.
Corrected bit error pulse CB to the set input terminal of
EP and input the modified alarm collection pulse CACP to the reset input terminal of the flip-flop circuit 24 and the clock input terminal of the flip-flop circuit 21;
The Q output signal Q20 of the flip-flop circuit 20 is input to the data input terminal of the flip-flop circuit 21, and the bit error alarm BEA is output from the Q output terminal of the flip-flop circuit 21.

In this first embodiment, it is preferable that at least the alarm collection pulse ACP has a pulse width of about one clock cycle.

Next, the operation of the first embodiment having the above configuration will be explained using FIG.

In FIG. 5, the alarm collection pulse ACP shown in FIG. 5(B) becomes logic H at time t10, and the immediately following time t
At 11, the bit error pulse BEP shown in FIG. Assume that the bit error pulse BEP changes logically at time t14, which is slightly delayed from time t13, and that the alarm collection pulse ACP also changes logically at the subsequent time t15.

A clock signal CK is input to the clock input terminal of the D flip-flop circuit 11 to which the bit error pulse BEP is applied.
Since the clock signal CK is directly applied, the rise of the clock signal CK becomes a problem. During the logic H period of the bit error pulse BEP, the tarock signal CK rises at time t13.
Time t when one clock period has elapsed since this time t13
At 17, the bit error pulse BEP has already fallen to the logical level. Therefore, the QN output signal QNII of the D flip-flop circuit 11 logically falls only during the period from time t13 to time t17, as shown in FIG.

As a result, this QN output signal QNII and clock signal C
From the NOR circuit 12 to which K is given, as shown in FIG. Pulse CBEP is output.

On the other hand, since the clock signal CK is inverted and supplied to the clock input terminal of the D flip-flop circuit 13 to which the alarm collection pulse ACP is supplied, the fall of the clock signal CK poses a problem. Alarm collection pulse A
During the logic H period of CP, the clock signal C at time t12
At time t16 when K falls and one clock cycle has passed from time t12, the alarm collection pulse ACP has already logically fallen. Therefore, the Q output signal Q13 of the D flip-flop circuit 13 rises to logic H only during the period from time t12 to time t16, as shown in FIG. 5(F).

As a result, the AND circuit 15 to which the Q output signal Q13 and the clock signal CK are applied rises to logic H for a period of 1/2 clock cycle from time t15 to t16, as shown in FIG. 5(G). An alarm collection pulse CAcp whose time axis has been corrected is output.

Therefore, FIG. 5 (H
Q output signal Q of the RSS flip flow 1 circuit 20 shown in )
20 rises at time tl&. However, Fig. 5 (I)
The bit error alarm BEA shown in FIG. 1 remains logical during the period before and after this period.

Eventually, the alarm collection pulse ACP reaches time t in FIG.
Even in the case where the acquisition is instructed again by taking the logic H level during the period from t20 to t21, it operates in the same way as described above, and is synchronized with the clock signal CK, and the data is output from 1/1 of the period from t20 to t22.
The AND circuit 15 outputs an alarm collection pulse CACP whose time axis has been corrected by rising to the logic F (for a period of two clock cycles. Thus, at time t20, R
SS Fritsubflo 9th F! ! 20 is reset and the bit error alarm BEA goes into alarm state.

Therefore, in this first embodiment, the bit error pulse BE
Since the time axis was modified to synchronize P with the logic period of the clock signal CK and synchronize the alarm collection pulse ACP with the logic H period of the clock signal CK, the corrected bit error pulse CBEP and alarm collection pulse CA
The logic H period no longer overlaps with CP, and the bit error pulse BEP is reliably set to the bit error alarm BE.
It can be converted to A and output.

[Grave Lambda] Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 shows the configuration of this second embodiment, and FIG. 7 is a timing chart of each part of the second embodiment.

In FIG. 6, this second embodiment includes an AND circuit 30,
It consists of an inverter circuit 31, a JK flip-flop circuit 32, and a D flip-flop circuit 33.

The bit error pulse BEP is applied to the J input terminal of the JK flip-flop circuit 32, and the alarm collection pulse AC
P is modified by the AND circuit 30 for a period corresponding to a predetermined condition and is applied to the input terminal of the JK flip-flop circuit 32. This JK flip-flop circuit 32 outputs a Q signal when the bit error pulse BEP is at a logic H level at the rising edge of the clock signal CK which arrives during a period when the modified alarm collection pulse CACP is at a logic logic level.
The output signal Q32 is set to logic H.

In the AND circuit 30, the bit error pulse BEP is inverted via the inverter circuit 31, so the condition for the AND circuit 30 to pass the logic H state of the alarm collection pulse ACP is that the bit error pulse BEP is logic. That's true. In other words, when the bit error pulse BEP and the alarm collection pulse ACP are both logic H, the AND circuit 30 forcibly converts the logic H of the alarm collection pulse ACP to logic logic only during the overlapping period. and is applied to the JK flip-flop circuit 32.

The Q output signal Q32 of the JK flip-flop circuit 32 is
It is applied to the data input terminal of the D flip-flop circuit 33. An alarm collection pulse ACP is applied to the clock input terminal of the JK flip-flop circuit 32. The Q output signal Q33 of this flip-flora 1 circuit 33 is sent out as a bit error alarm BEA.

Next, the operation of the second embodiment having the above configuration will be explained using FIG.

In FIG. 7, at time t30, the alarm collection pulse AC
P becomes logic H, the bit error pulse BEP becomes logic H at time t31 immediately after that, clock signal CK rises to logic H at time t32, and at this time t3
Bit error pulse B occurs at time t33, which is slightly later than 2.
Assume that EP changes logically, and furthermore, at a subsequent time point t34, the alarm collection pulse ACP also changes logically.

In this way, even if the bit error pulse BEP and the alarm collection pulse ACP partially overlap from 31 to t33, the bit error pulse BEP is not subjected to any processing and is passed to the J input of the JK flip-flop circuit 32. given to the terminal.

On the other hand, the alarm collection pulse ACP is gated by the AND circuit 30 so that the partially overlapping period is forced to be logical. That is, the bit error pulse BEP is applied to the AND circuit 30 via the inverter circuit 31, and the period t
31 to t33, the alarm collection pulse AeP is prevented from passing through the logic H state when the bit error pulse BEP is logic H. The alarm collection pulse CACP whose overlapping period has been forcibly converted into a logic logic in this manner is applied to the input terminal of the JK flip-flop circuit 32.

That is, at this collection timing, time t30 to t31
Alarm collection pulses A and CP are applied to the input terminals, which take a logic H level only during the period t33 and time t34.

Thus, when the clock signal CK rises at time t32, the Q output signal of the JK flip-flop 1 circuit 32 rises to logic H. However, since the original alarm collection pulse ACP rises at time t30, even if the Q output of the JK flip-flop circuit 32 rises, in the period before and after this, the D flip-flop circuit li'8
The bit error alarm BEA, which is the Q output signal of No. 33, does not become logic H.

After this, if the bit error pulse BEP and alarm collection pulse ACP continue to be logical, the clock signal CK
rises, the JK flip-flop circuit 32 does not change the logic level of the Q output, and the D flip-flop circuit 3
Do not change the Q output status of 3.

Eventually, at time t35, the alarm collection pulse ACP rises to logic H again, and at this time t35, the bit error alarm BEA rises to logic H, reporting the occurrence of a bit error. The logic H state of the alarm collection pulse ACP from this time t35 passes through the AND circuit 30 as it is and is applied to the JK flip-flop circuit 32, and then at the first rise time t36 of the clock signal CK, the JK
The Q output signal of flip-flop circuit 32 becomes a logic high.

That is, it is restored to a state where it can become logic H with the next generated bit error pulse BEP.

Therefore, in this second embodiment, the bit error pulse BE
When both P and alarm collection pulse ACP are logic H, the logic level of alarm collection pulse ACP is forcibly set to logic low only during the overlapping period, so after the modification, bit error pulse BEP The logic H periods of the signal and the alarm collection pulse CACP do not overlap, and the bit error pulse BEP can be reliably converted into the bit error alarm BEA and output.

The present invention can be applied not only to bit error detection circuits but also to various circuits and devices that require a configuration for detecting the generation of a pulse to be detected at the timing of generation of a timing pulse.

Further, in the above-described embodiment, an active high configuration is shown, but an active low configuration is of course possible.

[Effects of the Invention] As described above, according to the present invention, when the generation timing of the detected pulse and the generation timing of the detection timing pulse overlap, the detection is performed after avoiding the overlap of these generation timings. Since it is made to operate, it is possible to reliably detect the occurrence of the pulse to be detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of a pulse detection circuit according to the present invention, FIG. 2 is a block diagram showing a bit error detection circuit to which a conventional pulse detection circuit is applied, and FIG. 3 shows each part of FIG. 2. Timing chart, Fig. 4 is a timing chart of each part of Fig. 2 to explain the conventional drawbacks, Fig. 5
The figure is a timing chart of each part of the first embodiment, FIG. 6 is a block diagram of a second embodiment of the present invention, and FIG. 7 is a timing chart of each part of the second embodiment. 11.13.21.33...D flip-flop circuit, 12...NOR circuit, 14.31...Inverter circuit, 15.30...AND circuit, 20...RS flip-flop circuit, 32 ...JK flip-flop circuit. 108" λ time axis correction circuit l --- J Figure 1: Block diagram of the first embodiment. Figure 1: 7" of the conventional circuit. Timing of each part of the first embodiment: 9" fr) Figure 5: EP 1 t! 3 Fig. 2: Timing chart of the circuit Fig. 3: Timing chart for explaining the drawbacks of the conventional circuit Fig. 4: Fig. 6: 0 ss Timing chart of each part of the second embodiment! -Figure 7

Claims (3)

[Claims] (1) In a pulse detection circuit that holds the generation of the detected pulse in a holding circuit, outputs the held detected pulse at the timing of the detection timing pulse, and clears the holding state of the holding circuit, A pulse detection circuit characterized in that a pulse duplication removal circuit for correcting at least one of the detected pulse or the detection timing pulse is provided at a stage upstream of the holding circuit so as to eliminate the overlap between the period and the period of the detection timing pulse. (2) The pulse duplication removal circuit includes a detected pulse modification unit that passes the detected pulse only when the clock signal takes one logic level, and a detection timing that passes the detected pulse only when the clock signal takes the other logic level. 2. The pulse detection circuit according to claim 1, further comprising a detection timing pulse correction section for passing a pulse. (3) The pulse according to claim 1, wherein the pulse duplication removal circuit eliminates period overlap by forcibly reversing the logic level of the overlap period in the detection timing pulse. detection circuit.