JPH03149851A - Creation of mask pattern for integrated circuit - Google Patents

Abstract

PURPOSE:To achieve automatic conversion from a schematic drawing to a mask pattern layout and to enable an accurate mask pattern as in the schematic drawing to be created by providing each specific data input process, coordinates conversion process, and layout process. CONSTITUTION:In a method for creating a mask pattern for an integrated circuit by placing a cell corresponding to each element and wire based on a schematic diagram consisting of a plurality of elements and a wire between the elements, a data input process 14 for entering a data 10 for each element and each wire of the above schematic drawing and a cell data 12 corresponding to their elements, a coordinates conversion process 18 for converting the terminal coordinates of each element and the positional coordinates of wire based on the size of the corresponding cell, and a placement process 22 for placing each corresponding cell based on the coordinates which are converted by the coordinates conversion process 18 are provided for retaining the positional relationship between each element and each wire in the schematic drawing. For example, the circuit data 10 is input from a CAE device to a CAD device.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a method for creating a mask pattern for an integrated circuit, particularly a method for creating a mask pattern for an integrated circuit.
The present invention relates to a method of automatically creating a mask pattern using an AD device. [Background Art] With the dramatic progress in semiconductor technology in recent years, the scale of circuits has increased, and the circuit design has come to be performed using computers. Such a circuit design is
Normal CA D
sigm) device. Based on the circuit designed in this way,
The elements and wiring in I etc. are determined and a mask is created according to this pattern. That is, in the manufacturing process of LSI and the like, it is necessary to create a mask corresponding to a pattern desired to be manufactured in various processing processes such as photo etching. Normally, to create such a mask, based on circuit diagram data designed by a circuit designer, cells corresponding to each element in the circuit diagram, such as a transistor or a resistor, are read out from a cell library, and the read cells are inserted into the circuit. A mask pattern is created by arranging it at a predetermined position so as to match the logical connection of the diagram data.

Problem to be Solved by the Invention-1 However, when creating a mask pattern for SI manufacturing using a CAD device, conventionally, the operator of the CAD device has to create a mask pattern based on the circuit diagram data created by the circuit designer. , the cells corresponding to each element are manually arranged, which poses a problem in that it takes time to create a mask pattern and also leads to placement errors. For example, when creating a mask pattern for a bipolar analog LSI using bipolar transistors, the bipolar transistors and resistors that make up the amplifier circuit and filter circuit in the LSI, as well as the wiring that electrically connects these elements, are created. The circuit diagram data composed of
First of all, CAE (Computer Todoro1ded Engln)
erlnlE). Then, based on this input circuit diagram data, the operator of the CAD device reads cells corresponding to the elements of the circuit diagram from a cell library in which cells corresponding to each element such as a transistor or a resistor are stored in advance. and place them at appropriate positions while taking into consideration the design rules between each cell. Additionally, it should match the logical connections in the schematic data (
Wiring cells must be placed to connect each cell. As described above, the conventional mask pattern creation process involves a lot of manual intervention, requires a great deal of labor, and is extremely difficult to accurately realize the layout as shown in the circuit diagram. The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to create a mask pattern for an integrated circuit that can automatically convert a circuit diagram into a mask pattern layout and create a mask pattern accurate to the circuit diagram. The purpose is to provide a method. [Means for Solving the Problems] In order to achieve the above object, the method for creating a mask turn for an integrated circuit of the present invention is provided by inputting data of each element and wiring of a circuit diagram and data of cells corresponding to these elements. a data input process that converts the terminal coordinates and wiring position coordinates of each element in the circuit diagram based on the size of the corresponding cell; The present invention is characterized by comprising a placement process for arranging cells. [Sakugawa 1] The method for creating a mask pattern for an integrated circuit according to the present invention has such a process, and after inputting circuit diagram data and cell data designed by a circuit designer, elements are created based on the cell data. and changes the wiring data. That is, the distance between the terminal coordinates of each element and the positional coordinates of each wiring is defined according to the cell size of the cell corresponding to each element, and the distance between the coordinates is enlarged and transformed to satisfy this distance between the coordinates. Since the coordinates enlarged and transformed according to the cell size give the area of the cell to be placed, the corresponding cell line and one line are easily placed at the corresponding position, and the layout pattern as shown in the circuit diagram is created. Realize. 1 Embodiment A preferred embodiment of the integrated circuit mask pattern creation method according to the present invention will be described below with reference to the drawings. Figure m1 is a flowchart of this embodiment. A circuit diagram of a bipolar analog LSI circuit designed by a circuit designer is stored as circuit diagram data 10 in a CAD device. The circuit diagram data 10 is stored as symbols corresponding to each element constituting the circuit diagram and connection data between the symbols. On the other hand, cell data 12 read from a cell library in which cells corresponding to each element constituting the circuit, such as bipolar transistors and resistors, are stored in advance is input to a CAD device that creates a mask pattern corresponding to the circuit diagram. . For example, when the device is a bipolar transistor shown in FIG. 2(A), the data format of the cell stored in the cell library 12 is a rectangular shape having a predetermined width and length as shown in FIG. 2(B). Cells can be assigned. And the base terminal B of the bipolar transistor. The distance in the y direction between the collector terminals C is b (for example, 9 μm),
The distance in the y direction between the emitter terminal 81 and the base terminal B is given as C (for example, 11 μm), and the distance in the X direction as a bipolar transistor element is given as a (for example, 16 μm), and the area occupied by the bipolar transistor element is defined in the mask pattern. can do. In addition, if the circuit elements are resistors having resistance values of 5Ω and IOKΩ as shown in FIG. 3(A),
), allocate a rectangular cell with a predetermined width as in the case of a bipolar transistor, set the distance in the y direction as d and f (for example, d = 20 μm, f - 35 am), and determine the resistance value. At the same time, the area occupied by the resistive element can be defined by the mask pattern. Now, after inputting the circuit diagram data 10 and the cell data 12 from the cell library in process 14 of FIG. 1, in process 16 terminal coordinates and wiring position coordinates indicating the position of each element in the circuit diagram are input. Arrange the values in descending order and register them in the graph. For example, a circuit diagram for which a mask pattern is to be created includes three bipolar transistors Q1. Q2. Q3 and five resistors R
1 (Ω to 5), R2 (IOKΩ), R3 (Ω to 5)
, R4(IOKΩ), and R5(IOKΩ). A predetermined position if (point P at the lower left in the figure) is set at the origin (0,0) of mutually orthogonal X%y coordinates, and the coordinates of each element and wiring are determined. For example, the transistor Q1 has the base terminal B (9,40), the collector terminal C (14,45), and the emitter terminal E (14,35), and the terminal coordinates of the resistor R3 are (14,12).
, (14,22). Then, when the terminal coordinates of each of these elements and the position coordinates of each wiring are arranged in order of decreasing value, X coordinate: Q, 9.14.29.34 - Y coordinate = 0.8.9. 12.18 -... In process 16, the terminal coordinates of each element in the circuit diagram and the position coordinates of each wiring are arranged in order of decreasing value and registered in the graph, and then the process moves to process 18, in which the cell corresponding to each element is read from the cell library. The cells are extracted from among the cells, and the coordinates registered are converted by arranging them in order of decreasing value in the process 16 described above based on the extracted cell size. For example, in the circuit diagram shown in Figure 4, there is a wire named N1 at the position where the y-coordinate is 40, but when the data width of the wiring data is 4 μm, the y-coordinate is 40, taking into account the design rule of 2 μm between the wires. 4/2+2/2-3 μm are required above and below the wiring N1. Therefore, for the wiring N1 located at the y-coordinate 40, a distance of 3 μm above and below the y-coordinate 40 is given. Furthermore, for the bipolar transistor Q1, yMflll of its base terminal B is 4
0, the y-coordinate of the collector terminal C is 45, but in Fig. 2 (
As shown in B), the cell size of the cell corresponding to the bipolar transistor is that the distance between the base terminal B1 and the collector terminal C is b (9 μm), so the y coordinates are 40 and 45.
9 μm is given between. Then, the distance between the coordinates registered in the graph is defined by the cell size in this way, and each coordinate is transformed so as to satisfy the mutual distance. For example, the X coordinates of 0 and 9 are not defined by the cell size, and the distance between them is 0 μm, so they are converted to the same coordinate. Also, X
At coordinates 34 and 46, bipolar transistor Q2,
Q3 (area-3) and resistors R4 and R5 exist, but the cell size corresponding to bipolar transistors Q2 and Q3 is 16 μm x 20 μm and 130 μm x 2, respectively.
0 μm, and the cell size corresponding to the resistors R4 and R5 is 8 μm x 20.8 x 35 μm, so the mutual distance is defined by the transistor cells with large cell sizes,
The coordinates are transformed so that the distance becomes 16/2+30/2-23 μm. FIG. 5 shows how the coordinates are transformed so as to satisfy the mutual distance. As described above, the X coordinates of 0 and 9 are not defined by the cell size, and the distance between them is 0 μm, so they are converted to the same coordinate. After converting the coordinates and enlarging the graph so as to satisfy the mutual distance defined by the cell size in this way, the process moves to process 22 to arrange wiring and cells. i
Figure i6 first shows a layout pattern when wiring is arranged, and Figure w1 shows a layout pattern when cells corresponding to each element are arranged. At this time, for example, if resistors with the same terminal coordinates are arranged in parallel in a circuit diagram, the distance between the coordinates is determined by the cell size of the resistor with a large resistance value, so the cell size of the resistor with a small resistance value However, in this case, it is sufficient to determine in advance that the cell will be placed in the center of the area. After wiring and element cells are arranged in process 22,
Wiring is drawn to the terminal area of each element cell placed in process 24. The layout pattern in which wiring is drawn is shown in the m8 diagram. This layout pattern in FIG. 8 is a pattern in which the positional relationship of elements and wiring in the circuit diagram in FIG. 184 is maintained, and processes 14 to 2
Each of the processes in step 4 can be performed automatically by a computer because it only involves arranging numerical data and converting coordinates. The calculation result data thus obtained is output as a file (process 26) and stored in the CAp device (process 28) to create a mask pattern for LSI manufacturing. As described above, the integrated circuit mask pattern creation method of the present invention appropriately enlarges and converts the coordinates of each element and each wiring from circuit diagram data according to the cell size of the corresponding cell,
Corresponding cells are placed in predetermined positions based on the new coordinates expanded in this way, and a mask pattern can be automatically created while maintaining the positional relationship of each element shown in the circuit diagram. It is. Effects of the Invention 1 As explained above, according to the method for creating a mask pattern for an integrated circuit according to the present invention, a corresponding mask pattern can be automatically created while maintaining the inter-element positions in the circuit diagram. The manufacturing time can be significantly shortened, and element placement errors and wiring errors can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a flowchart of an embodiment of the integrated circuit mask pattern creation method according to the present invention, FIG. 2 is an explanatory diagram of a cell corresponding to a bipolar transistor in the embodiment, and tB3 is an explanatory diagram of a cell corresponding to a bipolar transistor in the embodiment. An explanatory diagram of the corresponding cell, FIG. 4 is a circuit diagram in the same embodiment, FIG. 5 is a conversion explanatory diagram showing the state of coordinate transformation of each element and each y-line in the same embodiment, and FIGS. 6 to 8 is an explanatory diagram of the arrangement in the same embodiment. 10...-Circuit diagram data 12...Cell data 14...-Data input process 16...Coordinate transformation process 22...Placement process

Claims (1)

[Claims] A method for creating a mask pattern for an integrated circuit, in which a mask pattern for an integrated circuit is created by arranging cells corresponding to each element and wiring at predetermined positions based on a circuit diagram consisting of a plurality of elements and inter-element wiring. a data input process in which data of each element and each wiring of the circuit diagram and data of cells corresponding to these elements are input; and terminal coordinates of each element and position coordinates of wiring in the circuit diagram are input to the corresponding cell. a coordinate conversion process for converting based on the size of the coordinates; and a placement process for arranging each corresponding cell based on the coordinates converted in the coordinate conversion process, and determining the positional relationship of each element and each wiring in the circuit diagram. 1. A method for creating a mask pattern for an integrated circuit, characterized by holding the following.