JP3141444B2 - Integrated circuit automatic layout system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic layout system for a gate array (fixed base type) in a semi-custom LSI.

[0002]

2. Description of the Related Art At present, it is an issue for a set maker to shorten the development period, to reduce the size and weight of the set, to reduce the cost, and to differentiate itself from other companies by unique functions and performance.

[0005] As a means for realizing this differentiation, semi-custom LSIs have been greatly expanded year by year. More recently,
In addition to the use of semi-custom LSIs for digital signal processing circuits, demand for semi-custom LSIs for analog circuits is increasing.

[0004] Semi-custom LSIs are roughly classified into a standard cell system and a gate array system with a fixed base. The present invention relates to a gate array system.

As described above, in an analog circuit or a gate array including an analog circuit, how to quickly and accurately complete the layout design of the analog circuit is as follows.
The shortest design period (T
AT). That is, in an analog circuit, the layout determines the electrical characteristics. For this reason, the layout design of the analog circuit has been centered on manual design. In recent years, some automatic layout systems that can be applied to analog circuits have come out in automatic layout systems that perform automatic layout by a program. The program used in this automatic layout system is to automatically arrange in an arbitrary area of a base for each circuit block having a hierarchical structure (hereinafter referred to as a sub-circuit). In other words, analog circuits use this function,
By setting an area (region) that satisfies the ratio accuracy of the base-emitter voltage V _BE of the transistor and the relative ratio of the resistance, the pairing is maintained even if the elements are automatically arranged in the area. Because.

FIG. 9 is a block diagram showing a main part of an example of such a conventional integrated circuit automatic layout system.
In this conventional example, the automatic layout means 4 includes an automatic arrangement means 44 and an automatic wiring means 45. Then, the automatic arrangement means 44 automatically converts each element data (for example, a symbol of an NPN transistor of a reference size and a symbol of a reference resistor) in the circuit connection information 1 of the sub-circuit into layout data corresponding to the element data in an arbitrary area on the base. After setting (hereinafter referred to as automatic placement) and placement of all elements is completed, automatic wiring is performed by the automatic wiring means 45, and layout data 3 including wiring data is output.

[0007]

As described above, in the conventional analog circuit section of a gate array, a layout design is often used to obtain desired electrical characteristics. In recent years, as an integrated circuit automatic layout system, a system in which a sub-circuit is arranged in an appropriate area of a base has been developed. However, in order to obtain high accuracy, this conventional integrated circuit automatic layout system cannot cope with the situation unless the sub-circuit is finely divided and the arrangement area of the base is small. This is unbalanced with the hierarchical level of circuit design, and there are many problems in realizing a high-precision analog circuit. In addition, since circuit elements are defined one by one as underlying elements, it is unclear whether all sub-circuits will be placed in a predetermined area until after execution.

As described above, in the prior art, the design method of the analog circuit of the gate array has problems such as a method of separating subcircuits and a layout design, and a problem that a short design required period which is an original sales merit of the gate array cannot be achieved. was there.

An object of the present invention is to provide an integrated circuit automatic layout system for a gate array which can realize a short design period by solving the above-mentioned problems.

[0010]

According to the present invention, there is provided a gate array having automatic layout means for inputting circuit connection information and layout position area designation information, automatically arranging and wiring elements, and outputting layout data. In the integrated circuit automatic layout system of the type, the automatic layout means comprises:
An element-by-element counting unit that counts the number of each element from the circuit connection information, an arrangement-possible element-by-element counting unit that counts the number of elements that can be arranged in a region specified by the arrangement position area designation information, and Comparing means for comparing the count result by the element-specific counting means with the count result by the allocable element-specific counting means to determine whether or not a desired element can be arranged; and determining that the element can be arranged by the comparing means. In the case where the element is included in the specified area while referring to the element precision information and the element restriction information of the maximum distance included in the circuit connection information ,
Place where it cannot be arranged to satisfy the required accuracy
In this case, an automatic arrangement means for outputting an alarm is provided.

[0011]

According to the present invention, first, it is determined whether or not an element to be arranged can be arranged in a base area arbitrarily designated in advance by element-based counting means, allocable element-based counting means, and comparing means. After it is determined that arrangement is possible, automatic arrangement is performed by the automatic arrangement means with reference to element restriction information for each element such as an element pair and specific accuracy included in the circuit connection information.

Therefore, it is possible to automatically arrange the elements satisfying the desired specific accuracy in the set area of the base,
It is possible to shorten the required design time.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.

In this embodiment, an integrated circuit automatic circuit 4a having automatic layout means 4a for inputting circuit connection information 1a and layout position area designation information 2a, automatically arranging and wiring elements, and outputting layout data 3 is provided. In the layout system, the automatic layout means 4a, which is a feature of the present invention, includes an element-specific counting means 41 for counting the number of elements for each element based on the circuit connection information 1a, and an automatic layout means 4a in an area designated by the arrangement position area designation information 2a. Arrangeable element-specific counting means 4 for counting the number of elements which can be arranged for each element
2, a comparing unit 43 that compares the count result of the element-specific counting unit 41 with the count result of the allocable element-specific counting unit 42 to determine whether or not a desired element can be arranged. An automatic arranging means 44a for automatically arranging the elements while referring to the element restriction information 5 included in the circuit connection information 1a when the arrangement is determined to be possible. Automatic wiring means 45a for performing automatic wiring is included.

Here, the automatic layout means 4a
Is realized using, for example, a CPU operated by an application program.

Next, an outline of the operation of this embodiment will be described with reference to FIG.
This will be described with reference to the flowchart shown in FIG.

First, the element-specific counting means 41
The circuit connection information 1a is read, and the number is counted for each element (hereinafter, this number is referred to as the number A) (step S1). Next, the allocable element-specific counting means 42 reads the arranging position area specifying information 2a including the arbitrarily predetermined base specifying area, and counts the number of elements that can be laid out in the specified area (hereinafter, referred to as the following). This number is referred to as the number B.) (Step S2). As an example of a method of counting usable elements based on this background information, in the gate array, each element is already arranged on the background with each coordinate, and it is defined whether the element is used or not from the circuit connection information. Therefore, if an arbitrary background position and area are set, the type and number of elements can be easily calculated from the coordinates.

Next, the comparing means 43 compares the number A with the number B to determine whether or not a desired element can be arranged in the designated area (step S3). If placement is impossible, an alarm is generated (step S7).

When the comparing means 43 determines that the element can be arranged, the automatic arranging means 44a
With reference to the element restriction information 5 including the element pair and the ratio accuracy, the elements are automatically arranged in the designated area (step S).
4). Here, the elements are sequentially arranged in order from the element required to have a high specificity pair property. Depending on the required specific accuracy and the size of the sub-circuit, the area to be arranged may be arranged in a smaller area in the set area. That is, since the pairing is usually related to the influence of etching on diffusion and the like, the further the element requiring the pairing is, the worse it becomes. In other words, since the maximum distance between the elements is relatively determined according to the desired accuracy, a table of the specific accuracy and the maximum distance is prepared in advance, and the layout is determined based on the circuit connection information and the specific accuracy described with reference to this table. Possible area can be set. If an arrangement that satisfies the element restriction information 5 cannot be performed (step S5), an alarm is generated (step S7).

When the automatic placement is completed, the wiring is automatically performed by the automatic wiring means 45a, and the layout data 3 is output (step S6). Here, the element replacement is performed by satisfying the element restriction information 5 so that the net is further shortened after the automatic wiring.

Next, the operation of this embodiment will be described with reference to FIGS.
A specific example will be described in detail with reference to FIG.

FIG. 3 shows an example of the circuit connection information 1a, FIG. 4 shows the connection information 6, FIG. 5 shows the element restriction information 5, and FIG. 2
FIG. 7A is a diagram showing the number A of element-specific counts, FIG. 7B is a diagram showing the number B of allocable element-specific counts, and FIG. It is a figure showing a state.

As shown in FIG. 3, the target circuit is an NPN bipolar transistor Q having an element name A1.
And 1 and Q2, and the transistor Q3 of the device names A2, a resistor R1, R2, R4 and R5 of the element name B1, and a resistor R3 of the element name B2.

As shown in FIG. 6, a designated area 7 is given to the designated area by the arrangement position / area designation information 2a.

Referring to FIGS. 3 and 6, the counting means 41 for each element and the counting means 42 for each disposable element are shown.
The number A and the number B, respectively, are calculated as shown in FIGS. 7A and 7B by the number A41a.
And the number B42a.

Next, the comparing means 43 compares the number 41a with the number 42a. In this example, since the number of the elements B1 counted from the designated area 7 is eight and the number of the elements B1 counted from the circuit connection information 1a is four, the arrangement of the elements B1 is possible. The same applies to other elements.

Next, automatic placement is performed by the automatic placement means 44a, and placement is performed according to the circuit connection information 1a. That is, as shown in FIG. 4, connection information 7 in which a pair symbol and a precision symbol are added to the circuit connection information 1a together with the circuit element name, the used element name, and the terminal connection information is searched for automatic placement.

The pair symbol is used to designate the elements requiring pairing with the same symbol. In this case, there is naturally no problem with a pair of two or more elements. The relative precision symbol is a symbol determined by the required precision. As shown in FIGS. 4 and 5, the ratio accuracy of the transistors Q1 and Q2 requiring the pair property is Δ5m.
If you want to get V, add 2.

In the automatic arrangement, the elements are arranged by deciding the priority order according to the precision symbol. At this time, the elements are arranged with reference to the pair symbols. That is, as shown in FIG. 8, the transistor Q1 is set for the underlying element A1 and the transistor Q1 is set.
The transistor Q2 requiring pairing is defined by selecting an element A1 within a range determined by desired accuracy. In this example, since the ratio of the transistors Q1 and Q2 is within the range 71 of the maximum distance of 50 μm from the ratio accuracy Δ5 mV, the transistor Q1 arbitrarily disposed and the element A within 50 μm thereof
One of the ones is defined as transistor Q2. Similarly, the resistor R2 (B1) arbitrarily arranged from the background information
The element B2 element within a range 72 of 30 μm is selected,
One of them is defined as resistor R3. Note that, as the resistor R1 without the pair designation, an appropriate element B1 in the designated region 7 is defined. In this case, the replacement of the elements is repeated due to the pairing between the elements, and as shown in FIG. 8, the proper element arrangement is completed, and all the elements on the sub-circuit are defined in the designated area 7 on the base. .

Next, automatic wiring is performed by the automatic wiring means 45a, and when unconnection or concentration of wiring occurs, re-execution is performed by the automatic arranging means 44a, and further element replacement such as shortening the net is performed.

In the present invention, an element having the same base or an array of different elements may be used, and the element structure may be a bipolar element or a CMOS element. Further, the application circuit has been described as an analog circuit having a limited layout, but can be applied to a digital circuit.

[0033]

As described above, according to the present invention,
Based on the connection information of the sub-circuit, automatic placement that satisfies the desired element ratio accuracy in the set area of the base becomes possible, and in particular, the design period of the gate array including the analog circuit can be shortened. Is great.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a flowchart showing an outline of the operation.

FIG. 3 is a diagram showing an example of the circuit connection information.

FIG. 4 is a diagram showing the connection information.

FIG. 5 is a diagram showing the contents of the element restriction information.

FIG. 6 is a diagram showing an example of the arrangement position area designation information.

FIG. 7 is a diagram showing the number A of element-based counts and the number B of arrangeable element-based counts;

FIG. 8 is a diagram showing an arrangement state in a designated area.

FIG. 9 is a block diagram showing a main part of a conventional example.

[Explanation of symbols]

 1, 1a Circuit connection information 2 Arrangement position designation information 2a Arrangement position area designation information 3 Layout data 4, 4a Automatic layout means 5 Element restriction information 6 Connection information 7 Designation area 41 Element-specific count means 41a (Count of element-specific) A 42 Arrangement-based element counting means 42a Number (of arrangement-possible element-based counts) B 43 Comparison means 44, 44a Automatic arrangement means 45, 45a Automatic wiring means 71, 72 Range S1 to S6 Step

Claims (1)

(57) [Claims] 1. A gateway having automatic layout means for inputting circuit connection information and layout position area designation information, automatically arranging and wiring elements, and outputting layout data.
In an integrated circuit automatic layout system of the Ray type, the automatic layout means includes element-specific counting means for counting the number of elements for each element from the circuit connection information, and elements which can be arranged in a region designated by the arrangement position area designation information. And a count result by the element-by-element counting means and a count result by the countable element-by-element-counting means to determine whether a desired element can be arranged. A comparing unit, and an element included in the circuit connection information when it is determined that the element can be arranged by the comparing unit .
The element satisfies the required accuracy in the specified area while referring to the element accuracy information of the specific accuracy and the maximum distance.
Automatic layout means for performing an alarm output when the layout cannot be performed .