CN110781641B

CN110781641B - Method for quickly identifying and correcting sensitive graph in layout

Info

Publication number: CN110781641B
Application number: CN201911017410.6A
Authority: CN
Inventors: 吕江萍
Original assignee: China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
Current assignee: China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
Priority date: 2019-10-24
Filing date: 2019-10-24
Publication date: 2023-10-10
Anticipated expiration: 2039-10-24
Also published as: CN110781641A

Abstract

The invention discloses a method for quickly identifying and correcting sensitive patterns in a layout, which comprises the following steps: step 1, a layout unit or a general diagram is opened, and related information of a sensitive graph is defined; step 2, searching sensitive graphs of the layout units or the total graphs one by one, confirming whether the design requirements of the sensitive graphs are met, if the design requirements are met, confirming the next sensitive graph, if the design requirements are not met, outputting relevant information of the sensitive graph, highlighting violation graphs, correcting the violation graphs, and finally confirming correction graphs; and step 3, repeating the steps until all the sensitive graphs in the layout unit or the master graph are confirmed. The method can avoid inconsistent design standards and missing in manual inspection of different layout engineers, unify the design requirements of sensitive graphs, and greatly shorten the pre-flow inspection time of the integrated circuit layout design, so that the whole circuit design flow is more efficient.

Description

Method for quickly identifying and correcting sensitive graph in layout

Technical Field

The invention relates to the field of automatic design of integrated circuit layouts, in particular to a method for quickly identifying sensitive graphs in a layout.

Background

In integrated circuit layout design, layout designers convert circuit structures into patterns of different levels meeting process rules, the layout is generally required to be checked and confirmed before layout design inspection and starting sheet flow are completed, and currently, the inspection is mainly required to pass through circuit layout consistency (LVS) inspection, and in high-precision integrated circuit layout design, a large number of circuit sensitive structures, namely layout sensitive patterns, such as input pair tubes of operational amplifiers and comparators, unit modules requiring symmetry and the like, are required to be designed, and are critical to the performance and precision of a circuit. Along with the gradual increase of the circuit scale, the layout sensitive graphs are more and more, the sensitive graphs are often designed by different layout engineers, the design standards are inconsistent, and meanwhile, corresponding tools for checking and confirming the layout sensitive graphs are also lacked, and the layout sensitive graphs are usually checked and confirmed one by manpower, so that the possibility of omission exists.

Disclosure of Invention

Aiming at the problems, the invention provides a method for quickly identifying and correcting the sensitive graph in the layout, which avoids the problems of inconsistent design standard of the sensitive graph and omission in manual inspection.

In order to solve the technical problems, the invention adopts the following technical scheme:

a method for quickly identifying and correcting sensitive patterns in a layout comprises the following steps:

step 1, a layout unit or a general diagram is opened, and related information of a sensitive graph is defined;

step 2, searching sensitive graphs of a layout unit or a total graph one by one, confirming whether the design requirement of the sensitive graph is met, if the design requirement is met, confirming the next sensitive graph, if the design requirement is not met, outputting relevant information of the sensitive graph, highlighting a sensitive graph which does not meet the design requirement at the position, namely, a violation graph, correcting the violation graph, highlighting a correction graph of the violation graph, and finally confirming the correction graph;

and step 3, repeating the steps until all the sensitive graphs in the layout unit or the master graph are confirmed.

Further, in step 1, the relevant information of the sensitive graph includes classification of sensitive devices and classification of sensitive structures.

Further, in step 2, the design requirements of the sensitive graph include whether the devices are symmetrically arranged, whether virtual devices (dummy) are arranged around the devices, and whether the wiring is symmetrical.

Further, in step 2, the output sensitive graphic related information includes a unit name and a location coordinate.

Further, under the environment of the Virtuoso software, after importing one layout data, opening a layout unit or a total diagram.

Further, the sensitive device classifications include, but are not limited to, PMOS devices, NMOS devices.

Further, classifications of sensitive structures include, but are not limited to, PMOS proportional current mirrors, NMOS differential input pair tubes.

The invention has the beneficial effects that:

compared with the prior art, the method can avoid inconsistent design standards and missing possibility of manual inspection of different layout engineers, unify the design requirements of sensitive graphs, and greatly shorten the pre-flow inspection time of the integrated circuit layout design, so that the whole circuit design flow is more efficient.

Drawings

FIG. 1 is a flow chart for quickly identifying sensitive patterns in a layout;

FIG. 2 is a schematic diagram of an operational amplifier circuit;

FIG. 3A is a schematic diagram of an original layout of an operational amplifier circuit;

fig. 3B is a schematic diagram of an operational amplifier circuit consistent with the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.

The invention discloses a method for quickly identifying and correcting sensitive patterns in a layout, which is shown in figure 1. After importing layout data, opening a layout unit or a total diagram, carrying out operation of quickly identifying and correcting sensitive patterns in the layout, defining related information of the sensitive patterns, including classification and form of sensitive unit modules, sensitive devices and sensitive structures, carrying out selection setting according to specific layout, searching the sensitive patterns of the layout unit or the total diagram, confirming whether the design requirements of the sensitive patterns are met one by one, if so, confirming the next sensitive pattern, if not, outputting related sensitive pattern information, such as unit names and position coordinates, highlighting the sensitive patterns which do not meet the design requirements, namely, violating the patterns, correcting the violating patterns, highlighting the correction patterns of the violating patterns, enabling the correction patterns to meet the design requirements of the sensitive patterns, and finally confirming the correction patterns. According to the layout situation, the identification and correction of the unit modules can be performed first, and then the identification and correction of the overall map of the layout can be performed. The steps can be repeated to quickly identify and correct the sensitive graph in the layout until all the sensitive graph is confirmed.

The method comprises the following specific steps:

in the environment of Virtuoso software, taking a circuit and a layout of an operational amplifier circuit as examples, the detailed step description of the method is carried out.

The operational amplifier circuit is shown in fig. 2, wherein PM1 and PM2 are proportional current mirror structures, W/L sizes of PM1 and PM2 are 2:1 relations, NM1 and NM2 are differential input pair tubes, W/L sizes of NM1 and NM2 are 1:1 relations, PM1 and PM2, NM1 and NM2 are circuit sensitive structures, corresponding layout patterns are sensitive patterns, fig. 3A is an original layout corresponding to fig. 2, fig. 3B is a layout corresponding to fig. 2 and processed by the sensitive circuits, and the layout comprises symmetrical arrangement of devices, addition of dummy devices around the devices and the like. The layout unit is opened to perform the operation of quickly identifying and correcting the sensitive patterns in the layout, and related information of the sensitive patterns is defined, wherein the related information comprises device classification, such as PMOS devices, NMOS devices and the like, and classification of sensitive structures, such as PMOS proportional current mirrors PM1 and PM2, NMOS differential input pair transistors NM1 and NM2 and the like. And searching sensitive patterns of layout units, and determining whether the requirements are met one by one, such as whether the devices are symmetrically arranged, whether dummy exists around the devices, whether wiring is symmetrical or not, and the like, wherein in fig. 3B, symmetrical arrangement is performed in PM1 and PM2, NM1 and NM2, dummy devices are added around the devices to enable the devices to meet the requirements of the sensitive patterns, then determining the next sensitive pattern, and if the next sensitive pattern is not met, outputting relevant sensitive pattern information, such as a unit name and a coordinate position where the unit is located. Simultaneously highlighting the violation pattern, such as all devices in fig. 3A, highlighting the correction pattern of the violation pattern, such as all devices in fig. 3B plus dummy devices, and finally confirming the correction pattern. The above structures requiring sensitivity, such as bipolar transistors, resistors and capacitors, unit modules requiring symmetry, etc., of other devices in the circuit can be set according to the method, so as to quickly identify and correct the sensitive patterns in the layout, until all the layouts finish the confirmation of the sensitive patterns.

In the actual layout inspection, the recognition and correction of the unit modules can be performed first, and then the recognition and correction of the overall layout diagram can be performed. The sensitive graph in the layout can be repeatedly identified and corrected quickly until the confirmation is completed. The method avoids the possibility of inconsistent design standards and omission in manual inspection in the design of different layout engineers, unifies the design requirements of sensitive graphs, and greatly shortens the pre-flow inspection time of the integrated circuit layout design, so that the whole circuit design flow is more efficient.

The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.

Claims

1. A method for quickly identifying and correcting sensitive patterns in a layout is characterized by comprising the following steps:

step 1, a layout unit or a general diagram is opened, and related information of a sensitive graph is defined; the related information of the sensitive graph comprises the classification of sensitive devices and the classification of sensitive structures;

step 2, searching sensitive graphs of a layout unit or a total graph one by one, confirming whether the design requirement of the sensitive graph is met, if the design requirement is met, confirming the next sensitive graph, if the design requirement is not met, outputting relevant information of the sensitive graph, highlighting a sensitive graph which does not meet the design requirement at the position, namely, a violation graph, correcting the violation graph, highlighting a correction graph of the violation graph, and finally confirming the correction graph; the design requirements of the sensitive graph comprise whether the devices are symmetrically arranged, whether virtual devices exist around the devices and whether wiring is symmetrical; the output sensitive graph related information comprises a unit name and a position coordinate;

2. A method for quickly identifying and correcting sensitive patterns in a layout according to claim 1 wherein the sensitive device classes include, but are not limited to, PMOS devices, NMOS devices.

3. The method for quickly identifying and correcting sensitive patterns in a layout according to claim 1, wherein the classification of sensitive structures comprises, but is not limited to, PMOS proportional current mirrors, NMOS differential input pair tubes.