CN110781641A

CN110781641A - Method for quickly identifying and correcting sensitive graph in layout

Info

Publication number: CN110781641A
Application number: CN201911017410.6A
Authority: CN
Inventors: 吕江萍
Original assignee: China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
Current assignee: China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
Priority date: 2019-10-24
Filing date: 2019-10-24
Publication date: 2020-02-11
Anticipated expiration: 2039-10-24
Also published as: CN110781641B

Abstract

The invention discloses a method for quickly identifying and correcting sensitive graphs in a layout, which comprises the following steps: step 1, opening a layout unit or a general graph, and defining related information of a sensitive graph; step 2, searching the sensitive graphs of the layout unit or the general graph, confirming one by one whether the design requirements of the sensitive graphs are met, if the design requirements are met, confirming the next sensitive graph, if the design requirements are not met, outputting the related information of the sensitive graph, highlighting the violating graph, correcting the violating graph, and finally confirming the corrected graph; and 3, repeating the steps until all the sensitive graphs in the layout unit or the general graph are confirmed. The method can avoid the design of different layout engineers with inconsistent design standards and the possibility of omission of manual inspection, unify the design requirements of sensitive graphs, and greatly shorten the check time before the tape-out of the integrated circuit layout design, so that the whole circuit design process is more efficient.

Description

Method for quickly identifying and correcting sensitive graph in layout

Technical Field

The invention relates to the field of automatic design of integrated circuit layouts, in particular to a method for quickly identifying sensitive graphs in a layout.

Background

In the integrated circuit layout design, a layout designer converts a circuit structure into graphs of different levels meeting process rules, generally needs to check and confirm a layout before completing layout design check and starting tape-out, and at present, the requirement is mainly to check the consistency (LVS) of the circuit layout. With the gradual increase of the circuit scale, more and more layout sensitive graphs are designed by different layout engineers, the design standards are inconsistent, and meanwhile, a corresponding tool for checking and confirming the layout sensitive graphs is lacked, so that the checking and confirming are usually carried out manually one by one, and the possibility of omission exists.

Disclosure of Invention

Aiming at the problems, the invention provides a method for quickly identifying and correcting sensitive graphs in a layout, and solves the problems of inconsistent design standards of the sensitive graphs and omission in manual inspection.

In order to solve the technical problems, the invention adopts the following technical scheme:

a method for rapidly identifying and correcting sensitive graphs in a layout comprises the following steps:

step 1, opening a layout unit or a general graph, and defining related information of a sensitive graph;

step 2, searching the sensitive graphs of the layout unit or the general graph, confirming whether the design requirements of the sensitive graphs are met one by one, if the design requirements are met, confirming the next sensitive graph, if the design requirements are not met, outputting the relevant information of the sensitive graphs, highlighting the sensitive graphs which are not designed to meet the requirements, namely the violating graphs, correcting the violating graphs, highlighting the corrected graphs of the violating graphs, and finally confirming the corrected graphs;

and 3, repeating the steps until all the sensitive graphs in the layout unit or the general graph are confirmed.

Further, in step 1, the relevant information of the sensitive pattern includes the classification of the sensitive device and the classification of the sensitive structure.

Further, in step 2, the design requirements of the sensitive pattern include whether the devices are symmetrically arranged, whether dummy devices (dummy) are around the devices, and whether the wiring is symmetrical.

Further, in step 2, the relevant information of the sensitive graph output includes the unit name and the location coordinate.

Furthermore, in the environment of Virtuoso software, after importing a layout data, opening a layout unit or a general diagram.

Further, sensitive device classes include, but are not limited to, PMOS devices, NMOS devices.

Further, the classification of the sensitive structure includes, but is not limited to, PMOS proportional current mirror, NMOS differential input pair transistor.

The invention achieves the following beneficial effects:

compared with the prior art, the method can avoid the design standard inconsistency of different layout engineers and the possibility of omission of manual inspection, unify the design requirements of sensitive graphs, and greatly shorten the check time before the tape-out of the integrated circuit layout design, so that the whole circuit design process is more efficient.

Drawings

FIG. 1 is a flow chart for rapidly identifying sensitive patterns in a layout;

FIG. 2 is a schematic diagram of an operational amplifier circuit;

FIG. 3A is a diagram of an original layout of an operational amplifier circuit;

fig. 3B is a schematic layout diagram of an operational amplifier circuit according to the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

The invention discloses a method for quickly identifying and correcting sensitive graphs in a layout, which is shown in figure 1. After importing a layout data, opening a layout unit or a general diagram, rapidly identifying and correcting the sensitive graph in the layout, firstly defining the relevant information of the sensitive graph, including the classification and the form of a sensitive unit module, a sensitive device and a sensitive structure, selectively setting according to the specific layout, searching the sensitive graph of the layout unit or the general diagram, confirming whether the design requirements of the sensitive graph are met one by one, such as whether the devices are symmetrically arranged, whether virtual devices exist around the devices, whether wiring is symmetrical, if the requirements are met, confirming the next sensitive graph, if the requirements are not met, outputting the relevant sensitive graph information, such as the unit name and the position coordinates of the unit, highlighting the sensitive graph which is not met with the requirements, namely the violated graph, correcting the violated graph, and highlighting the corrected graph violating the graph, the design requirements of the sensitive graph are met, and finally the corrected graph is confirmed. According to the layout condition, the unit modules can be recognized and corrected firstly, and then the layout general diagram can be recognized and corrected. The steps can be repeated to quickly identify and correct the sensitive graphs in the layout until all the sensitive graphs are confirmed.

The method comprises the following specific steps:

in the environment of Virtuoso software, the detailed steps of the method are explained by taking a circuit and a layout of an operational amplifier circuit as an example.

The operational amplifier circuit is shown in fig. 2, wherein PM1 and PM2 are proportional current mirror structures, the W/L sizes of PM1 and PM2 are 2:1, NM1 and NM2 are differential input pair transistors, the W/L sizes of NM1 and NM2 are 1:1, PM1 and PM2, NM1 and NM2 are circuit sensitive structures, corresponding layout patterns are sensitive patterns, fig. 3A is an original layout corresponding to fig. 2, and fig. 3B is a layout processed by the sensitive circuit corresponding to fig. 2, and the layout includes symmetrical arrangement of devices, addition of dummy devices around the devices, and the like. And opening the layout unit, carrying out rapid identification and correction operation on the sensitive graph in the layout, and defining related information of the sensitive graph, including device classification, such as PMOS devices, NMOS devices and the like, and classification of sensitive structures, such as PMOS proportional current mirrors PM1 and PM2, NMOS differential input pair transistors NM1 and NM2 and the like. And searching the sensitive graphs of the layout units, and confirming whether the sensitive graphs meet the requirements one by one, such as whether the devices are symmetrically arranged, whether dummy devices exist around the devices, whether wiring is symmetrical, and the like, as shown in fig. 3B, symmetrically arranging the devices in PM1 and PM2, NM1 and NM2, adding dummy devices around the devices, and the like so as to meet the requirements of the sensitive graphs, confirming the next sensitive graph, and if the sensitive graphs do not meet the requirements, outputting relevant sensitive graph information, such as unit names and coordinate positions where the sensitive graphs are located. At the same time, highlighting the violation pattern, e.g., all devices in FIG. 3A, highlighting the correction pattern of the violation pattern, e.g., all devices in FIG. 3B, and adding dummy devices, and finally confirming the correction pattern. The structures requiring sensitivity, such as other devices in the circuit, such as bipolar transistors, resistance capacitors, unit modules requiring symmetry and the like, can also be set according to the method, and sensitive graphs in the layout are rapidly identified and corrected until all the layouts are confirmed.

In the actual layout inspection, the identification and correction of the unit module can be carried out firstly, and then the identification and correction of the layout general diagram can be carried out. And the sensitive graphs in the layout can be repeatedly and rapidly identified and corrected until the confirmation is completely finished. The design method avoids the possibility of design standard inconsistency and omission of manual inspection in different layout engineer designs, unifies the design requirements of sensitive graphs, and greatly shortens the check time before tape-out of the integrated circuit layout design, so that the whole circuit design process is more efficient.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims

1. A method for quickly identifying and correcting sensitive graphs in a layout is characterized by comprising the following steps:

2. The method for rapidly identifying and correcting the sensitive graphics in the layout as claimed in claim 1, wherein in the step 1, the related information of the sensitive graphics comprises the classification of sensitive devices and the classification of sensitive structures.

3. The method for rapidly identifying and correcting the sensitive graph in the layout as claimed in claim 1, wherein in the step 2, the design requirements of the sensitive graph include whether the devices are symmetrically arranged, whether virtual devices are around the devices, and whether the wiring is symmetrical.

4. The method for rapidly identifying and correcting the sensitive graph in the layout as claimed in claim 1, wherein in the step 2, the relevant information of the sensitive graph output comprises the name and the position coordinates of the cell.

5. The method as claimed in claim 2, wherein the sensitive devices are classified as PMOS devices and NMOS devices.

6. The method as claimed in claim 2, wherein the classification of the sensitive structure includes, but is not limited to, PMOS proportional current mirror, NMOS differential input pair transistor.