CN115796113A - Method, device and storage medium for rapidly analyzing EM/IR of integrated circuit layout - Google Patents

Method, device and storage medium for rapidly analyzing EM/IR of integrated circuit layout Download PDF

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CN115796113A
CN115796113A CN202211546112.8A CN202211546112A CN115796113A CN 115796113 A CN115796113 A CN 115796113A CN 202211546112 A CN202211546112 A CN 202211546112A CN 115796113 A CN115796113 A CN 115796113A
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effective
circuit layout
mos tube
integrated circuit
load current
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李雷
陈志东
刘伟平
陆涛涛
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Shanghai Huada Jiutian Information Technology Co ltd
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Abstract

The invention discloses a method, a device and a storage medium for rapidly analyzing EM/IR of an integrated circuit layout. The method loads the acquired load current corresponding to the effective MOS tube to the position of the power supply wiring of the effective MOS tube; extracting a resistance network of a configuration area of the effective MOS tube based on the loaded load current, establishing a resistance network matrix, and calculating an electrical index parameter for analyzing EM/IR in circuit wiring related to the effective MOS tube based on the resistance network matrix; and outputting the analysis result of the EM/IR of the integrated circuit layout.

Description

Method, device and storage medium for rapidly analyzing EM/IR of integrated circuit layout
Technical Field
The invention relates to the technical field of design analysis of EDA tools, in particular to a method and a device for rapidly analyzing power supply/ground layout EM/IR and a storage medium.
Background
With the process of the ultra-large scale integrated circuit entering a deep submicron stage, the power supply voltage of the chip is reduced, and the resistance of a power supply/ground network cannot be ignored. The power grid on the chip (including power and ground signals) is generally treated as an ideal network. In fact, this assumption does not exist in engineering design, and particularly as integrated circuit processes evolve to and below ultra-deep sub-microns, the impedance characteristics of all interconnect lines, including power supply networks, are very significant. Due to the existence of the resistance, the capacitance and the inductance of the interconnection line of the power supply network, the voltage on the power supply network fluctuates, and the voltage value is no longer a stable and unchangeable single value, thereby causing the problems of power supply voltage drop (IR-drop) and ground voltage rise or ground-bounce (ground-bounce). For simplicity, the following "power source" includes a power signal VDD and a ground signal VSS; the "IR drop" includes a voltage drop on the power signal VDD and a voltage bounce on the ground signal VSS.
IR drop is a phenomenon that indicates a voltage drop or rise on the power and ground networks present in an integrated circuit. The magnitude of the voltage drop is determined by the magnitude of the equivalent resistance from the power supply to the logic gate cell being calculated. The IR drop may be local or global. When a certain number of logic gate units in adjacent positions have logic turnover actions at the same time, the local IR drop phenomenon is caused, and when the resistance value of a certain part of the power grid is particularly high, the local IR drop is also caused; when logic in one area of the chip causes IR drop in other areas, it is called a global phenomenon.
The IR drop problem often behaves like some timing and may even be a signal integrity problem. If the global IR drop of the chip is too high, the logic gate will have a functional failure, causing the chip to fail completely, although logic simulations show that the design is correct. The local IR drop is sensitive and may occur only under certain conditions, such as when all bus data is flipped synchronously, so that the chip may intermittently exhibit some functional failures. The more common effect of IR drop is to slow down the chip.
In addition to voltage fluctuations, the current capability that can be tolerated on the power network wiring is also a matter of concern in power supply design. The metal layer used as the interconnection line has a certain limit on the maximum current allowed to flow on the metal layer under a certain manufacturing process, otherwise, the excessive current can cause the metal connecting line to be fused after a large current flows for a period of time, and the chip is failed. This phenomenon is called Electromigration (EM).
Electromigration (EM) problems are used to indicate some of the causes of failure that lead to cracking, melting, etc. of the metal interconnect lines on the chip. When electrons flow through the metal line, they collide with atoms of the metal line, which causes the resistance of the metal to increase and heat to be generated. Electromigration (EM) is a long-term depletion phenomenon that often manifests as timing or functional errors in the chip over time. If a single wire in a chip is unique, the electromigration problem will cause the whole chip to fail. If some of the connections are inherently redundant in design, such as in a power supply network, some of the connections will be disconnected when electromigration problems occur, while other connections will suffer from larger IR drop problems. If a short circuit between the lines occurs due to electromigration, the entire chip fails.
In the prior art, analyzing the EM/IR in the power/ground layout depends on a simulation technique to simulate the voltage of a corresponding point and solve the EM/IR information. The problem is that the required conditions are too many, 1. A front-end engineer is required to provide a 'virtual platform' testbench;2. a back-end engineer is required to complete the layout completely, and a special DSPF (customized Standard Parasitic Format) for EM/IR calculation is extracted; 3. analysis and modification of results requires a front-end engineer to coordinate the iteration.
In addition, the traditional method for analyzing the current density and voltage drop of the power supply/ground layout needs to call a simulator, set up testbench to simulate and obtain voltage current points at corresponding positions, and then obtain EM/IR at corresponding positions.
Disclosure of Invention
The present invention has been made in view of the above problems. Aiming at the problems that the traditional process of analyzing the current density, the voltage drop and the like in the integrated circuit layout needs more steps, more tools and the like, the invention aims to provide a method for rapidly analyzing the EM/IR of the integrated circuit layout.
Means for solving the technical problem
A method for rapidly analyzing EM/IR of an integrated circuit layout, comprising:
(1) Searching MOS tubes connected with a power supply/ground network in the integrated circuit layout;
(2) Screening and extracting effective MOS tubes in a normal saturation region working state based on the searched MOS tubes;
(3) According to the size of the effective MOS tube, obtaining a load current corresponding to the effective MOS tube by referring to a preset normalized load current of the MOS tube with unit size, and loading the obtained load current and the obtained load current to the position of a power supply wiring of the effective MOS tube;
(4) Extracting a resistance network of a configuration area of the effective MOS tube based on the loaded load current and establishing a resistance network matrix;
(5) Calculating an electrical index parameter for analyzing EM/IR in circuit wiring related to the effective MOS tube based on the resistance network matrix; and
(6) And outputting the analysis result of the EM/IR of the integrated circuit layout.
In an implementation manner of the present invention, for an effective MOS transistor composed of a plurality of single gates, a plurality of load currents corresponding to the plurality of single gates are respectively calculated according to the size of the single gate, and the calculated plurality of load currents are used as the load currents of the effective MOS transistor.
In an implementation mode of the invention, voltage excitation is applied to an input end of an effective MOS tube, resistance information including metal, a via hole, a contact hole and an active region related to the effective MOS tube is extracted according to a load current loaded at the position of the effective MOS tube, and a resistance network matrix is established based on the resistance information.
In one implementation manner of the present invention, the step (5) includes: using a formula
Figure BDA0003979980370000031
Calculating the voltage and power at each point in the circuit layout associated with the active MOS transistor, where P i Indicating the power, V, at each point in the circuit layout associated with an active MOS transistor i Showing each of the circuit wiring associated with the active MOS transistorVoltage of point, theta ij Represents the resistance value between the circuit wiring nodes associated with the effective MOS transistors, i, j =1, 2 … n, and
and calculating the current density of the circuit wiring related to the effective MOS tube according to the voltage and the power.
The invention also provides a device for rapidly analyzing EM/IR of the integrated circuit layout, which comprises a processing part, a storage part and a display part, wherein the storage part and the display part are connected with the processing part, and the processing part comprises:
the extraction module screens and extracts effective MOS tubes in a normal saturation region working state;
a load current loading module, which refers to a preset normalized load current of an MOS transistor with a unit size according to the extracted size of the effective MOS transistor, obtains a load current corresponding to the effective MOS transistor, and loads the obtained load current to a position where a power supply wiring of the effective MOS transistor is located;
the calculation module extracts a resistance network of the configuration area of the effective MOS tube based on the loaded load current, establishes a resistance network matrix, and calculates an electrical index parameter for analyzing EM/IR in circuit wiring related to the effective MOS tube based on the resistance network matrix;
and the output module is used for outputting the analysis result of the EM/IR of the integrated circuit layout.
The invention also provides a computer-readable storage medium having stored thereon a computer program for executing the method for fast analyzing EM/IR of an integrated circuit layout as claimed in any one of claims 1 to 5 when executedInvention of Effect。
The invention can quickly evaluate the EM/IR of the power supply network of any module in the integrated circuit layout of the finished product or the semi-finished product, and presents the robustness graphical result of the integrated circuit layout under the worst distribution condition to a user.
The invention simplifies the EM/IR analysis flow of the integrated circuit layout, reduces the working strength of front and back end engineers, improves the efficiency of power supply design and reduces the cost.
Drawings
FIG. 1 is a flow chart of an EM/IR method for rapidly analyzing an integrated circuit layout according to the present invention.
FIG. 2 is an integrated circuit layout obtained by the present invention.
Fig. 3 is a schematic diagram of an effective MOS transistor according to the present invention.
Fig. 4 is parameter information including loaded load current, rectangular area, etc. related to the active MOS transistor obtained by the present invention.
Fig. 5 is an analysis result of the voltage drop distribution shown in the present invention.
Fig. 6 shows the value and position of the voltage excitation applied to the active MOS transistor and the current value and position of the start terminal of the voltage AVDD according to the present invention.
Fig. 7 shows the analysis results of the current density according to the present invention.
FIG. 8 is a block diagram of a processing portion of the apparatus for rapidly analyzing EM/IR of an integrated circuit layout according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be described below clearly with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived from the embodiments in the present application by a person skilled in the art, are within the scope of protection of the present application.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
The EM/IR method for quickly analyzing the integrated circuit layout extracts an effective MOS tube connected with a power supply/ground network from the integrated circuit layout containing the power supply/ground, loads a load current corresponding to the effective MOS tube to a configuration area of the effective MOS tube, extracts a resistance network corresponding to the wiring of the effective MOS tube and establishes a resistance network matrix, then calculates a power spectrum, a voltage point and the like of a coordinate position corresponding to the effective MOS tube by using a matrix solver according to the resistance network matrix and a power supply excitation applied to the effective MOS tube, then calculates electrical index values such as current density, voltage drop and the like in the integrated circuit layout of the corresponding position by using a resistor connected with the corresponding node, and graphically draws the electrical index values.
The invention can quickly evaluate the EM/IR of the power/ground network of any module (BLOCK) in the layout of the finished or semi-finished integrated circuit, and present the graphical analysis result of the EM/IR of the robustness of the integrated circuit layout (Chinese.
FIG. 1 is a flow chart of an EM/IR method for rapidly analyzing an integrated circuit layout according to the present invention. The EM/IR method of the present invention for rapidly analyzing an integrated circuit layout is described in detail below with reference to FIG. 1. The invention comprises the following steps:
(1) Searching all MOS (metal oxide semiconductor) tubes connected with a power supply/ground network in the integrated circuit layout;
(2) Extracting effective MOS tubes in a normal saturation region working state from the searched MOS tubes;
in the specific embodiment of the invention, a part of the MOS tubes are filtered according to a preset rule aiming at the searched MOS tubes, and the MOS tubes meeting the rule (namely in a normal saturation region working state) are left as effective MOS tubes (current loads) for analysis.
(3) For an effective MOS transistor, assuming that the normalized load current of the MOS transistor with a unit width-to-length ratio is I, if the width-to-length ratio of a single effective MOS is k, the load current corresponding to the effective MOS is k × I.
And loading the obtained load current k I to the position of the power supply wiring of the effective MOS tube.
(4) Applying voltage excitation on the input end of the effective MOS tube, extracting a resistance network of a configuration area of the effective MOS tube in the integrated circuit layout and establishing a resistance network matrix based on the obtained load current corresponding to the effective MOS tube (namely the load current loaded at the position of the power supply wiring of the effective MOS tube);
(5) Based on the established resistance network matrix, exciting the voltage input by the effective MOS tube, and calculating an electrical index value which is related to the effective MOS tube and is used for performing EM/IR analysis;
(6) And outputting the EM/IR analysis result of the integrated circuit layout.
The invention comprises that the solved electric index values of voltage, current density spectrum and the like are shown in a graphical mode and the like at the position corresponding to the effective MOS tube.
In an embodiment of the present invention, an EM/IR method for rapidly analyzing an integrated circuit layout specifically includes the steps of:
first, in step 101, as shown in fig. 1, an integrated circuit layout including a power source/ground is obtained, and one or more effective MOS transistors in a normal saturation region operating state connected to a power source/ground network in the integrated circuit layout are screened and extracted.
In the embodiment of the invention, all the MOS tubes connected with the power supply/ground network in the integrated circuit layout are searched in a traversing way, and then whether the searched MOS tubes are the MOS tubes in the working state of the normal saturation region or not is judged (screened) one by one according to the set rule.
Specifically, the method for extracting effective MOS tubes according to the set rule comprises the following steps: (a) A number of Enable Signals (EN)/Power Down (PD) are preset. When screening MOS tubes, if the grid (Gate) of the MOS tube is marked as PD and EN, filtering the current MOS tube for the searched MOS tube; and (b) filtering the MOS tube with the source electrode source and the drain electrode drain in short circuit. It should be noted that the set rule is only an exemplary description of the present invention for extracting an effective MOS transistor, and the set rule is not limited to the above description, and is applicable to the present invention as long as the set rule can extract an MOS transistor in a normal saturation region operation state.
As shown in fig. 2, in the present invention, it is determined according to at least one of the above setting rules that 4 MOS transistors M5, M6, M7, and M8 are in a normal saturation region operating state, and therefore, the 4 MOS transistors M5, M6, M7, and M8 are determined as valid MOS transistors.
In step 102, for the extracted effective MOS transistor, a load current corresponding to the effective MOS transistor is obtained.
In the embodiment of the present invention, the MOS transistors (M5, M6, M7, M8) are generally constituted by a plurality of (e.g., 4) finger gates. A plurality of load currents corresponding to a plurality of finger gates are calculated for each of the effective MOS transistors formed of the plurality of finger gates, and the calculated plurality of load currents are used as the load currents of the effective MOS transistors.
Specifically, for example, for the effective MOS transistor M5, after finding the 1 st finger Gate (single Gate) of the effective MOS transistor M5 and the dispersion layer (active region) on the connection voltage AVDD side, at a place where the 1 st finger Gate (single Gate) and the dispersion layer (active region) intersect, a center point coordinate of a rectangular region for loading a load current is set by moving a predetermined distance to the dispersion layer (active region) side with the edge of the 1 st finger Gate (single Gate) as a starting point, and then based on the center point coordinate, the width of the 1 st finger Gate (single Gate) is taken as a long side of the rectangular region for loading a load current, the width is taken to be 5 to 10 nm, and the rectangular region for recording a load current is established on the dispersion layer (active region). Next, obtaining the load current I of the 1 st finger Gate in the established rectangular area according to the normalized load current I of the MOS transistor with the unit width-length ratio multiplied by the width-length ratio K of the 1 st finger Gate 1 And = k × I. Then repeating the above steps to obtain the load current I of other finger gates (single grid) of the effective MOSM5 in the established rectangular area 2 …I n . Calculating the load current I 1 …I n Set as the load current A of the effective MOS tube 5 。
Preferably, the invention relates the center point coordinate and the size of the rectangular region for loading the load current associated with the effective MOS tube M5, the process layer for placing the effective MOS tube M5, and the loadCurrent A 5 And storing the identifier of the effective MOS transistor M5 in association with the identifier.
With reference to the above processing procedure for the effective MOS transistor M5, the load currents a corresponding to the effective MOS transistors M6, M7, and M8 are calculated for the other effective MOS transistors M6, M7, and M8, respectively 6 、A 7 、A 8 。
Similarly, the coordinates and the size of the center point of the rectangular region for loading the load current, the process layer for placing the effective MOS transistors M6, M7, M8, and the load current a, which are respectively associated with the effective MOS transistors M6, M7, M8, can be preferably selected 6 、A 7 、A 8 And storing the identifiers of the effective MOS tubes M6, M7 and M8 in association with each other.
Fig. 4 shows an example of storing the above parameter information calculated for the extracted effective MOS transistors M5, M6, M7, M8, respectively: e1 to E12.
In step 103, voltage excitation is applied to the input end of the active MOS transistor, and based on the obtained load current corresponding to the active MOS transistor (i.e. the load current loaded at the circuit wiring position of the active MOS transistor), the resistor network extraction performed on the configuration region of the active MOS transistor is performed, and a resistor network matrix is established.
Specifically, in the present invention, voltage excitation is applied to the input terminals of the effective MOS transistors M5, M6, M7, M8, and the load currents a corresponding to the effective MOS transistors M5, M6, M7, M8 obtained in step 102 are respectively applied to the load currents a 5 、A 6 、A 7 、A 8 Extracting resistance information including metal (metal), via hole (via), contact hole (contact) and active area (dispersion) related to effective MOS tubes M5, M6, M7 and M8 in the integrated circuit layout, and establishing a resistance network matrix R:
Figure BDA0003979980370000071
wherein, theta 11 …θ nn The resistance values between nodes in the circuit wiring lines related to the effective MOS transistors M5, M6, M7, and M8 are shown.
In step 104, based on the established resistance network matrix R and the voltage excitation input to the effective MOS tube, the electrical index value related to the effective MOS tube for EM/IR analysis is calculated.
In the specific embodiment of the present invention, a matrix solver is called to solve according to the established resistance network matrix R, and the voltages and powers of the points in the circuit wiring related to the effective MOS transistors M5, M6, M7, and M8 are calculated.
Specifically, voltage excitation is applied to the input ends of the effective MOS transistors M5, M6, M7, and M8, and based on the resistance network R, the solution is obtained through kirchhoff equation:
Figure BDA0003979980370000081
wherein, P i Power, V, at each point in the circuit layout associated with the active MOS transistors M5, M6, M7, M8 i Voltage, θ, representing each point in the circuit wiring associated with the active MOS transistors M5, M6, M7, M8 ij The resistance values between the circuit wiring nodes of the effective MOS transistors M5, M6, M7, and M8 are shown, i, j =1 and 2 … n.
In the invention, the voltage value at two ends of each resistor is firstly obtained, the current flowing through each resistor is calculated, the power of each point is calculated according to the formula (1), and then the current density of the circuit wiring related to the effective MOS transistors M5, M6, M7 and M8 in the integrated circuit layout is calculated according to the voltage and the power.
In step 105, the results of the visual analysis of the EM/IR of the integrated circuit layout are output. .
In the specific implementation of the invention, after the solution is completed, the analysis result of the EM/IR characteristic visualization of the integrated circuit layout is output. The method specifically comprises the following steps: first, the analysis result of the voltage drop of the voltage AVDD is displayed, and as shown in fig. 5, different gray scales represent different voltage drop distributions; the second display current analysis result, as shown in fig. 6, displays the value and position of the voltage excitation applied to the active MOS transistor and the current value and position of the start end of the voltage AVDD; and thirdly, displaying the analysis result of the current density, as shown in fig. 7, displaying the current density of each layer of metal conductor and via hole in the integrated circuit layout so as to judge whether the power line and the via hole meet the requirement of the wafer foundry on the electromigration rate, and ensuring the safety of the chip design.
The method for quickly analyzing the EM/IR of the power source/ground layout according to the present invention is implemented, for example, by a computer terminal to which dedicated application software (a plurality of application programs such as the power source/ground layout designing program and the EM/IR for quickly analyzing the power source/ground layout according to the present invention) is installed. The computer terminal can implement each function described later, including hardware resources necessary for implementing each function, by executing processing related to a plurality of application programs. The computer terminal has an input device, a display device, an external I/F, a communication I/F, a processor, and a memory. These hardware components are connected to each other so as to be able to communicate via a bus.
The input device is, for example, a keyboard, a mouse, a touch panel, or the like. The display device is, for example, various types of flat panel displays.
The processor is a CPU in the computer or a processing component such as a special CPU, a DSP and the like. The Memory device includes a computer-readable storage medium, such as a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk.
The computer may communicate with the server over a network. The computer and the server can be respectively and independently used for executing the method for rapidly analyzing the power/ground layout EMIR provided by the application. The computer and the server can also be used for cooperatively executing the computer provided by the application. For example, the server may transmit to the computer the integrated circuit layout required for the rapid analysis of the power/ground layout EMIR method. The computer may also send the analysis results of the power/ground layout MIR to the server, etc.
In an embodiment, the present invention further provides an apparatus for rapidly analyzing EM/IR of a power/ground layout, which includes a processing unit, a storage unit, and a display unit, as shown in fig. 8, where the processing unit includes: the device comprises an extraction module 101, a load current loading module 102, a calculation module 103 and an output module 104. Wherein:
the extraction module 101 is used for screening and extracting effective MOS tubes in a normal saturation region working state;
a load current loading module 102, configured to obtain a load current corresponding to the effective MOS transistor by referring to a normalized load current of a preset MOS transistor of a unit size according to the extracted size of the effective MOS transistor, and load the obtained load current to a position where a power supply wiring of the effective MOS transistor is located;
a calculation module 103, which extracts a resistance network of the configuration region of the effective MOS transistor based on the loaded load current and establishes a resistance network matrix, and calculates an electrical index parameter for analyzing EM/IR in a circuit wiring related to the effective MOS transistor based on the resistance network matrix;
an output module 104 for outputting the result of the EM/IR analysis of the integrated circuit layout.
Other specific definitions of the apparatus for rapidly analyzing the EM/IR of the power source/ground layout according to the present invention may refer to the above definitions of the method for rapidly analyzing the EM/IR of the power source/ground layout according to the present invention, and are not described herein again. The various modules in the above-described apparatus for rapidly analyzing EM/IR of a power/ground layout may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment of the present invention, the present invention further provides a computer-readable storage medium having stored thereon a computer program which, when run, performs the method for fast analysis of EM/IR of an integrated circuit layout as described above.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A method for rapidly analyzing EM/IR of an integrated circuit layout, comprising:
(1) Searching MOS (metal oxide semiconductor) tubes connected with a power supply/ground network in the integrated circuit layout;
(2) Screening and extracting effective MOS tubes in a normal saturation region working state based on the searched MOS tubes;
(3) According to the size of the effective MOS tube, obtaining a load current corresponding to the effective MOS tube by referring to a preset normalized load current of the MOS tube with unit size, and loading the obtained load current and the obtained load current to the position of a power supply wiring of the effective MOS tube;
(4) Extracting a resistance network of a configuration area of the effective MOS tube based on the loaded load current and establishing a resistance network matrix;
(5) Calculating an electrical index parameter for analyzing EM/IR in circuit wiring related to the effective MOS tube based on the resistance network matrix; and
(6) And outputting the analysis result of the EM/IR of the integrated circuit layout.
2. A method for rapid EM/IR analysis of an integrated circuit layout according to claim 1,
for an effective MOS tube composed of a plurality of single grids, a plurality of load currents corresponding to the plurality of single grids are respectively calculated according to the size of the single grids, and the calculated plurality of load currents are used as the load currents of the effective MOS tube.
3. A method for rapid EM/IR analysis of an integrated circuit layout according to claim 1,
applying voltage excitation to the input end of the effective MOS tube, extracting resistance information which is relevant to the effective MOS tube and comprises metal, a through hole, a contact hole and an active region according to the load current loaded at the position of the effective MOS tube, and establishing a resistance network matrix based on the resistance information.
4. A method for rapid EM/IR analysis of an integrated circuit layout according to claim 1,
the step (5) comprises the following steps: using formulas
Figure FDA0003979980360000011
Calculating the voltage and power at each point in the circuit layout associated with the active MOS transistor, where P i Indicating the power, V, at each point in the circuit layout associated with an active MOS transistor i Indicating the voltage, theta, at each point in the circuit layout associated with an active MOS transistor ij Represents the resistance value between the circuit wiring nodes associated with the effective MOS transistors, i, j =1, 2 … n, and
and calculating the current density of the circuit wiring related to the effective MOS tube according to the voltage and the power.
5. An apparatus for rapidly analyzing EM/IR of an integrated circuit layout, comprising a processing portion, a storage portion connected to the processing portion, and a display portion, wherein the processing portion comprises:
the extraction module screens and extracts effective MOS tubes in a normal saturation region working state;
a load current loading module, which refers to a preset normalized load current of an MOS transistor with a unit size according to the extracted size of the effective MOS transistor, obtains a load current corresponding to the effective MOS transistor, and loads the obtained load current to a position where a power supply wiring of the effective MOS transistor is located;
the calculation module extracts a resistance network of the configuration area of the effective MOS tube based on the loaded load current, establishes a resistance network matrix, and calculates an electrical index parameter for analyzing EM/IR in circuit wiring related to the effective MOS tube based on the resistance network matrix;
and the output module is used for outputting the analysis result of the EM/IR of the integrated circuit layout.
6. A method for rapid EM/IR analysis of an integrated circuit layout according to claim 5,
for an effective MOS tube formed by a plurality of single grids, the load current loading module respectively calculates a plurality of load currents corresponding to the plurality of single grids according to the size of the single grid, and the calculated plurality of load currents are used as the load currents of the effective MOS tube.
7. A method for fast analysis of EM/IR of an integrated circuit layout according to claim 5,
applying voltage excitation to an input end of an effective MOS tube, extracting resistance information related to the effective MOS tube and comprising metal, a via hole, a contact hole and an active region according to a load current loaded at the position of the effective MOS tube, and establishing a resistance network matrix based on the resistance information.
8. A method for rapid EM/IR analysis of an integrated circuit layout according to claim 5,
the calculation module utilizes a formula
Figure FDA0003979980360000021
Calculating the voltage and power at each point in the circuit layout associated with the active MOS transistor, where P i Indicating the power, V, at each point in the circuit layout associated with an active MOS transistor i Indicating the voltage, theta, at each point in the circuit layout associated with an active MOS transistor ij Represents the resistance between the circuit wiring nodes associated with the active MOS transistors, i, j =1, 2 … n, and
and calculating the current density of the circuit wiring related to the effective MOS tube according to the voltage and the power.
9. A computer-readable storage medium having stored thereon a computer program which, when executed, performs the method for fast analysis of EM/IR of an integrated circuit layout as claimed in any one of claims 1-5.
CN202211546112.8A 2022-12-05 2022-12-05 Method, device and storage medium for rapidly analyzing EM/IR of integrated circuit layout Pending CN115796113A (en)

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CN116108802A (en) * 2023-04-12 2023-05-12 苏州珂晶达电子有限公司 Standard cell library determination method, device and system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116108802A (en) * 2023-04-12 2023-05-12 苏州珂晶达电子有限公司 Standard cell library determination method, device and system
CN116108802B (en) * 2023-04-12 2023-08-04 苏州珂晶达电子有限公司 Standard cell library determination method, device and system

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