CN117494654B - Voltage drop signing method, electronic equipment and storage medium - Google Patents
Voltage drop signing method, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN117494654B CN117494654B CN202311823654.XA CN202311823654A CN117494654B CN 117494654 B CN117494654 B CN 117494654B CN 202311823654 A CN202311823654 A CN 202311823654A CN 117494654 B CN117494654 B CN 117494654B
- Authority
- CN
- China
- Prior art keywords
- node
- voltage
- value
- confirming
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000003860 storage Methods 0.000 title claims abstract description 16
- 238000013178 mathematical model Methods 0.000 claims abstract description 21
- 238000004590 computer program Methods 0.000 claims description 11
- 238000013461 design Methods 0.000 claims description 9
- 230000003071 parasitic effect Effects 0.000 claims description 4
- 230000008439 repair process Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 14
- 238000004458 analytical method Methods 0.000 description 10
- 238000005295 random walk Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- 238000004891 communication Methods 0.000 description 8
- 239000011159 matrix material Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 238000004088 simulation Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 4
- 239000000047 product Substances 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 238000012790 confirmation Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 235000001892 vitamin D2 Nutrition 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000005094 computer simulation Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012886 linear function Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000010801 machine learning Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 230000001953 sensory effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The disclosure provides a voltage drop signing method, electronic equipment and a storage medium, and relates to the technical field of chips, wherein the method comprises the following steps: confirming at least one hot spot area in the chip based on an equivalent mathematical model corresponding to the chip; repairing the at least one hot spot area, and confirming the voltage parameter of the repaired first target node based on the voltage parameter of the adjacent node of the repaired first target node and the conductance value between the adjacent node and the first target node; responding to the condition that the voltage parameter is outside the target threshold, repairing the repaired first target node again, and confirming the voltage parameter of the repaired first target node for a plurality of times until the voltage parameter responding to the repaired first target node for a plurality of times is within the target threshold, and confirming that the voltage drop signing of the first target node is completed; therefore, the efficiency of voltage drop signing and checking can be improved, and the time and resources for using the voltage drop signing and checking are saved.
Description
Technical Field
The disclosure relates to the technical field of chips, and in particular relates to a voltage drop signing method, electronic equipment and a storage medium.
Background
The recent decades have seen a rapid development of digital integrated circuits by the continued advancement of semiconductor technology, which has presented greater challenges to designers as the integration level and complexity of integrated circuits have increased. Meanwhile, as integrated circuit processes enter ultra-deep submicron and nanometer orders of magnitude, power consumption and current density on a unit area are obviously increased, and the problems of voltage drop of a power supply network in an ultra-large-scale integrated circuit are caused; the voltage drop can reduce the operating voltage of the chip, leading to timing problems and potential functional failure risks.
In the related art, in order to ensure that mass-produced chips can stably work, a link for performing voltage drop analysis on the chips is added on the basis of the original front-end design and back-end design; the voltage drop of each node in the chip is determined by adopting a mode of solving a full chip by a large linear sparse equation set, and after repairing the illegal node, the voltage drop of each node in the full chip is solved again; however, with the development of integrated circuit processes, especially under deep submicron processes, tens of millions of nodes are included in a chip, and the solution of a full chip usually takes several hours to tens of hours, which is a great waste of time and resources.
Disclosure of Invention
The present disclosure provides a voltage drop signing method, an electronic device, and a storage medium, so as to at least solve the above technical problems in the prior art.
According to a first aspect of the present disclosure, there is provided a voltage drop signing method, including:
Confirming at least one hot spot area in the chip based on an equivalent mathematical model corresponding to the chip;
repairing the at least one hot spot area, and confirming the voltage parameter of the repaired first target node based on the voltage parameter of the adjacent node of the repaired first target node and the conductance value between the adjacent node and the first target node, wherein the voltage parameter comprises voltage and voltage drop;
Responding to the fact that the voltage parameter of the repaired first target node is outside the target threshold, repairing the repaired first target node again, and confirming the voltage parameter of the repaired first target node for a plurality of times until the voltage parameter of the repaired first target node is within the target threshold, and confirming that the voltage drop signing of the first target node is completed; wherein the first target node is any node in the at least one hotspot region.
According to a second aspect of the present disclosure, there is provided an electronic device comprising:
at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the present disclosure.
According to a third aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of the present disclosure.
A fourth aspect of the present disclosure provides a computer program product comprising a computer program/instruction which, when executed by a processor, implements the voltage drop checking method described above.
According to the voltage drop signing method, at least one hot spot area is confirmed based on an equivalent mathematical model corresponding to the chip; repairing the at least one hot spot area, and confirming the voltage parameter of the repaired first target node based on the voltage parameter of the adjacent node of the repaired first target node and the conductance value between the adjacent node and the first target node, wherein the voltage parameter comprises voltage and voltage drop; responding to the fact that the voltage parameter of the repaired first target node is outside the target threshold, repairing the repaired first target node again, and confirming the voltage parameter of the repaired first target node for a plurality of times until the voltage parameter of the repaired first target node is within the target threshold, and confirming that the voltage drop signing of the first target node is completed; wherein the first target node is any node in the at least one hotspot region; therefore, after full-chip analysis and repair, the full-chip analysis is not needed again, the voltage drop of any node in the hot spot area can be confirmed in a random walk mode, the voltage drop signing and checking efficiency is improved, and the time and resources for voltage drop signing and checking are saved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
FIG. 1 is a schematic diagram of an alternative flow of a voltage drop signature method provided by an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of another alternative flow of the voltage drop signature method provided by embodiments of the present disclosure;
FIG. 3 shows a schematic diagram of a simplified model of a build chip provided by an embodiment of the present disclosure;
FIG. 4 shows an equivalent circuit model of a chip power supply network provided by an embodiment of the present disclosure;
FIG. 5 illustrates a schematic diagram of a chip hotspot region provided by an embodiment of the present disclosure;
FIG. 6 shows a schematic diagram of node x and its neighboring nodes;
fig. 7 illustrates an alternative structural schematic diagram of a voltage drop signing device provided by an embodiment of the present disclosure;
fig. 8 shows a schematic diagram of a composition structure of an electronic device according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
In the following description, the terms "first", "second", and the like are merely used to distinguish between similar objects and do not represent a particular ordering of the objects, it being understood that the "first", "second", and the like may be interchanged with one another, if permitted, in order to enable the disclosed embodiments described herein to be implemented in an order other than that illustrated or described herein; a plurality to two or more.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the present disclosure is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.
It should be understood that, in various embodiments of the present disclosure, the size of the sequence number of each implementation process does not mean that the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.
Before explaining the embodiments of the present disclosure in further detail, terms and terminology involved in the embodiments of the present disclosure are explained, and the terms and terminology involved in the embodiments of the present disclosure are applicable to the following explanation.
Voltage Drop (IR Drop) indicates a phenomenon that occurs when the voltage on the integrated circuit power and ground networks drops or rises. In integrated circuit designs, it is generally assumed that an ideal power supply is provided to provide infinite current to maintain a specific operating voltage across the entire chip, but in practice, the evolution of semiconductor processes into ultra-deep submicron, the current per unit area increases dramatically, and the width of metal interconnect lines becomes narrower and narrower, resulting in a significant increase in the resistance value on the power supply network, and the power supply current will lose voltage from the system power supply to the power supply terminal of the device, so there will be a certain voltage drop in the local area of the power supply network.
In the related art, a sparse matrix is adopted to solve the voltage of the full chip, voltage simulation of the full chip is required to be repeated, and a large amount of time is spent on similar designs, so that the embodiment of the disclosure provides a higher-efficiency method, the voltage drop of the local area to be repaired is solved through probability simulation by adopting a random walk voltage drop solving method, a huge node voltage linear equation set of the full chip power supply network is not required to be repeatedly constructed during signing, the voltage drop quick solving requirement is greatly improved, and engineering iteration efficiency is improved.
Fig. 1 is a schematic flow chart of an alternative voltage drop signing method according to an embodiment of the disclosure, and will be described according to the steps.
Step S101, confirming at least one hot spot area based on an equivalent mathematical model corresponding to the chip.
It should be noted that, the chips referred to in the embodiments of the present disclosure are chips in a broad sense, and include chip finished products or chip semi-finished products, such as circuits related to chips during the manufacturing process, and also included in the chips defined in the embodiments of the present disclosure.
In some embodiments, a simplified model corresponding to the chip is obtained based on a physical design layout of the chip; and acquiring an equivalent mathematical model corresponding to the chip based on the simplified model. In the equivalent mathematical model, the network corresponding to the chip is a linear system, and the voltage parameter of each node in the chip can be confirmed based on the conductance matrix and the current source vector corresponding to each node, wherein the voltage parameter comprises a voltage value or a voltage drop.
And confirming at least one hot spot area based on the voltage parameter of each node and the target threshold, specifically, confirming at least one hot spot area in the chip based on the voltage value of each node and the first preset threshold. The voltage value of the node in the hot spot area is smaller than a first preset threshold value. Or determining at least one hot spot area in the chip based on the voltage drop of each node and a second preset threshold, wherein the voltage drop of the node in the hot spot area is larger than the second preset threshold.
In some embodiments, the voltage drop is the difference between the node voltage and the current source voltage.
Step S102, repairing the at least one hot spot area, and confirming the voltage parameter of the repaired first target node based on the voltage parameter of the adjacent node of the repaired first target node and the conductance value between the adjacent node and the first target node.
In some embodiments, the corresponding repair policy may be confirmed based on the violation condition of the hotspot area, and the hotspot area may be repaired based on the repair policy; the different violations correspond to at least one repair strategy that includes at least one of modifying a place and route, increasing a power supply point, modifying a location of a violation instance, replacing cell currents of different drive capabilities, and increasing decoupling capacitance (Decoupling Capacitor, decap), among others.
In some embodiments, taking the first target node as an example, the voltage drop of the first target node is greater than the second preset threshold, or the voltage value of the first target node is less than the first preset threshold, to indicate that the first target node has a voltage drop, that is, a violation exists; and confirming a repair strategy based on the violation characteristics of the first target node violation, and repairing the first target node violation based on the repair strategy.
In some embodiments, it is necessary to confirm whether the repaired first target node still has a voltage drop, but since the chip is physically modified during the repair process, the voltage of most nodes in the chip is changed from known to unknown, and only the voltages of the node corresponding to the current source and the ground node are known, it is necessary to confirm the unknown voltage from the known voltage in a recursive manner.
In the specific implementation, confirming the voltage parameter of the repaired first target node based on the voltage parameter of the adjacent node of the repaired first target node and the conductance value between the adjacent node and the first target node; if the voltage parameters of the adjacent nodes of the first target node are unknown, confirming the voltage parameters of the node based on the voltage parameters of the adjacent nodes of the node and the conductance value between the nodes; and confirming the voltage parameter of the first template node until the voltage parameter of the adjacent node is known. The voltage parameter here may be a voltage value.
And step S103, repairing the repaired first target node again in response to the fact that the voltage parameter of the repaired first target node is outside the target threshold, and confirming the voltage parameter of the repaired first target node for a plurality of times until the voltage parameter of the repaired first target node is within the target threshold in response to the fact that the voltage drop of the first target node is confirmed to be checked.
In some embodiments, after the first target node repairs and reacquires the voltage parameter of the first target node, determining whether the voltage drop still exists in the repaired first target node, responding to the fact that the voltage parameter of the repaired first target node is outside the target threshold, indicating that the voltage drop still exists in the repaired first target node, determining a repair strategy based on the violation characteristics, repairing the violation of the first target node based on the repair strategy again, and then determining the voltage parameter of the first target node again until the voltage parameter of the first target node is within the target threshold, and determining that the voltage drop signing of the first target node is completed, namely that the voltage drop does not exist in the first target node.
The target threshold comprises a first preset threshold and a second preset threshold; the voltage parameter is outside the target threshold, including that the voltage is smaller than a first preset threshold or the voltage drop is larger than a second preset threshold; correspondingly, the voltage parameter is within the target threshold, including the voltage being greater than a first preset threshold or the voltage drop being less than a second preset threshold.
Therefore, according to the voltage drop signing and checking method provided by the embodiment of the disclosure, after full chip analysis and restoration, the full chip analysis is not required to be carried out again, the voltage drop of any node in the hot spot area can be confirmed in a random walk mode, the voltage drop signing and checking efficiency is improved, and the time and resources for using the voltage drop signing and checking are saved.
Fig. 2 is a schematic diagram showing another alternative flow of the voltage drop signing method according to the embodiment of the present disclosure, and will be described according to the steps.
Step S201, a simplified model of the chip is confirmed.
In some embodiments, each of the simulation tools and analysis tools rely on modeling the behavior of its components, which cannot be simulated without modeling. Also, voltage drop analysis requires a set of models to accurately model the behavior of standard cell, input/Output (IO) blocks, memory, etc. Voltage drop analysis requires solving g×v=i, so the physical implementation is modeled as a resistive-capacitive matrix and a current model. Wherein G is a conductance value, V is a node voltage value, and I is a current value.
Fig. 3 shows a schematic diagram of a simplified model of a build chip provided by an embodiment of the disclosure.
In some embodiments, as shown in fig. 3, power is a Power supply, group is a Ground line or a digital Ground line, and the simplified model includes a resistor-capacitor model and a current source model, that is, a resistor-capacitor model is confirmed based on wiring punching of a Power supply network; validating the current source model based on the cell circuit; further, parasitic parameters are extracted from the physical design layout of the chip, and a resistance-capacitance model corresponding to the chip is confirmed; modeling a gate electrode circuit in the chip to obtain a current source model; confirming a simplified model of the chip based on the power supply network, the resistance capacitance model and the current source model; in fig. 3 AND is an AND gate (implementing a logical function AND), BUF is a logic function for directly transferring an input signal to an output port.
Fig. 4 shows an equivalent circuit model of a chip power supply network provided by an embodiment of the present disclosure.
In specific implementation, as shown in fig. 4, a device in a chip is packaged to form a Package, parasitic parameters are extracted from a physical design layout of the chip to obtain a power supply network (VDD grid), namely the device, working voltage inside the device, and a Resonant Cavity (RC) network of a digital ground wire (GND gird), namely a resistor-capacitor model; modeling the gate electrode circuit to obtain a static or dynamic current source model.
Step S202, confirming an equivalent mathematical model of the chip.
In some embodiments, an equivalent mathematical model corresponding to the chip is validated based on the reduced model.
In some embodiments, the simplified model is a linear system corresponding to a chip, for analysis of static voltage drop, the power supply network adopts a pure resistor network, and the calculation formula of the node voltage is as follows:
G × V = b（1）
g is the node conductance matrix, b is the current source vector, and V is the solved voltage values of all nodes of the power supply network.
Wherein, the conductance matrix is extracted from the resistance, specifically comprising: a typical rectangular region of metal or polysilicon layer, the resistance of which can be calculated as r=rsl/W, where Rs is the rectangular region resistance, depending on the material used; l is the length along the current direction region and W is the width of the verify current direction region. If the resistance region is not a standard rectangular region, the resistance value of each metal segment is calculated by correction.
Modeling of the current source comes from unit circuit simulation, specifically, a gate circuit is added with a certain excitation and load, and the current waveform of the power supply port can be measured.
Because of the large scale of the chip Power network, which has tens of millions to hundreds of millions nodes in the prior art, and the presence of many linearized switching devices in the network, equation (1) is actually a huge linear equation set that represents a P/G network (Power/group Power network), typically containing tens of millions of unknowns (e.g., the current 14nm mobile phone chip, each with tens of millions of gates), and current circuit analysis software has difficulty in simulating such complex systems. Therefore, the analysis problem of the P/G network is the problem of quickly solving the oversized linear sparse equation set.
The method comprises the following steps of generating a current source model, wherein the current source model comprises a static simulation equivalent mathematical model and a dynamic simulation equivalent mathematical model; the static current source model refers to a current source model at a single moment, the dynamic current source model refers to a current source model at a plurality of moments, and the static current source model or the dynamic current source model can be selected based on requirements in practical application; if the dynamic current source model is selected, the node voltage parameter at each moment needs to be confirmed.
Step S203, the voltage parameter of each node in the chip is confirmed.
In some embodiments, the voltage value of each node in the equivalent mathematical model is solved based on equation (1), and the chip corresponding hotspot region and the voltage drop hotspot map are confirmed based on a numerical comparison result between the voltage value of each node and the target threshold.
In the implementation, confirming the voltage value of each node in the chip based on the conductance value and the current value corresponding to each node in the equivalent mathematical model; and determining the region corresponding to the node with the voltage value smaller than the first preset threshold value as a hot spot region, or determining the region corresponding to the node with the voltage drop larger than the second preset threshold value as a hot spot region.
The target threshold comprises a first preset threshold and a second preset threshold; the voltage parameter is outside the target threshold, and comprises that the voltage is smaller than a first preset threshold or the voltage drop is larger than or equal to a second preset threshold; correspondingly, the voltage parameter is within the target threshold, including the voltage being greater than a first preset threshold or the voltage drop being less than a second preset threshold.
FIG. 5 is a schematic diagram of a hot spot area of a chip according to an embodiment of the present disclosure, wherein a node where two lines intersect represents one node, and the node that is elliptical is a node whose voltage is lower than a first preset threshold; the elliptical area is a hot spot area.
And step S204, repairing the illegal node.
In some embodiments, the different violations correspond to at least one repair policy that includes at least one of modifying layout routing, increasing power supply points, modifying locations of violations, replacing cell currents for different drive capabilities, and increasing decap capacitance.
In some embodiments, taking the first target node violation as an example, the voltage value of the first target node is smaller than a first preset threshold value, which indicates that the first target node has a voltage drop, that is, a violation exists; and confirming a repair strategy based on the violation characteristics of the first target node violation, and repairing the first target node violation based on the repair strategy.
Step S205, the voltage parameter of the repaired node is confirmed.
The gist of the embodiment of the present disclosure is to avoid reconfirming the voltage value of the full-chip node after repair, so that after repair, the voltage value of a certain node is separately confirmed by the method provided by the embodiment of the present disclosure. The following description will take, as an example, confirming the voltage value of the repaired first target node:
In some embodiments, the voltage value of the first target node is validated based on the conductance values between the first target node and all nodes adjacent thereto, and the voltage values of all nodes adjacent to the first target node, and the current value of the first target node.
Fig. 6 shows a schematic diagram of node x and its neighboring nodes.
In specific implementation, based on the voltage values of all nodes adjacent to a first target node, the conductance values between the first target node and all nodes adjacent to the first target node are confirmed, and a third voltage value corresponding to the first target node is confirmed; confirming a fourth voltage value corresponding to a first target node based on the conductance values between the first target node and all nodes adjacent to the first target node and the current value of the first target node; and confirming the difference between the third voltage value of the first target node and the fourth voltage value of the first target node as the voltage value of the first target node. The specific deduction process is as follows:
As shown in fig. 6, node 1, node 2, node 3, and node 4, a total of 4 nodes are adjacent to node x; i1, I2, I3 and I4 are current values corresponding to the node 1, the node 2, the node 3 and the node 4 respectively; g1, g2, g3 and g4 are conductance values between node 1, node 2, node 3 and node 4, respectively, and node x; according to kirchhoff's law, for any node, the current that it flows out is equal to the sum of the currents that flow into that node. Setting up Is the voltage (or voltage value) of node x,/>For the voltage of node i (i=1, 2,3, 4),For the conductance value between node i and node x, based on the base Huo Fugong, the following conclusions are drawn:
（2）
Wherein, For the current value flowing out of the node x, N is the total number of nodes adjacent to the node x, and n=4 in fig. 6.
Transforming the formula (2) to obtain:
（3）
from equation (3), it can be derived that the voltage value of any node in the path is a linear function of the voltage values of its neighboring nodes, letting:
（4）
（5）
thus, the problem of solving the voltage value of the node x is a random walk problem, Probability of being a graph edge (i.e., probability of going from neighbor node i to node x)/>Is penalty (i.e. voltage drop), i.e. the cost to pay to walk from node i to node x, the ideal state of the benefit m0=vdd (i.e. without any cost or voltage drop), further equation (3) can be transformed into:
（6）
In some embodiments, since the voltage values of most nodes in the chip become unknown, nodes with known voltage values need to be recursively obtained by using the nodes with known voltage values, so that all paths formed by at least two nodes from a first target node to a second target node are confirmed; the second target node is a node with known voltage, such as a current source node or a ground node.
In some embodiments, a first target node may be determined as a starting point, a second target node may be determined as an ending point, all paths between the first target node and the second target node are determined, nodes forming all paths are not identical, for example, according to the first target node as the starting point, the second target node may determine 4 paths L1, L2, L3 and L4 by taking the second target node as the ending point, and the first path L1 includes the first target node, the node a, the node a+1, … … and the second target node; the second path L2 includes a first target node, a node b, a node b+1, … … second target nodes; the third path L3 includes a first target node, a node c, a node c+1, … … second target nodes; the fourth path L4 includes the first target node, the node d, the node d+1, … … and the second target node; the number of nodes in each path is not necessarily the same, and there may be the same node or different nodes in each path.
Then, based on a formula (6), respectively confirming a voltage calculation formula of each node in each path, and then bringing the voltage value into the formula for deduction until alternative voltage values calculated by the first target node in different paths are calculated and averaged to obtain the voltage value of the first target node.
In some embodiments, confirming a voltage value calculation formula of all nodes in any path based on a formula (6), and then reversely bringing the voltage value calculation formula of all nodes in the path with the end point of the path, namely the voltage value of the second target node, to obtain the voltage value of all nodes in the path and the alternative voltage value of the first target node; and obtaining alternative voltage values of the first target nodes in all paths based on the scheme, and averaging to obtain the voltage values of the first target nodes.
In the implementation, taking two adjacent nodes in any path as an example, confirming all paths from the first target node to the second target node in the chip; wherein the voltage value of the second target node is known; the second node is a node on any path in all paths, and at least one first node is a node adjacent to the second path, and may or may not be on the path; confirming the voltage value of the second node based on the voltage value of at least one first node, the conductance value between the at least one first node and the second node and the current value of the second node until at least one alternative voltage value corresponding to the first target node in all paths is confirmed; confirming the average value of the at least one alternative voltage as the voltage value of the repaired first target node; wherein the voltage value of the first node is known and the voltage value of the second node is unknown.
Specifically, based on the voltage value of the at least one first node, the conductance value between the at least one first node and the second node confirms the first voltage value corresponding to the second node; confirming a second voltage value corresponding to a second node based on the conductance value between the at least one first node and the second node and the current value of the second node; and confirming the difference between the first voltage and the second voltage as the voltage value of the second node.
Confirming the probability of the second node moving to any of the first nodes (i.e) The product between the voltage values of the respective first nodes is the sub-voltage value corresponding to the second node (i.e./>) ; Confirming the sum of all sub-voltage values corresponding to the second node as the first voltage value corresponding to the second node (i.e./>）。
In some embodiments, after confirming the voltage value of the first target node, comparing the voltage value with a first preset threshold, if the voltage value of the first target node is greater than the first preset threshold, executing step S206, or if the voltage value of the first target node is less than the first preset threshold, repeatedly executing steps S204 to S205 until the voltage value of the first target node is greater than the first preset threshold, executing step S206.
Step S206, voltage drop signing is completed.
In some embodiments, in response to the voltage value of the first target node being greater than the first preset threshold, it is determined that the first target node completes voltage drop signing, and signing may be performed on nodes in other hot spot areas in the chip based on steps S204 to S205 until all nodes in the chip complete signing.
In this way, the embodiment of the disclosure provides a voltage drop signing and checking method, which solves the voltage value of the required node through probability simulation without constructing a huge node voltage linear equation set of the whole power supply network for many times and adopting a direct method and an iteration method of a traditional sparse matrix for solving, so that the local solving speed is very high, the requirement of the voltage drop quick solving is greatly improved, and the engineering iteration efficiency is improved.
In some embodiments, the execution subject of steps S101 to S103, and steps S201 to S206 may include one of a terminal device, a server, a processor, a chip, and an on-chip processor (e.g., a central processor inside a system-on-chip).
Fig. 7 is a schematic diagram showing an alternative structure of the voltage drop signing device according to the embodiment of the present disclosure, and will be described according to various parts.
In some embodiments, the voltage drop signing device 600 includes a hotspot region confirmation unit 601, a random walk unit 602, and a signing unit 603.
The hot spot area confirming unit 601 is configured to confirm at least one hot spot area in the chip based on an equivalent mathematical model corresponding to the chip.
The random walk unit 602 is configured to repair the at least one hot spot area, and confirm the voltage parameter of the repaired first target node based on the voltage parameter of the repaired first target node and the conductance value between the adjacent node and the first target node.
The signing unit 603 is configured to, in response to the voltage parameter of the repaired first target node being outside the target threshold, repair the repaired first target node again, and confirm the voltage parameter of the repaired first target node multiple times until the voltage parameter of the repaired first target node is within the target threshold, and confirm that voltage drop signing of the first target node is completed. Wherein the first target node is any node in the at least one hotspot region.
The hotspot area confirmation unit 601 is further configured to perform parasitic parameter extraction on a physical design layout of the chip before confirming at least one hotspot area in the chip based on an equivalent mathematical model corresponding to the chip, and confirm a power supply network and a resistor-capacitor model corresponding to the chip; modeling a gate electrode circuit in the chip to obtain a current source model; confirming a simplified model of the chip based on the power supply network, the resistance capacitance model and the current source model; and confirming an equivalent mathematical model corresponding to the chip based on the simplified model.
The hotspot area confirming unit 601 confirms a voltage value of each node in the chip based on a conductance value and a current value corresponding to each node in the equivalent mathematical model; determining that a region corresponding to a node with voltage smaller than a first preset threshold value in the voltage parameter is a hot spot region, or determining that a region corresponding to a node with voltage drop larger than a second preset threshold value in the voltage parameter is a hot spot region; the hot spot area is an area formed by at least one node in the chip, and the voltage parameter of the node in the hot spot area is outside the target threshold.
The random walk unit 602 is specifically configured to confirm that all paths formed by at least two nodes in the chip from the first target node to the second target node after repair are started; wherein the voltage parameter of the second target node is known; confirming the voltage value of the second node based on the voltage value of at least one first node, the conductance value between the at least one first node and the second node and the current value of the second node until at least one alternative voltage value corresponding to the first target node in all paths is confirmed; confirming the average value of the at least one alternative voltage value as the voltage value of the repaired first target node; the second node is any node on at least one path in the all paths, the first node and the second node are adjacent nodes, the voltage value of the first node is known, and the voltage value of the second node is unknown.
The random walk unit 602 is specifically configured to confirm a first voltage value corresponding to a second node based on a voltage value of the at least one first node, and a conductance value between the at least one first node and the second node; confirming a second voltage value corresponding to a second node based on the conductance value between the at least one first node and the second node and the current value of the second node; and confirming the difference between the first voltage and the second voltage as the voltage value of the second node.
The random walk unit 602 is specifically configured to confirm that a product between a probability that the second node moves to any one of the first nodes and a voltage value of the corresponding first node is a sub-voltage value corresponding to the second node; confirming the sum of all sub-voltage values corresponding to the second node as a first voltage value corresponding to the second node; wherein the probability of the second node moving to any one of the first nodes is determined based on the conductance value between the at least one first node and the second node.
The random walk unit 602 is specifically configured to confirm that a ratio of a current value of the second node to a sum of conductance values between the at least one first node and the second node is a second voltage value corresponding to the second node.
According to embodiments of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.
Fig. 8 illustrates a schematic block diagram of an example electronic device 800 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 8, the electronic device 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.
Various components in electronic device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the electronic device 800 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.
The computing unit 801 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the respective methods and processes described above, such as the voltage drop check method. For example, in some embodiments, the voltage drop signature method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 800 via the ROM 802 and/or the communication unit 809. When a computer program is loaded into RAM 803 and executed by computing unit 801, one or more steps of the voltage drop checking method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the voltage drop signature method in any other suitable manner (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (10)
1. A voltage drop signing method, the method comprising:
confirming at least one hot spot area based on an equivalent mathematical model corresponding to the chip;
Repairing the at least one hot spot area, and confirming that all paths formed by at least two nodes are finished from a first target node to a second target node after repairing in the chip; confirming the voltage parameter of the repaired first target node based on the voltage parameter of the adjacent node of the first target node in the whole path and the conductance value between the adjacent node and the first target node, wherein the voltage parameter comprises voltage and voltage drop;
Responding to the fact that the voltage parameter of the repaired first target node is outside the target threshold, repairing the repaired first target node again, and confirming the voltage parameter of the repaired first target node for a plurality of times until the voltage parameter of the repaired first target node is within the target threshold, and confirming that the voltage drop signing of the first target node is completed;
Wherein the first target node is any node in the at least one hotspot region.
2. The method of claim 1, wherein prior to identifying at least one hot spot region based on the equivalent mathematical model corresponding to the chip, the method further comprises:
extracting parasitic parameters from a physical design layout of a chip, and confirming a power supply network and a resistance capacitance model corresponding to the chip;
modeling a gate electrode circuit in the chip to obtain a current source model;
Confirming a simplified model of the chip based on the power supply network, the resistance capacitance model and the current source model;
And confirming an equivalent mathematical model corresponding to the chip based on the simplified model.
3. The method of claim 1, wherein identifying at least one hot spot region based on the equivalent mathematical model corresponding to the chip comprises:
Confirming the voltage parameter of each node in the chip based on the conductance value and the current value corresponding to each node in the equivalent mathematical model;
Determining that a region corresponding to a node with voltage smaller than a first preset threshold value in the voltage parameter is a hot spot region, or determining that a region corresponding to a node with voltage drop larger than a second preset threshold value in the voltage parameter is a hot spot region;
The hot spot area is an area formed by at least one node in the chip, and the voltage parameter of the node in the hot spot area is outside the target threshold.
4. The method of claim 1, wherein the validating the voltage parameter of the repaired first target node based on the voltage parameter of the neighboring node of the first target node in the overall path and the conductance value between the neighboring node and the first target node comprises:
Confirming the voltage value of the second node based on the voltage value of at least one first node, the conductance value between the at least one first node and the second node and the current value of the second node until at least one alternative voltage value corresponding to the first target node in all paths is confirmed;
confirming the average value of the at least one alternative voltage value as the voltage value of the repaired first target node;
The second node is any node on at least one path in the all paths, the first node and the second node are adjacent nodes, the voltage value of the first node is known, the voltage value of the second node is unknown, and the voltage value of the second target node is known.
5. The method of claim 4, wherein said validating the voltage value of the second node based on the voltage value of the at least one first node, the conductance value between the at least one first node and the second node, and the current value of the second node, comprises:
Confirming a first voltage value corresponding to a second node based on a voltage value of the at least one first node and a conductance value between the at least one first node and the second node;
Confirming a second voltage value corresponding to a second node based on the conductance value between the at least one first node and the second node and the current value of the second node;
and confirming the difference between the first voltage value and the second voltage value as the voltage value of the second node.
6. The method of claim 5, wherein the validating the first voltage value corresponding to the second node based on the voltage value of the at least one first node and the conductance value between the at least one first node and the second node comprises:
Confirming that the product between the probability of the second node moving to any first node and the voltage value of the corresponding first node is the sub-voltage value corresponding to the second node;
confirming the sum of all sub-voltage values corresponding to a second node as a first voltage value corresponding to the second node;
wherein the probability of the second node moving to any one of the first nodes is determined based on the conductance value between the at least one first node and the second node.
7. The method of claim 5, wherein said validating a second voltage value corresponding to a second node based on a conductance value between said at least one first node and said second node, and a current value of said second node, comprises:
And confirming the ratio of the current value of the second node to the sum of the conductance values between the at least one first node and the second node as a second voltage value corresponding to the second node.
8. An electronic device, comprising:
At least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.
9. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-7.
10. A computer program product comprising a computer program which, when executed by a processor, implements the method of any of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311823654.XA CN117494654B (en) | 2023-12-28 | 2023-12-28 | Voltage drop signing method, electronic equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311823654.XA CN117494654B (en) | 2023-12-28 | 2023-12-28 | Voltage drop signing method, electronic equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117494654A CN117494654A (en) | 2024-02-02 |
| CN117494654B true CN117494654B (en) | 2024-05-14 |
Family
ID=89680350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311823654.XA Active CN117494654B (en) | 2023-12-28 | 2023-12-28 | Voltage drop signing method, electronic equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117494654B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104460226A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Automatic repair method of hot spots of photolithography technique |
| CN108170956A (en) * | 2017-12-28 | 2018-06-15 | 佛山中科芯蔚科技有限公司 | The sequential signing method and device of a kind of retention time |
| CN109344528A (en) * | 2018-10-22 | 2019-02-15 | 上海威固信息技术股份有限公司 | A method of by quickly estimation power voltage-drop to search design weak spot in chip layout design |
| CN110412417A (en) * | 2019-07-15 | 2019-11-05 | 中国人民解放军陆军工程大学 | Micro-grid data fault diagnosis method based on intelligent power monitoring instrument |
| CN111965523A (en) * | 2020-08-14 | 2020-11-20 | 上海兆芯集成电路有限公司 | Chip testing method |
| CN112115676A (en) * | 2020-09-29 | 2020-12-22 | 天津飞腾信息技术有限公司 | Static voltage drop repairing method, device, equipment and storage medium |
| CN116298830A (en) * | 2022-09-06 | 2023-06-23 | 联芸科技(杭州)股份有限公司 | Verification method and processing system of integrated circuit |
| CN117094276A (en) * | 2023-09-08 | 2023-11-21 | 昆腾微电子股份有限公司 | Timing sequence path repairing method and device, electronic equipment and storage medium |
-
2023
- 2023-12-28 CN CN202311823654.XA patent/CN117494654B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104460226A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Automatic repair method of hot spots of photolithography technique |
| CN108170956A (en) * | 2017-12-28 | 2018-06-15 | 佛山中科芯蔚科技有限公司 | The sequential signing method and device of a kind of retention time |
| CN109344528A (en) * | 2018-10-22 | 2019-02-15 | 上海威固信息技术股份有限公司 | A method of by quickly estimation power voltage-drop to search design weak spot in chip layout design |
| CN110412417A (en) * | 2019-07-15 | 2019-11-05 | 中国人民解放军陆军工程大学 | Micro-grid data fault diagnosis method based on intelligent power monitoring instrument |
| CN111965523A (en) * | 2020-08-14 | 2020-11-20 | 上海兆芯集成电路有限公司 | Chip testing method |
| CN112115676A (en) * | 2020-09-29 | 2020-12-22 | 天津飞腾信息技术有限公司 | Static voltage drop repairing method, device, equipment and storage medium |
| CN116298830A (en) * | 2022-09-06 | 2023-06-23 | 联芸科技(杭州)股份有限公司 | Verification method and processing system of integrated circuit |
| CN117094276A (en) * | 2023-09-08 | 2023-11-21 | 昆腾微电子股份有限公司 | Timing sequence path repairing method and device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117494654A (en) | 2024-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11847397B1 (en) | Barycenter compact model to determine IR drop exact solution for circuit network | |
| US11017149B2 (en) | Machine-learning design enablement platform | |
| CN110728096B (en) | Method for manufacturing integrated circuit and computing system for designing integrated circuit | |
| US9171124B2 (en) | Parasitic extraction in an integrated circuit with multi-patterning requirements | |
| CN112364213A (en) | Graph database-based power grid retrieval method and system | |
| US7827016B1 (en) | Simulating circuits by distributed computing | |
| US9177096B2 (en) | Timing closure using transistor sizing in standard cells | |
| US10558772B1 (en) | Partitioning a system graph for circuit simulation to obtain an exact solution | |
| US20220215152A1 (en) | Generation of layout including power delivery network | |
| KR100895260B1 (en) | Method of analyzing circuit model by reduction | |
| US9471733B1 (en) | Solving a circuit network in multicore or distributed computing environment | |
| US20060026540A1 (en) | Electro-migration (EM) and Voltage (IR) Drop Analysis of Integrated Circuit (IC) Designs | |
| US8850374B2 (en) | Method of reducing parasitic mismatch | |
| US8719760B1 (en) | Validating integrated circuit simulation results | |
| CN117494654B (en) | Voltage drop signing method, electronic equipment and storage medium | |
| US10216887B1 (en) | Methods, systems, and computer program products for implementing an electronic design with time varying resistors in power gating analysis | |
| CN115796113A (en) | Method, device and storage medium for rapidly analyzing EM/IR of integrated circuit layout | |
| US8984468B1 (en) | Method to adaptively calculate resistor mesh in IC designs | |
| CN113033128B (en) | Method for selecting initial value of Newton iteration in circuit simulation | |
| US9552453B1 (en) | Integrated circuit with power network aware metal fill | |
| CN117751364A (en) | Method and apparatus for electronic design automation | |
| JP2009276822A (en) | Semiconductor device design support device and semiconductor device design support method | |
| US20240028910A1 (en) | Modeling method of neural network for simulation in semiconductor design process, simulation method in semiconductor design process using the same, manufacturing method of semiconductor device using the same, and semiconductor design system performing the same | |
| Wu et al. | A Dynamic Capacitance Matching (DCM)-based Current Response Algorithm for Signal Line RC Network | |
| US10068044B1 (en) | System and method for efficient device testing and validation of fast transients |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |